AMD Athlon 6 User manual

AMD Athlon™ Processor Model 6
Revision Guide
Publication # 24332 Rev: E
Issue Date: December 2002
Preliminary Information

Preliminary Information
Trademarks
AMD, the AMD Arrow logo, AMD Athlon, and combinations thereof, are trademarks of Advanced Micro Devices,
Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of
their respective companies.
© 2001, 2002 Advanced Micro Devices, Inc.
All rights reserved.
The contents of this document are provided in connection with Advanced
Micro Devices, Inc. (“AMD”) products. AMD makes no representations or
warranties with respect to the accuracy or completeness of the contents of
this publication and reserves the right to make changes to specifications and
product descriptions at any time without notice. No license, whether express,
implied, arising by estoppel or otherwise, to any intellectual property rights
is granted by this publication. Except as set forth in AMD’s Standard Terms
and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims
any express or implied warranty, relating to its products including, but not
limited to, the implied warranty of merchantability, fitness for a particular
purpose, or infringement of any intellectual property right.
The AMD products described herein may contain design defects or errors
(“Product Errata”) that cause AMD products to deviate from published spec-
ifications. Currently characterized Product Errata may be available upon
request.
AMD’s products are not designed, intended, authorized or warranted for use
as components in systems intended for surgical implant into the body, or in
other applications intended to support or sustain life, or in any other applica-
tion in which the failure of AMD’s product could create a situation where per-
sonal injury, death, or severe property or environmental damage may occur.
AMD reserves the right to discontinue or make changes to its products at any
time without notice.

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24332E—December 2002 AMD Athlon™ Processor Model 6 Revision Guide
Preliminary Information
Revision History
Date Rev Description
December 2002 E Added errata #22–24.
July 2002 D Added errata #20 and #21.
October 2001 C
■Added silicon revision A5 information
■Added erratum #18 and #19
■Added Table 2: Cross-reference of Erratum to Processor Segments to include all processor
segments
■Updated reference documents listed in section 3.1
May 2001 B Initial public release.

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AMD Athlon™ Processor Model 6 Revision Guide 24332E—December2002
Preliminary Information
AMD Athlon™ Processor Model 6
Revision Guide
The purpose of the AMD Athlon™ Processor Model 6 Revision Guide is to communicate updated product
information on the AMD Athlon processor model 6 to designers of computer systems and software
developers. This revision guide applies to the AMD Athlon processor model 6, mobile AMD Athlon
processor model 6, and AMD Athlon MP processor model 6. This guide consists of three sections:
■Product Errata: This section, which starts on page 5, provides a detailed description of product
errata, including potential effects on system operation and suggested workarounds. An erratum is
defined as a deviation from the product’s specification. A product errata may cause the behavior of
the AMD Athlon processor model 6 to deviate from the published specifications.
■Revision Determination: This section, which starts on page 16, shows the AMD Athlon processor
model 6 identification numbers returned by the CPUID instruction for each revision of the
processor.
■Technical and Documentation Support: This section, which starts on page 17, provides a listing of
available technical support resources. It also lists corrections, modifications, and clarifications to
listed documents. Please refer to the data sheets listed in this section for product marking
information.
Revision Guide Policy
Occasionally AMD identifies deviations from or changes to the specification of the AMD Athlon
processor model 6. These changes are documented in the AMD Athlon™ Processor Model 6 Revision
Guide as errata. Descriptions are written to assist system and software designers in using the
AMD Athlon processor model 6 and corrections to AMD’s documentation on the AMD Athlon
processor model 6 are included. This release documents currently characterized product errata.

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24332E—December 2002 AMD Athlon™ Processor Model 6 Revision Guide
Preliminary Information
1 Product Errata
This section documents AMD Athlon™ Processor Model 6 product errata. The errata are divided into
categories to assist referencing particular errata. A unique tracking number for each erratum has been
assigned within this document for user convenience in tracking the errata within specific revision
levels. Table 1 cross-references the revisions of the processor to each erratum. An “X” indicates that
the erratum applies to the stepping. The absence of an “X” indicates that the erratum does not apply
to the stepping. Table 2 on page 6 cross-references erratum to each processor segment. An “X”
indicates that the erratum applies to the processor segment.
Note: There can be missing errata numbers. Errata that have been resolved from early revisions of the
processor have been deleted, and errata that have been reconsidered may have been deleted or
renumbered.
Table 1. Cross-Reference of Product Revision to Errata
Errata Numbers and Description
Revision
Numbers
A0 A2 A5
16 INVLPG Instruction Does Not Flush Entire Four-Megabyte Page Properly with
Certain Linear Addresses XX
17 Deadlock May Occur in a Two-Processor System in the Presence of Probe to
Memory- Mapped I/O XX X
18 Processor May Issue Non-Connect Bus Cycle After FID Special Cycle X X
19 Processor Does Not Support Reliable Microcode Patch Mechanism X
20 Processor Performance Counters Do Not Count Some x86 Instructions X X X
21 A Speculative SMC Store Followed by an Actual SMC Store May Cause One-
Time Stale Execution XX X
22 Real Mode RDPMC with Illegal ECX May Cause Unpredictable Operation X X X
23 Using Task Gates With Breakpoints Enabled May Cause Unexpected Faults X X X
24 Single Step Across I/O SMI Skips One Debug Trap X X X

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AMD Athlon™ Processor Model 6 Revision Guide 24332E—December2002
Preliminary Information
Table 2. Cross-Reference of Erratum to Processor Segments
Errata
Number Workstation/Server1Desktop2Mobile3
16 XXX
17 X
18 X
19 XXX
20 XXX
21 XXX
22 XXX
23 XXX
24 XXX
Notes:
1. The workstation/server segment currently includes the AMD Athlon™ MP processor.
2. The desktop segment currently includes the AMD Athlon XP processor.
3. The mobile segment currently includes the AMD Athlon 4 processor.

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24332E—December 2002 AMD Athlon™ Processor Model 6 Revision Guide
Preliminary Information
16 INVLPG Instruction Does Not Flush Entire Four-Megabyte Page Properly with Certain
Linear Addresses
Products Affected. A0, A2
Normal Specified Operation. After executing an INVLPG instruction the TLB should not contain any
translations for any part of the page frame associated with the designated logical address.
Non-conformance. When the logical address designated by the INVLPG instruction is mapped by a 4-
Mbyte page mapping and LA[21] is equal to one it is possible that the TLB will still retain translations
after the instruction has finished executing.
Potential Effect on System. The residual data in the TLB can result in unexpected data access to stale or
invalid pages of memory.
Suggested Workaround. When using the INVLPG instruction in association with a page that is mapped via
a 4-Mbyte page translation, always clear bit 21.
Resolution Status. Fix planned for a future revision.

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AMD Athlon™ Processor Model 6 Revision Guide 24332E—December2002
Preliminary Information
17 Deadlock May Occur in a Two-Processor System in the Presence of Probe to Memory-
Mapped I/O
Products Affected. A0, A2, A5
Normal Specified Operation. Processor should not hang.
Non-conformance. In a multiprocessor system, if one processor (A) is continuously writing to a cacheable
memory-mapped I/O block while the other processor (B) is trying to read the same cacheable I/O block,
and at the same time both processors are also trying to write a different memory-based cache block,
then processor B may hang. Should this occur and processor A fields an interrupt, the deadlock will be
resolved.
Potential Effect on System. System will hang or exhibit performance degradation.
Suggested Workaround. The current processor design assumes that memory-mapped I/O is incoherent and
does not handle all deadlock cases. System logic should not generate probes for memory mapped I/O
addresses.
Resolution Status. No fix planned.

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24332E—December 2002 AMD Athlon™ Processor Model 6 Revision Guide
Preliminary Information
18 Processor May Issue Non-Connect Bus Cycle After FID Special Cycle
Products Affected. A0, A2
Normal Specified Operation. The first processor cycle after a FID Change special cycle should be a Connect
special cycle.
Non-conformance. In rare circumstances, a processor victim write may be pending inside the processor
when the FID Change special cycle is issued. Several bus clocks later, the WrVictimBlk command for
the victim will be issued. This violates the specification, which states that all processor-based
commands should be finished before the FID change special cycle.
Potential Effect on System. The core logic may become confused.
Suggested Workaround. System core logic can wait for numerous bus clocks after receiving the FID change
special cycle before attempting to disconnect in order to generate a window sufficiently large enough
to allow the WrVictimBlk transaction to take place prior to the disconnect.
Resolution Status. Fix planned for a future revision.

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AMD Athlon™ Processor Model 6 Revision Guide 24332E—December2002
Preliminary Information
19 Processor Does Not Support Reliable Microcode Patch Mechanism
Products Affected. A5
Normal Specified Operation. The processor should function properly after a microcode patch is loaded.
Non-conformance. The processor has the patch RAM BIST function disabled. Since BIST is not run on the
patch RAM, reliable operation of the patch RAM cannot be guaranteed. Therefore it should not be
used.
Potential Effect on System. When a microcode patch is loaded, the system may not behave properly.
Suggested Workaround. Do not load a microcode patch.
Resolution Status. Fix planned for a future revision.