Analog Devices Blackfin ADSP-BF537 Application guide

ADSP-BF537 Blackfin®Processor
Hardware Reference
Revision 2.0, December 2005
Part Number
82-000555-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106 a

Copyright Information
© 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu-
ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
Disclaimer
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prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
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Trademark and Service Mark Notice
The Analog Devices logo, Blackfin, the Blackfin logo, CrossCore, EZ-KIT
Lite, SHARC, TigerSHARC, and VisualDSP++ are registered trademarks
of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.

ADSP-BF537 Blackfin Processor Hardware Reference iii
CONTENTS
PREFACE
Purpose of This Manual ............................................................... xliii
Intended Audience ....................................................................... xliii
Manual Contents .......................................................................... xliv
What’s New in This Manual ......................................................... xlvii
Technical or Customer Support .................................................... xlvii
Supported Processors .................................................................. xlviii
Product Information ..................................................................... xlix
MyAnalog.com ........................................................................ xlix
Processor Product Information ................................................. xlix
Related Documents ..................................................................... l
Online Technical Documentation ............................................... li
Accessing Documentation From VisualDSP++ ....................... lii
Accessing Documentation From Windows ............................. lii
Accessing Documentation From the Web .............................. liii
Printed Manuals ....................................................................... liii
VisualDSP++ Documentation Set ......................................... liii
Hardware Tools Manuals ...................................................... liv
Processor Manuals ................................................................ liv
Data Sheets .......................................................................... liv

Contents
iv ADSP-BF537 Blackfin Processor Hardware Reference
Conventions .................................................................................... lv
Register Diagram Conventions .................................................. lvi
INTRODUCTION
Peripherals .................................................................................... 1-1
Memory Architecture .................................................................... 1-4
Internal Memory ..................................................................... 1-6
External Memory .................................................................... 1-6
I/O Memory Space .................................................................. 1-7
DMA Support .............................................................................. 1-7
External Bus Interface Unit ........................................................... 1-9
PC133 SDRAM Controller ..................................................... 1-9
Asynchronous Controller ........................................................ 1-9
Ports .......................................................................................... 1-10
General-Purpose I/O (GPIO) ................................................ 1-10
Two-Wire Interface ..................................................................... 1-11
Controller Area Network ............................................................ 1-12
Ethernet MAC ............................................................................ 1-14
Parallel Peripheral Interface ......................................................... 1-14
SPORT Controllers .................................................................... 1-16
Serial Peripheral Interface (SPI) Port ........................................... 1-18
Timers ....................................................................................... 1-18
UART Ports ............................................................................... 1-19
Real-Time Clock ........................................................................ 1-20
Watchdog Timer ......................................................................... 1-21

ADSP-BF537 Blackfin Processor Hardware Reference v
Contents
Clock Signals .............................................................................. 1-22
Dynamic Power Management ...................................................... 1-23
Full On Mode (Maximum Performance) ................................ 1-23
Active Mode (Moderate Power Savings) .................................. 1-23
Sleep Mode (High Power Savings) .......................................... 1-23
Deep Sleep Mode (Maximum Power Savings) ......................... 1-24
Hibernate State ..................................................................... 1-24
Voltage Regulation ...................................................................... 1-24
Boot Modes ................................................................................ 1-25
Instruction Set Description ......................................................... 1-27
Development Tools ..................................................................... 1-29
CHIP BUS HIERARCHY
Overview ...................................................................................... 2-1
Interface Overview ........................................................................ 2-3
Internal Clocks ........................................................................ 2-4
Core Bus Overview .................................................................. 2-4
Peripheral Access Bus (PAB) ..................................................... 2-6
PAB Arbitration .................................................................. 2-6
PAB Agents (Masters, Slaves) ............................................... 2-6
PAB Performance ................................................................ 2-7
DMA Access Bus (DAB), DMA Core Bus (DCB),
DMA External Bus (DEB) .................................................... 2-8
DAB Arbitration ................................................................. 2-8
DAB Bus Agents (Masters) .................................................. 2-9
DAB, DCB, and DEB Performance ................................... 2-10

Contents
vi ADSP-BF537 Blackfin Processor Hardware Reference
External Access Bus (EAB) .................................................... 2-10
Arbitration of the External Bus .............................................. 2-11
DEB/EAB Performance ......................................................... 2-11
MEMORY
Memory Architecture .................................................................... 3-1
L1 Instruction SRAM ................................................................... 3-5
L1 Data SRAM ............................................................................ 3-7
L1 Data Cache ............................................................................. 3-8
Boot ROM ................................................................................... 3-8
External Memory .......................................................................... 3-8
Processor-Specific MMRs .............................................................. 3-8
DMEM_CONTROL Register ................................................. 3-9
DTEST_COMMAND Register ............................................ 3-10
SYSTEM INTERRUPTS
Overview ...................................................................................... 4-1
Features .................................................................................. 4-1
Interfaces ...................................................................................... 4-2
Description of Operation .............................................................. 4-2
Events and Sequencing ............................................................ 4-2
System Peripheral Interrupts .................................................... 4-7
Programming Model ................................................................... 4-14
System Interrupt Initialization ............................................... 4-14
System Interrupt Processing Summary ................................... 4-14

ADSP-BF537 Blackfin Processor Hardware Reference vii
Contents
System Interrupt Controller Registers .......................................... 4-16
SIC_IARx Registers ............................................................... 4-18
SIC_IMASK Register ............................................................ 4-20
SIC_ISR Register .................................................................. 4-21
SIC_IWR Register ................................................................. 4-22
Programming Examples ............................................................... 4-23
Clearing Interrupt Requests ................................................... 4-23
DIRECT MEMORY ACCESS
Overview and Features .................................................................. 5-1
DMA Controller Overview ............................................................ 5-5
External Interfaces ................................................................... 5-6
Internal Interfaces ................................................................... 5-6
Peripheral DMA ...................................................................... 5-7
Memory DMA ........................................................................ 5-9
Handshaked Memory DMA Mode .................................... 5-11
Modes of Operation .................................................................... 5-12
Register-based DMA Operation ............................................. 5-12
Stop Mode ........................................................................ 5-13
Autobuffer Mode .............................................................. 5-14
Two-Dimensional DMA Operation ........................................ 5-14
Examples of Two-Dimensional DMA ................................ 5-15
Descriptor-based DMA Operation ......................................... 5-16
Descriptor List Mode ........................................................ 5-17
Descriptor Array Mode ..................................................... 5-18

Contents
viii ADSP-BF537 Blackfin Processor Hardware Reference
Variable Descriptor Size .................................................... 5-18
Mixing Flow Modes .......................................................... 5-19
Functional Description ............................................................... 5-20
DMA Operation Flow ........................................................... 5-20
DMA Startup ................................................................... 5-20
DMA Refresh ................................................................... 5-25
Work Unit Transitions ...................................................... 5-27
DMA Transmit and MDMA Source .............................. 5-28
DMA Receive ............................................................... 5-30
Stopping DMA Transfers .................................................. 5-31
DMA Errors (Aborts) ............................................................ 5-32
DMA Control Commands .................................................... 5-34
Restrictions ...................................................................... 5-38
Transmit Restart or Finish ............................................. 5-38
Receive Restart or Finish ............................................... 5-39
Handshaked Memory DMA Operation .................................. 5-40
Pipelining DMA Requests ................................................. 5-41
HMDMA Interrupts ......................................................... 5-43
DMA Performance ................................................................ 5-44
DMA Throughput ............................................................ 5-45
Memory DMA Timing Details .......................................... 5-48
Static Channel Prioritization ............................................. 5-48
Temporary DMA Urgency ................................................ 5-50
Memory DMA Priority and Scheduling ............................. 5-51
Traffic Control ................................................................. 5-53

ADSP-BF537 Blackfin Processor Hardware Reference ix
Contents
Programming Model ................................................................... 5-55
Synchronization of Software and DMA .................................. 5-56
Single-buffer DMA Transfers ............................................. 5-58
Continuous Transfers Using Autobuffering ........................ 5-58
Descriptor Structures ........................................................ 5-60
Descriptor Queue Management ......................................... 5-61
Descriptor Queue Using Interrupts on Every Descriptor 5-62
Descriptor Queue Using Minimal Interrupts .................. 5-63
Software Triggered Descriptor Fetches ............................... 5-65
DMA Registers ........................................................................... 5-67
DMA Channel Registers ........................................................ 5-68
DMAx_PERIPHERAL_MAP/
MDMA_yy_PERIPHERAL_MAP Registers ................... 5-71
DMAx_CONFIG/MDMA_yy_CONFIG Registers ........... 5-74
DMAx_IRQ_STATUS/
MDMA_yy_IRQ_STATUS Registers .............................. 5-78
DMAx_START_ADDR/
MDMA_yy_START_ADDR Registers ............................ 5-82
DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR
Registers ........................................................................ 5-83
DMAx_X_COUNT/MDMA_yy_X_COUNT Registers .... 5-85
DMAx_CURR_X_COUNT/
MDMA_yy_CURR_X_COUNT Registers ..................... 5-86
DMAx_X_MODIFY/
MDMA_yy_X_MODIFY Registers ................................ 5-88

Contents
x ADSP-BF537 Blackfin Processor Hardware Reference
DMAx_Y_COUNT/
MDMA_yy_Y_COUNT Registers ................................. 5-90
DMAx_CURR_Y_COUNT/
MDMA_yy_CURR_Y_COUNT Registers ..................... 5-91
DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY
Registers ........................................................................ 5-93
DMAx_NEXT_DESC_PTR/
MDMA_yy_NEXT_DESC_PTR Registers ..................... 5-94
DMAx_CURR_DESC_PTR/
MDMA_yy_CURR_DESC_PTR Registers .................... 5-96
HMDMA Registers ............................................................... 5-98
HMDMAx_CONTROL Registers .................................... 5-99
HMDMAx_BCINIT Registers ........................................ 5-101
HMDMAx_BCOUNT Registers .................................... 5-101
HMDMAx_ECOUNT Registers ..................................... 5-102
HMDMAx_ECINIT Registers ........................................ 5-103
HMDMAx_ECURGENT Registers ................................ 5-104
HMDMAx_ECOVERFLOW Registers ........................... 5-104
DMA Traffic Control Registers ............................................ 5-105
DMA_TC_PER Register ................................................ 5-105
DMA_TC_CNT Register ............................................... 5-106
Programming Examples ............................................................ 5-107
Register-Based 2D Memory DMA ....................................... 5-107
Initializing Descriptors in Memory ...................................... 5-111
Software-Triggered Descriptor Fetch Example ...................... 5-114
Handshaked Memory DMA Example .................................. 5-116