Analog Devices LTC6955 Quick setup guide

1
DEMO MANUAL DC2611A
Rev. 0
DESCRIPTION
LTC6955/LTC6955-1
Ultralow Jitter 11 Output
Fanout Buffer
Demonstration Circuit 2611A features the LT C
®
6955/
LTC6955-1, Ultralow Jitter 11 Output Fanout Buffers.
By default, the DC2611A is powered from a single 3.3V
supply. An option is provided to power to the DC2611A
from dual supplies, allowing for the LTC6955’s output
supply pins to connect to an LTC Silent Switcher
®
and the
LTC6955 input supply pin to connect to a low noise LDO.
The differential inputs and six of the differential outputs
are populated with 0.5" spaced SMA connectors. These
outputs are AC-coupled with 50Ω transmission lines
All registered trademarks and trademarks are the property of their respective owners.
making them suitable to drive 50Ω impedance instru-
ments. The remaining four differential outputs are termi-
nated with 100Ω.
A calibration path is provided to aid in accurate LTC6955
propagation delay measurements. The calibration path
can be also reconfigured as a DC path, which allows for
a convenient method of locking the LTC6955 outputs to
an external PLL/VCO, as shown in Figure2.
Design files for this circuit board are available.
Figure1. DC2611A Connections
CAL_IN,
SMA
Single Supply 3.3V Input,
banana jacks J27 & J28
OUT1, CML
AC-coupled
Outputs, SMA
OUT0, CML
AC-coupled
Outputs, SMA
CAL_OUT,
SMA
OUT8, CML
AC-coupled
Outputs, SMA
OUT10, CML
AC-coupled
Outputs, SMA
IN Input, SMA
VIN33 Option,
Refer to
DC2611 Reconfiguration
OUT6, CML
AC-coupled
Outputs, SMA
OUT4, CML
AC-coupled
Outputs, SMA
TEMP, turret
OUTPUT SEL,
Switches
FILT, Header

2
DEMO MANUAL DC2611A
Rev. 0
QUICK START PROCEDURE
The DC2611A is easy to set up to evaluate the perfor-
mance of the LTC6955. Follow the procedure below
DC2611A Configuration
1. Connect J27 and J28 to a power supply and apply power
(see Figure1 and the Typical DC2611A Requirements
and Characteristics table).
2. Connect a low phase-noise (or jitter) single-ended sig-
nal to IN–(J25). Refer to the LTC6955 data sheet for
acceptable input frequencies and amplitudes.
3. Connect desired output (OUT10, OUT8, OUT6, OUT4,
OUT1 or OUT0) to a test instrument or other demo
board to evaluate performance. Terminate the unused
outputs with 50Ω.
4. Ensure SW0:3 are configured to enable the desired
output. Setting SEL[3:1]=H and SEL0=L enables all
outputs. Refer to Table1 for a list of SEL[3:0] settings
vs output states.
Be sure to power down or terminate any unused RF output
with 50Ω, or poor spurious performance may result.
Troubleshooting
If the LTC6955 does not output a signal
1. Ensure LTC6955 input signal is connected to the
LTC6955 IN– pin, not the LTC6955 IN+ pin.
If DC2611A performance is less than the LTC6955 data
sheet specifications:
1. For unexpected spurious response, verify power sup-
plies are low noise and spurious free power supplies.
Power supplies that are based off a switching regulator
architecture are known to generate spurs on low jitter
clock outputs.
2. For poor phase noise results, verify the phase noise
specifications of the input signal and the phase noise
measurement instrument. Traditional signal sources
and spectrum analyzers have higher phase noise than
the LTC6955 and will degrade measurement results. To
measure phase noise performance it is recommended
to use a low jitter oscillator and a signal source analyzer,
such as Keysight’s (previously Agilent/HP) E5052.
3. Contact the factory for further troubleshooting.
Table1. LTC6955 SEL[3:0] Settings vs Output States
SEL[3:0]
TEMP
DIODE OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0
0x0 Pwrdn
0x1 ON ON Pwrdn ON Pwrdn ON Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn Pwrdn
0x2 ON ON Pwrdn ON Pwrdn ON Pwrdn ON Pwrdn Pwrdn Pwrdn Pwrdn
0x3 ON ON Pwrdn ON Pwrdn ON Pwrdn ON Pwrdn ON Pwrdn Pwrdn
0x4 ON ON ON ON Pwrdn ON Pwrdn ON Pwrdn ON Pwrdn Pwrdn
0x5 ON ON Inverted ON Pwrdn ON Pwrdn ON Pwrdn ON Pwrdn Pwrdn
0x6 ON ON ON ON ON ON Pwrdn ON Pwrdn ON Pwrdn Pwrdn
0x7 ON ON Inverted ON Inverted ON Pwrdn ON Pwrdn ON Pwrdn Pwrdn
0x8 ON ON ON ON ON ON ON ON Pwrdn ON Pwrdn Pwrdn
0x9 ON ON Inverted ON Inverted ON Inverted ON Pwrdn ON Pwrdn Pwrdn
0xA ON ON ON ON ON ON ON ON ON ON Pwrdn Pwrdn
0xB ON ON Inverted ON Inverted ON Inverted ON Inverted ON Inverted Pwrdn
0xC ON ON ON ON ON ON ON ON ON ON ON Pwrdn
0xD ON ON Inverted ON Inverted ON Inverted ON Inverted ON Inverted ON
0xE ON ON ON ON ON ON ON ON ON ON ON ON
0xF ON Pwrdn

3
DEMO MANUAL DC2611A
Rev. 0
DC2611A RECONFIGURATION
The following covers the hardware reconfiguration of the
DC2611A. Refer to LTC6955 data sheet for a better under-
standing of device specific considerations.
Power Supply Options
Table2 provides the power supply options for DC2611A.
By default the DC2611A is setup to use the single supply
option. However, a dual supply option is available to power
the higher current supply from our Silent Switcher, such
as the LT8609S. The Silent Switcher improves the power
efficiency over the low noise LDO. A spurious free supply,
such as a low noise LDO, is required on the LTC6955’s
VIN+supply pin.
Table2. Power Supply Options
Power Supply Voltage/Current
(Recommended Supply)
DEFAULT OPTION R18 J27 (3.3V) E10 (VIN33)
x Single
Supply
Installed 3.3V/750mA
(Low Noise LDO)
NA
Dual
Supply
Do Not
Install
3.3V/750mA
(Silent Switcher)
3.3V/150mA
(Low Noise LDO)
Input Termination Options
Table3 provides the single-ended and differential input
termination options. By default the DC2611A is setup for
a single-ended input on the IN–SMA (J25). For best per-
formance different termination networks are provided for
input signals <5GHz and input signals >5GHz.
LTC6955-1 Divide by Two Coupling Spur
To help reduce the LTC6955-1’s OUT10 /2 coupling spur
to other outputs a ferrite bead (FB1) should be installed
on the OUT10 supply pin, VOUT+ (Pin 5). For the LTC6955
FB1 should be a 0Ω resistor.
CML Outputs, OUT[10:0]
The DC2611A has 11 CML outputs. Six of these outputs
are AC-coupled and brought out to SMAs (OUT10, OUT8,
OUT6, OUT4, OUT1 or OUT0). To drive 50Ω impedance
instruments connect OUTx+ to the instrument and OUTx–
to a 50Ω termination, or vice versa.
The remaining five outputs (OUT9, OUT7, OUT5, OUT3,
and OUT2) are terminated with a 100Ω resistor on board.
To connect these outputs to a 50Ω instrument, remove
the 100Ω termination, and install the appropriate SMAs
and AC blocking capacitors.
Refer to LTC6955 data sheet for differential termination
options.
Alternate Configuration Options
To take advantage of the LTC6955’s maximum output
frequency and ultralow output additive phase noise,
the DC2611A (LTC6955, LTC6955-1), the DC2609A
(LTC6952) and the VCO rider board (DC2664A) were
designed to mate directly together, as shown in Figure2.
This setup allows for options to lock the LTC6952 refer-
ence input to:
A) A <7.5GHz VCO and LTC6955-1 output frequency, by
utilizing the LTC6955-1 divide by two output on OUT10
to drive the LTC6952 VCO input. (refer to Figure2)
B) Any VCO and create lower jitter clocks from a LTC6955
or LTC6955-1 output than a standalone LTC6952
produces.
Refer to the LTC6952 and LTC6955 data sheet’s typical
application for measured results. Refer to the DC2664A
demo manual for recommendation on loop filter compo-
nent placement.
Table3. Input Termination Options (*)
DEFAULT TERMINATION R8 (Ω) R9 (Ω) R10 (Ω) R11 (Ω) R19 (Ω) R20 (Ω) C58 C59 C60 C61
DC2611A-A SE, IN–, <5GHz 75 DNI 30 DNI DNI DNI 0.1uF 0.1uF DNI 0.1uF
DC2611A-B SE, IN–, ≥5GHz DNI DNI DNI 1nH DNI 49.9 DNI 1pF 1pF DNI
SE, IN+, <5GHz 30 DNI 75 DNI DNI DNI 0.1uF DNI 0.1uF 0.1uF
SE, IN+, ≥5GHz DNI DNI DNI 1nH 49.9 DNI DNI 1pF 1pF DNI
DIFF, CML or PECL, <5GHz DNI 160 DNI DNI DNI DNI DNI 0.1uF 0.1uF DNI
DIFF, CML or PECL, ≥5GHz DNI DNI DNI 1nH DNI DNI DNI 1pF 1pF DNI
DIFF, LVDS DNI DNI DNI 160 DNI DNI DNI 0.1uF 0.1uF DNI
*SE = Single-Ended, DIFF = Differential, DNI = Do Not Install

4
DEMO MANUAL DC2611A
Rev. 0
Change C56 & C57
to 0 ohm resistors
DC2611A RECONFIGURATION
Figure2. Alternate Configuration, Locking LTC6955 Outputs to an External PLL/VCO

5
DEMO MANUAL DC2611A
Rev. 0
TYPICAL DC2611A REQUIREMENTS AND CHARACTERISTICS
Table4.
PARAMETER INPUT OR OUTPUT PHYSICAL LOCATION DETAILS
3.3V Power Supply Input J27 and J28 BNC Banana Jacks If R18 populated, default option, single supply: 3.3V low-
noise and spur-free supply, 1A;
If R18 depopulated, dual supply option, allows for
experiments with more efficient power supply evaluation
(Silent Switcher).
See 3.3V power supply #2 (VIN33)
3.3V Power Supply #2 (VIN33) Input E10 Turret (VIN33) If R18 depopulated, dual supply option, 3.3v low-noise and
spur-free supply, 150mA;
OUT10+; OUT10– Two Outputs J1 and J2 SMA Connectors* CML, AC-coupled, 800mVP-P differential
OUT8+; OUT8– J5 and J6 SMA Connectors*
OUT6+; OUT6– J21 and J22 SMA Connectors*
OUT4+; OUT4– J17 and J18 SMA Connectors*
OUT1+; OUT1– J11 and J12 SMA Connectors*
OUT0+; OUT0– J9 and J10 SMA Connectors*
OUT9+; OUT9– Two Outputs
(Not Connected)
J3 and J4 (SMA Not Populated) On board differential 100Ω termination
OUT7+; OUT7– J7 and J8 (SMA Not Populated)
OUT5+; OUT5– J19 and J20 (SMA Not Populated)
OUT3+; OUT3– J15 and J16 (SMA Not Populated)
OUT2+; OUT2– J13 and J14 (SMA Not Populated)
IN+ Input
(Not Connected)
J26 SMA Connector Default: Not connected
(see Table3, for correct input termination options)
IN- Input J25 SMA Connector Default: Preferred single-ended input
(see Table3, for correct input termination options)
FILT Input, Center Pin JP1 3-Pin Header L(Default): FILT disabled, set by pull-down resistor
H: FILT enabled
TEMP Output E1 Turret (TEMP) Internal temperature diode
*Any unused RF output must be powered down or terminated with 50Ω, or poor spurious performance may result.
ASSEMBLY OPTIONS
Table5. DC2611A Assembly Options
ASSEMBLY VERSION U1 PART NUMBER
DC2611A-A LTC6955IUKG
DC2611A-B LTC6955IUKG-1

6
DEMO MANUAL DC2611A
Rev. 0
PCB LAYOUT
Top Layer

7
DEMO MANUAL DC2611A
Rev. 0
PARTS LIST
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
Required Circuit Components
1 15 C1, C2, C5, C6, C9-C12, C17, C18,
C21, C22, C50, C56, C57
CAP., X7R, 0.1µF, 10V, 10%, 0402 MURATA, GRM155R71A104KA01D
2 0 C3, C4, C7, C8, C13-C16, C19, C20 CAP., 0402 OPT
3 12 C25-C36 CAP., X7R, 0.01µF, 6.3V, 10%, 0201 MURATA, GRM033R70J103KA01D
4 11 C38-C48 CAP., X5R, 1µF, 16V, 10%, 0402 MURATA, GRM155R61C105KE01D
5 1 C49 CAP., X7R, 10µF, 25V, 10%, 1206 MURATA, GRM31CR71E106KA12L
6 1 C62 CAP., TANT., 330µF, 10V, 10%, 7343 AVX, TPME337K010R0035
7 10 E1-E10 TURRET, TESTPOINT 0.064" MILL-MAX, 2308-2-00-80-00-00-07-0
8 1 JP1 CONN., HEADER, MALE, 1X3, 2mm, THT WURTH ELEKTRONIK, 62000311121
9 16 J1, J2, J5, J6, J9-J12, J17, J18,
J21-J26
CONN., SMA 50Ω EDGE-LAUNCH, CON-SMA-R CCSJ, 142-0701-851
10 0 J3, J4, J7, J8, J13-J16, J19, J20 CONN., SMA 50Ω EDGE-LAUNCH, CON-SMA-R OPT
11 2 J27, J28 CONN, JACK, BANANA KEYSTONE, 575-4
12 2 R1, R2 RES., CHIP, 10k, 1/10W, 1% 0402 VISHAY, CRCW040210K0FKED
13 1 R3 RES., CHIP, 100k, 1/10W, 1% 0402 VISHAY, CRCW0402100KFKED
14 5 R4, R5, R6, R7, R12 RES., CHIP, 100Ω, 1/16W, 1% 0402 VISHAY, CRCW0402100RFKED
15 1 R18 RES., CHIP, 0Ω, 1/10W, 0402 VISHAY, CRCW04020000Z0ED
16 4 SW0, SW1, SW2, SW3 SWITCH, SLIDE SPDT 200MA 30V, SW-EG1218 E-SWITCH, EG1218
17 1 SHUNT ON JP1 (1&2) SHUNT, 2mm WURTH ELEKTRONIK, 60800213421
18 4 MH1-MH4 STANDOFF, NYLON, 0.5, 1/2" WURTH ELEKTRONIK, 702935000
19 1 DUST CAP FOR J26 WYHP DUST CAP FOR SMA FEMALE RF CONN AMAZON

8
DEMO MANUAL DC2611A
Rev. 0
PARTS LIST
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
DC2611A3-A Required Circuit Components
1 1 DC2611A3-GENERAL BOM
2 3 C58, C59, C61 CAP., X7R, 0.1µF, 10V, 10%, 0402 MURATA, GRM155R71A104KA01D
3 0 C60 CAP., 0402 OPT
4 1 FB1 RES., CHIP, 0Ω, 1/20W, 1% 0201 VISHAY, CRCW02010000Z0ED
5 1 R8 RES., CHIP, 75Ω, 1/16W, 1% 0402 VISHAY, CRCW040275R0FKED
6 0 R9, R11, R19, R20 RES., 0402 OPT
7 1 R10 RES., CHIP, 30Ω, 1/16W, 1% 0402 VISHAY, CRCW040230R0FKED
8 1 U1 I.C., ULTRALOW JITTER 11 OUTPUT FANOUT BUFFER,
QFN52UKG-7X8
LINEAR TECH., LTC6955IUKG
DC2611A3-B Required Circuit Components
1 1 DC2611A3-GENERAL BOM
2 0 C58, C61 CAP., 0402 OPT
3 2 C59, C60 CAP., C0G, 1pF, 50V, 10%, 0402 MURATA, GJM1555C1H1R0CB01
4 1 FB1 IND., 47ΩS AT 100MHz, FERRITE BEAD, 0201 TDK, MMZ0603D470ET000
5 0 R8, R9, R10, R19 RES., 0402 OPT
6 1 R11 IND., FIXED, HIFREQ, 47nH 5% 0.15A, 0402 COIL CRAFT, 0402CS-1N0XJL
7 1 R20 RES., CHIP, 49.9, 1/16W, 1% 0402 VISHAY, CRCW040249R9FKED
8 1 U1 I.C., ULTRALOW JITTER 11 OUTPUT FANOUT BUFFER,
QFN52UKG-7X8
LINEAR TECH., LTC6955IUKG-1

9
DEMO MANUAL DC2611A
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
SCHEMATIC DIAGRAM
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
3.3V SUPPLIES
1. ALL RESISTORS AND CAPACITORS ARE 0402. NOTES: UNLESS OTHERWISE SPECIFIED
PLACE ON TOP SIDE
PLACE ON BOTTOM SIDE
[2]
[2]. J26 = INSTALLED BUT UNUSED. [3]. COMPONENTS WILL BE STUFFED WITH DEFAULT VALUES.
FOR INPUT SIGNALS < 5GHz
DIFFERENTIAL S-E IN- (DEFAULT FOR -A) S-E IN+
R8 R9 R10C59 C60
OPT75 300.1uF
0.1uF0.1uF
7530 OPTOPT
OPT
0.1uF
OPTOPT 160
OTHER VALUES ARE FOR LAB USED ONLY.
[3]
ALL INPUT AND OUTPUT CONNECTIONS ARE SAME LENGTH, 50 OHM CONTROLLED IMPEDANCE.
[4]. ASSEMBLY TABLE:
ASSY U1 SUFFIX
A LTC6955
LTC6955-1 1
DC2611A -
BDC2611A -
LH LH LH LH
C58 C61
0.1uF 0.1uF
0.1uF 0.1uF
R11 R19 R20
OPT OPT OPT
OPT OPT OPT
OPT OPT OPT
FOR INPUT SIGNALS > 5GHz
DIFFERENTIAL S-E IN- (DEFAULT FOR -B) S-E IN+
R8 R9 R10C59 C60
OPT
1pF
OPT
OPTOPT
C58 C61 R11 R19 R20
1nH OPT
OPT
49.9
OPT 49.9 OPT
OPT OPT OPT
1pF 1pF
1pF 1pF 1pF
OPT OPT OPT
OPT OPT
OPT
OPT OPT
1nH 1nH
FB1 FB1
MMZ0603
OPT OPT
0 OHM
MMZ0603 MMZ0603
0 OHM 0 OHM
OUT0+
SEL3
OUT0- OUT1+ OUT1- OUT2- OUT3+
OUT4+ OUT4- OUT5+ OUT5- OUT6+ OUT6-
OUT7+ OUT7- OUT8+ OUT8- OUT9- OUT10- OUT10+
TEMP
IN- IN+
OUT9+
CAL_INCAL_OUT
OUT3-
FILT
SEL0 SEL1 SEL2
OUT2+
3.3V
3.3V 3.3V
3.3V 3.3V 3.3V 3.3V
3.3V 3.3V 3.3V
3.3V
3.3V 3.3V 3.3V
3.3V
VIN33
VIN33
3.3V
3.3V
REVISION HISTORY DESCRIPTION DATEAPPROVEDECO REV
CHRIS P.PRODUCTION
__ 3 07-07-17
REVISION HISTORY DESCRIPTION DATEAPPROVEDECO REV
CHRIS P.PRODUCTION
__ 3 07-07-17
REVISION HISTORY DESCRIPTION DATEAPPROVEDECO REV
CHRIS P.PRODUCTION
__ 3 07-07-17
SIZE DATE:
IC NO. REV.
SHEET OF
TITLE:
APPROVALS
PCB DES.
APP ENG.
TECHNOLOGY Fax: [phone]
Milpitas, CA 95035 Phone: [phone] McCarthy Blvd. LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SCHEMATIC
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCALE = NONE
www.linear.com
3
DEMO CIRCUIT 2611A
Friday, July 07, 2017
11
ULTRALOW JITTER 11 OUTPUT FANOUT BUFFER
N/A
LTC6955IUKG, LTC6955IUKG-1
KIM T.
CHRIS P.
SIZE DATE:
IC NO. REV.
SHEET OF
TITLE:
APPROVALS
PCB DES.
APP ENG.
TECHNOLOGY Fax: [phone]
Milpitas, CA 95035 Phone: [phone] McCarthy Blvd. LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SCHEMATIC
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCALE = NONE
www.linear.com
3
DEMO CIRCUIT 2611A
Friday, July 07, 2017
11
ULTRALOW JITTER 11 OUTPUT FANOUT BUFFER
N/A
LTC6955IUKG, LTC6955IUKG-1
KIM T.
CHRIS P.
SIZE DATE:
IC NO. REV.
SHEET OF
TITLE:
APPROVALS
PCB DES.
APP ENG.
TECHNOLOGY Fax: [phone]
Milpitas, CA 95035 Phone: [phone] McCarthy Blvd. LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SCHEMATIC
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCALE = NONE
www.linear.com
3
DEMO CIRCUIT 2611A
Friday, July 07, 2017
11
ULTRALOW JITTER 11 OUTPUT FANOUT BUFFER
N/A
LTC6955IUKG, LTC6955IUKG-1
KIM T.
CHRIS P.
SW2
EG1218
SEL2
13
2
J10
SMA
OUT0-
C25
0.01uF
0201
E10
VIN33
C56 0.1uF
J13
SMA
OUT2+
OPT
C6 0.1uF
J26
SMA
IN+
J4
SMA
OUT9+
OPT
C61
U1 [4]
VOUT+ 32
OUT1+ 31
OUT1- 30
VOUT+ 29
OUT2+ 28
OUT2- 27
VOUT+
26
OUT3+
25
OUT3-
24
VOUT+
23
VOUT+
14
SEL3
1
VD+
2
OUT10-
3
OUT10+
4
VOUT+
5
OUT9-
6
OUT9+
7
VOUT+
8
OUT8-
9
OUT8+
10
VOUT+
11
OUT7-
12
VIN+ 39
IN- 38
OUT7+
13
VOUT+
20
VOUT+
17
OUT5+
19
OUT6+
16
OUT4-
21
OUT4+
22
OUT5-
18
IN+ 37
NC 36
OUT0+ 34
VOUT+ 35
OUT6-
15
OUT0- 33
FILT 40
GND 41
NC 42
NC 43
NC 44
NC 45
NC 46
NC 47
NC 48
TEMP 49
SEL0 50
SEL1 51
SEL2 52
EP 53
C19 OPT C20 OPT
E7
GND
J14
SMA
OUT2-
OPT
JP1
HD1X3-079
L
H
FILT
1 3 2
C3 OPT
C32
0.01uF
0201
C15 OPT
J3
SMA
OUT9-
OPT
E9
C57 0.1uF
C30
0.01uF
0201
C18 0.1uF
C28
0.01uF
0201
J16
SMA
OUT3-
OPT
C14 OPT
R9
J17
SMA
OUT4+
C5 0.1uF
J23
SMA
CAL_OUT
R7 100
E3
GND
SW1
EG1218
SEL1
13
2
R5 100
J20
SMA
OUT5-
OPT
C50 0.1uF
C10 0.1uF
J18
SMA
OUT4-
C31
0.01uF
0201
R1 10k
E2
GND
C48 1uF
J8
SMA
OUT7+
OPT
C35
0.01uF
0201
C59
C17 0.1uF
J6
SMA
OUT8+
C8 OPT
J15
SMA
OUT3+
OPT
C42 1uF
R4 100
C1 0.1uF
C21 0.1uF
J11
SMA
OUT1+
E8
J24
SMA
CAL_IN
R18
0
C13 OPT
R2 10k
R20
J5
SMA
OUT8-
C44 1uF
C22 0.1uF
J27
3.3V
KEY-575
E6
GND
J1
SMA
OUT10-
C43 1uF
C29
0.01uF
0201
C38 1uF
R8
C2 0.1uF
J9
SMA
OUT0+
C46 1uF
J21
SMA
OUT6+
J19
SMA
OUT5+
OPT
C47 1uF
+
C62 330uF 10V 7343
E1
TEMP
C45 1uF
C7 OPT
C34
0.01uF
0201
J25
SMA
IN-
SW3
EG1218
SEL3
13
2
C11 0.1uF
J12
SMA
OUT1-
C27
0.01uF
0201
J22
SMA
OUT6-
R6 100
R3 100k C9
0.1uF
C39 1uF C40
1uF C41
1uF
FB1
[3]
R10
C12 0.1uF
C26
0.01uF
0201
R19
E4
GND
J7
SMA
OUT7-
OPT
C58
E5
GND
C36 0.01uF 0201
SW0
EG1218
SEL0
13
2
C49 10uF 1206 C33
0.01uF
0201
J28
GND
KEY-575
C16 OPT
J2
SMA
OUT10+
R11
R12 100
C60
C4 OPT

10
DEMO MANUAL DC2611A
Rev. 0
 ANALOG DEVICES, INC. 2019
www.analog.com
01/19
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions
By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and
conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation
Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”)
and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to
Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and
agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted
is expressly made subject to the following additional limitations:Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board;and (ii) permit any Third
Party to access the Evaluation Board. As used herein, the term “Third Party”includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is
NOT sold to Customer;all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all
be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of
use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile
or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited
to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS
Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF
LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS”AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY
DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS
LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING
BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE
HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States
federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts
(excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits
to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.