Analog Devices ADuCM355 Quick start guide

4) 5V USB FROM 8-PIN JTAG CONNECTOR
MICRO USB CONNECTOR
J-TAG CONNECTOR
2) CONNECT 5V TO 2-PIN CONNECTOR
3) CONNECT 3.3V DIRECT TO DVDD OR AVDD
POWER OPTIONS:
USB TO UART
JLINK DEBUG
CONNECTOR
OPTIONAL PULL_UPS FOR SW LINES
OPTIONAL EXTERNAL 3V
SUPPLY CONNECTOR 1) VIA USB
OPTIONAL 5V CONNECTOR
1 2
<DESIGN_VIEW>
: n/a
Product(s): ADuCM355
HW TYPE : Customer Evaluation
1:1
B
02_045865
<PTD_ENGINEER>
ADP7158ACPZ-3.3-R7
560
SML-310MTT86
10UF
0.1UF
60OHM AT 100MEGHZ
0.1UF
1UF
BLM41A800SPB-1806
0.1UF
M20-9990245
2.2
60OHM AT 100MEGHZ2.2
FT232RQ
M20-9990245
0.1UF 0.1UF
0
25.195.0253.0
10UF
25.195.0253.0
0.1UF0.1UF
10UF
2520-6002-UB
0.1UF
10UF
0.1UF
0.1UF
0
1K
100K
DNI
100K
100K
TSW-101-07-G-D
0.1UF
BLM41A800SPB-1806
0.1UF
1UF
0
1UF
TSW-104-25-F-D-RA
10UF
47346-0001
P4
AVDD
DVDD
JP36
DS1
R17
JP39
P14
R4
R13
R3
JP38
R7
JP5 P3
C36
C35
JP41
JP40
JP37
JP42 JP43
JP44
JP34
JP32
JP46
JP45
JP35
R14
C57
P27
C38
C48 C49
C52 C53
C54
C55
E4
E3
R9
R8
C47
C41
JP6
C43 C44
U3
E1
E2
C39
C40
C37
U2
C42
C46
C45
5VUSB
USBD-
AVDD_PREFILTER
3V3VOUT
USBD+
USBD-
P0.10_SOUT
P0.11_SIN
3V3VOUT
3V3VOUT
DVDD_PREFILTER
AVDD_PREFILTER
DVDD
AVDD
P1.5_CS
DVDD
SWDIO
SWCLK
P0.10_SOUT
SWCLK
SWDIO
P0.11_SIN
/RESET
DVDD
5VUSB DVDD
P0.11_SINSWCLK
P0.10_SOUTSWDIO
5VUSB
5VUSB DVDD_PREFILTER
/RESET
USBD+
G6
G5
G4
G3
G2
G1
5
4
3
2
1
2
1
2
1
21
A C
21
2
1
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
21
21
21
21 21
21
21
21
21
21
21 87 65 43 21
21
21
21
8
3
2
1
10
9
6
7
PAD
5
4
21
21
1 19
14
15
30
26
2323
18 28
27
29 25 23 13 12
5
20 17
4
PAD
31
6
7
8
9
11
10
21
22
24
16
DGND
VCCVCCIO
CBUS4
CBUS3
CBUS2
CBUS1
CBUS0
RTS#
DTR#
TXD
OSCO
3V3OUT
NCEP AGNDGND
USBDP
USBDM
CTS#
DCD#
DSR#
RI#
RXD
OSCI
TEST
RESET#
AGND
DGND
DGND
DGND
AGND
DGND
AGND
DGND
DGND
EP
VIN
VIN
VREG
REF
REF_SENSE
EN
BYP
VOUT_SENSE
VOUT
VOUT
DGND
DGND
DGND
DGND
DGND
GND
PINS
AGND
DGND
DGND
DGND
DGND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR DRAWING NO.
2
SCALE
D
D
D
SIZE
D
REV
SHEET
1
1
A
2
3
4
3
5
8
D
7
67
8
A
B
CC
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL G
E
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
E
ANV
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE

OPTIONAL UART PULL-UPS
OPTIONAL I2C PULL-UPS
OPTIONAL DIGITAL TEMP SENSOR
INPUT BUFFERS
ANALOG SIGNALS
EC SENSOR SHORTING FET
RESET BUTTON
WAKE-UP BUTTON
EC SENSOR CHANNEL 0
DIGITAL TEST PINS
0R RESEISTORS CLOSE TO DUT
EC SENSOR SHORTING FET
EXTERNAL CRYSTAL
EC SENSOR CHANNEL 1
BOOT MODE BUTTON
4-PIN DUAL SENSOR JMPRS
EXTERNAL RTIA
DECOUPLING CAPS
GPIO CONTROLLED LED
RCAL RESISTOR
OPTIONAL CONNECTOR TO A SENSOR
ADUCM355
2 2
<DESIGN_VIEW>
: n/a
Product(s): ADuCM355
HW TYPE : Customer Evaluation
1:1
B
02_045865
<PTD_ENGINEER>
31022-00-21-00-00-08-0
4.7UF
200
0.47UF
0.1UF
0.47UF
TSW-110-08-G-S
DNI
0
0
0
150K
DNI
DNI
560
LNJ926W8CRA
100K
100K
1K
1K
32MEGHZ
ADT7420UCPZ-RL7
AD8671ARZ
TSW-120-07-S-S
B3S-1000
DNI
0.47UF
DNI
RED
RED
DNI
RED
RED
DNI
AD8671ARZ
RED
DNI DNI
RED
RED
DNI
RED RED RED
DNI
DNI
RED
RED
DNIDNI
RED
DNI
RED
DNI
DNI
RED
DNI
RED
DNI
31022-00-21-00-00-08-0
150K
0.1UF
CO-A4
DNI
B3S-1000
0.15UF 10K
220PF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
7PF 7PF
TSW-101-07-G-D
0.47UF
4.7UF
B3S-1000
100K
DNI
0.1UF
.125
0.1UF
4.7UF
0.1UF
0.47UF
DNI
0.1UF
CO-A4
0.1UF
DNI
0.1UF
DNI
0.1UF
MMBFJ177
0
0.1UF
DNI
DNI
0
0
0
0
0
0
0
0
0
0
0
0
IPS1-109-01-L-D
100K
DNI
DNI
DNI
DNI
0
0.1UF
0.1UF
0
MMBFJ177
0.47UF
0.1UF
0.1UF
0.1UF
0.1UF
0
ADUCM355
0
C25
JP4
C_LPF1
C17
C21
RCAL
JP19
JP20
JP12
JP7
JP8
JP9
R1
A1
DS2 R10 JP33
TP11
TP13 TP14
TP12 A2
TP15 TP17
TP16
TP18
TP10
TP9TP7TP6
TP8
TP5
TP1
TP2
Y1
CTIA RTIA
U4
R16
R15
JP28
JP27
JP26
JP25
R6
R5
JP24
JP23
P2
JP22
JP21 JP10
P5
TP3 JP14
JP13
JP18
JP17
JP16
JP11
JP15
TP4
P1
C28 S1
C22
JP31
JP30
JP29
C23
P26
R11
C56
R12
C4
C8
C7
C5
C6
C3
C13
C_LPF0
C20
C19
C18
C34
C14
S2
S3
C32 C33
C30
C29
C26
C31C27
Q1
Q2
JP2
JP3
JP1
C9
C10
C12
C11
R2
C1
C2
C24
CH1
CH0
U1
SE0
CE0
RE0
VBIAS0
RE1
SE1
VBIAS1
VZERO1
DVDD
VZERO0
AIN0
AIN3
AIN5
AIN6
CE1
CAP_POT0
CAP_POT1
XTALO
CE1
RE1
AIN6
AIN5
AIN3
AIN2
AIN1
AIN0
P2.4
AIN1
P0.10_SOUT
SCL_PULLEDUP
AIN2
AIN3
P0.5_SDA
P0.3_CS0
RE1RE0
AFEDIE_GPIO1
P0.11_SIN
P0.10_SOUT
P0.5_SDA
SE1
SE1
VBIAS1
VZERO1
DE0
AIN0
DE0
AIN3
VZERO0
VBIAS0
AVDD
DVDD
DVDD
P0.1_MOSI0
RE1
DVDD
DVDD
DE1
SE1
SDA_PULLEDUP
AFEDIE_GPIO0
P0.3_CS0
/RESET
/RESET
P0.4_SCL
P2.4
XTALO
XTALI
AVDD
DVDD
P1.5_CS
P1.1
AIN2
DE1
SE0
DE0
P1.4_MISO1
P1.3_MOSI1
P1.2_SCLK1
P0.2_MISO0
P0.0_SCLK0
P0.1_MOSI0
P1.3_MOSI1
P0.10_SOUT
CAP_POT0
CE0
RE0
DE0
SE0
DE0
SE0
CE0
AIN1
AVDD
AIN6
AIN0
DE0 AIN0
SE1
DE1
RE0
AGND
AVDD
P1.0
DVDD
DVDD
P1.1
RE0
AVDD
CAP_POT1
AVDD
CE1
DVDD
P1.4_MISO1
P0.4_SCL DVDDSCL_PULLEDUP
DVDD
DVDD
P1.5_CS
P1.4_MISO1
P1.3_MOSI1
P1.2_SCLK1
P1.1
P0.2_MISO0
P0.0_SCLK0
P2.4
AFEDIE_GPIO1
DE1 AIN1
P0.5_SDA SDA_PULLEDUP
P0.11_SIN
P1.0
P0.11_SIN
P0.4_SCL
AIN5
RE1
AFEDIE_GPIO0
P1.0
SWDIO
SWCLK
XTALI
E11
1 2
A C
1
1 1
1
4
7
6
3
851
2
1 1
1
1
1
111
1
1
1
1
4
7
6
3
851
2
31
42
12
2
1
PAD
16 15 14 13
8 7 6 5
9
11
10
4
3
21
21
2
1
2
1
21
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
1
10
9
8
7
6
5
4
3
2
1
3
42
1
21 21
21
2
1
3
42
1
3
42
1
2
3
1
2
3
1
2
3
1
4
2
3
1
4
J1
H1
B10
B2
E2
A5
J11 H11 J9 J8 G11
C10
C2
H4
H3
A9
A3
J10
A11
A1
A6
A7
D10
D11
D2
D1
D6
F6
D7
E7
D5
F5
J2
J3
H5
J5
H6
H7
H8
H9
E10
E5
H10
G10
G1 J7 F1 J6
F2 F7
A10
A2
B11
B1
C11
C1
J4
E1 G2 F11
A8
B3
B4
A4
B7
B6
B8
B9
B5
H2
F10
DGND
DGND
DGND
DGND
DGND
DGND
AGND
AGND
DGND
G
D
S
G
D
S
AGND
AGND
AGND
AE
RE
WECE
AGND
AGND
AGND
AGND
NC
OUT
V+
V-
NC
OUT
V+
V-
AGND
AE
RE
WECE
GND
PAD
VDD
GND
CT
INT
NC
A1
A0
SDA
SCL
AGND
AGND
DGND
AGND
DGND
DGND
AGND
DGND
DGND
AGND
DGND
DGND
DGND
RESET_N
VDCDC_CAPOUT
VDCDC_CAP1P
VDCDC_CAP1N
DVDD_REG
DVDD
P0.4/I2C_SCL
BM/P2.4
P0.10/UART_SOUT
P0.11/UART_SIN
XTALO
VDCDC_CAP2N
GPIO1/PWM1/EXTCLK
P0.0/SPI0_CLK
P0.1/SPI0_MOSI
P0.2/SPI0_MISO
P0.3/SPIO_/CS0
P0.5/I2C_SDA
SWDIO
SWCLK
AGND_DD
XTALI
VCDC_CAP2P
GPIO0/PWM0/POR/HIBERNATE
AVDD_DD
DVDD_REG_AD
AVDD
AGND DGND
P1.4/SPI1_MISO
P1.0/SYS_WAKE
DGND_AD
DVDD_AD
ADCVBIAS_CAP
NC
P1.2/SPI1_CLK
NC
VREF_2.5V
AVDD_REG
RC1_0
RC1_1
P1.3/SPI1_MOSI
P1.5/SPI1_/CS0
P1.1
RC0_1
RC0_0
CAP_POT1
VBIAS1
VBIAS0
CAP_POT0
CE1
VZERO1
AIN0
AIN1
AIN3/BUF_VREF1V8
AIN2
AGND_REF
AIN5
AIN6
VZERO0
CE0
RE1
DE1
SE1
AIN7_LPF1
RCAL0
RCAL1
VREF_1.8V
AIN4_LPF0
SE0
DE0
RE0
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR DRAWING NO.
2
SCALE
D
D
D
SIZE
D
REV
SHEET
1
1
A
2
3
4
3
5
8
D
7
67
8
A
B
CC
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL G
E
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
E
ANV
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE