Analog Devices ADT7460 User manual

dB COOL™ Remote Thermal
Controller and Fan Controller
ADT7460
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Controls and monitors up to 4 fan speeds
1 on-chip and 2 remote temperature sensors
Dynamic TMIN control mode optimizes system acoustics
intelligently
Automatic fan speed control mode controls system cooling
based on measured temperature
Enhanced acoustic mode dramatically reduces user
perception of changing fan speeds
Thermal protection feature via THERM output
Monitors performance impact of Intel®Pentium®4
Processor thermal control circuit via THERM input
2-wire and 3-wire fan speed measurement
Limit comparison of all monitored values
Meets SMBus 2.0 electrical specifications (fully
SMBus 1.1-compliant)
APPLICATIONS
Low acoustic noise PCs
Networking and telecommunications equipment
GENERAL DESCRIPTION
The ADT74601dBCOOL controller is a thermal monitor and
multiple PWM fan controller for noise-sensitive applications
requiring active system cooling. It can monitor the temperature
of up to two remote sensor diodes plus its own internal temp-
erature. It can measure and control the speed of up to four fans
so that they operate at the lowest possible speed for minimum
acoustic noise. The automatic fan speed control loop optimizes
fan speed for a given temperature. A unique dynamic TMIN
control mode enables the system thermals/acoustics to be
intelligently managed. The effectiveness of the system’s thermal
solution can be monitored using the THERM input. The
ADT7460 also provides critical thermal protection to the
system by using the bidirectional THERM pin as an output
to prevent system or component overheating.
FUNCTIONAL BLOCK DIAGRAM
03228-001
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
GND
SERIAL BUS
INTERFACE
SCL SDA
VALUE AND
LIMIT
REGISTERS
LIMIT
COMPARATORS
INTERRUPT
STATUS
REGISTERS
BAND GAP
TEMP SENSOR
V
CC
TO ADT7460
ADDRESS
POINTER
REGISTER
PWM
CONFIGURATION
REGISTERS
INTERRUPT
MASKING
V
CC
D1+
D1–
D2+
D2–
+2.5V
IN
THERMAL
PROTECTION
PERFORMANCE
MONITORING
PWM REGISTERS
AND
CONTROLLERS
PWM1
PWM2
PWM3
ACOUSTIC
ENHANCEMENT
CONTROL
BAND GAP
REFERENCE
10-BIT
ADC
ADT7460
AUTOMATIC
FAN SPEED
CONTROL
DYNAMIC
T
MIN
CONTROL
FAN SPEED
COUNTER
TACH1
TACH2
TACH3
TACH4
THERM
SMBALERT
SMBUS
ADDRESS
SELECTION
ADDR
SELECT ADDR_EN
Figure 1.
1Protected by U.S. Patent Nos. 6,188,189; 6,169,442; 6,097,239; 5,982,221; and 5,867,012. Other patents pending.

ADT7460
Rev. C | Page 2 of 52
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Product Description......................................................................... 9
Measurement Inputs .................................................................... 9
Sequential Measurement ............................................................. 9
Recommended Implementation................................................. 9
ADT7460 Address Selection ..................................................... 10
Internal Registers of the ADT7460 .......................................... 10
Theory of Operation ...................................................................... 11
Serial Bus Interface..................................................................... 11
Voltage Measurement Input...................................................... 15
Additional ADC Functions for Voltage Measurements........ 17
Temperature Measurement System.......................................... 17
Additional ADC Functions for Temperature Measurement 19
Limits, Status Registers, and Interrupts................................... 20
Status Registers ........................................................................... 21
Handling SMBALERT Interrupts............................................. 22
THERM Timer ........................................................................... 24
Fan Drive Using PWM Control ............................................... 27
Operating from 3.3 V Standby ................................................. 33
XNOR Tree Test Mode .............................................................. 33
Power-On Default ...................................................................... 33
ADT7460 Register Summary........................................................ 34
Outline Dimensions ....................................................................... 51
Ordering Guide .......................................................................... 51
REVISION HISTORY
3/05—Rev. B to Rev. C
Updated Format.................................................................. Universal
Changes to Absolute Maximum Ratings Table..............................5
Changes to ADT7460 Register Map Summary Section .............34
Updated Ordering Guide................................................................51
9/03—Rev. A to Rev. B
Changed XOR Tree Test Mode to XNOR ............................ Universal
Changes to SPECIFICATIONS............................................................. 2
Changes to TPC 7....................................................................................7
6/03—Rev. 0 to Rev. A
Updated ORDERING ............................................................................4
Updated the SERIAL BUS INTERFACE section................................9
Added the To Assign THERM Functionality to a Pin 9 section ....21
Added the THERM as an Input section.............................................21
Renamed the Therm Input section to THERM Timer ....................21
Renumbered the figures after Figure 25.............................................22
Updated Step 1 in the Configuring the Desired THERM Behavior
section........................................................................................................2
Updated the Fan Speed Control section ............................................28
Added the POWER-ON DEFAULT section .....................................29
Updated Table IV ..................................................................................30
Updated Table XVIII ............................................................................38
Updated Table XX .................................................................................40
Updated Table XXXV ...........................................................................46
Updated OUTLINE DIMENSIONS ...................................................49

ADT7460
Rev. C | Page 3 of 52
SPECIFICATIONS
TA= TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.
Table 1.
Parameter1, ,2 3 Min Typ4Max Unit Test Conditions/Comments
POWER SUPPLY
Supply Voltage 3.0 5.0 5.5 V
Supply Current, ICC 3 mA Interface inactive, ADC active
20 µA Standby mode
TEMPERATURE-TO-DIGITAL CONVERTER
Local Sensor Accuracy ±1.5 °C 0°C ≤ TA≤ 70°C
±3 °C −40°C ≤ TA≤ +120°C
Resolution 0.25 °C
Remote Diode Sensor Accuracy ±1.5 °C 0°C ≤ TA≤ 70°C; 0°C ≤ TD≤ 120°C
±2.5 °C 0°C ≤ TA≤ 105°C; 0°C ≤ TD≤ 120°C
±3 °C 0°C ≤ TA≤ 120°C; 0°C ≤ TD≤ 120°C
Resolution 0.25 °C
Remote Sensor Source Current 180 µA High level
11 µA Low level
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error, TUE ±1.5 %
Differential Nonlinearity, DNL ±1 LSB 8 bits
Power Supply Sensitivity ±0.1 %/V
Conversion Time (Voltage Input) 11.38 13 ms Averaging enabled
Conversion Time (Local Temperature) 12.09 13.50 ms Averaging enabled
Conversion Time (Remote Temperature) 25.59 28 ms Averaging enabled
Total Monitoring Cycle Time 120.17 134.50 ms Averaging enabled (incl. delay5)
13.51 15 ms Averaging disabled
Input Resistance 80 140 200 kΩ
FAN RPM-TO-DIGITAL CONVERTER
Accuracy ±7 % 0°C ≤ TA≤ 70°C
±11 % 0°C ≤ TA≤ 105°C
±13 % −40°C ≤ TA≤ +120°C
Full-Scale Count 65,535
Nominal Input RPM 109 RPM Fan count = 0xBFFF
329 RPM Fan count = 0x3FFF
5000 RPM Fan count = 0x0438
10000 RPM Fan count = 0x021C
Internal Clock Frequency 82.8 90.0 97.2 kHz
OPEN-DRAIN DIGITAL OUTPUTS, PWM1–PWM3, XTO
Current Sink, IOL 8.0 mA
Output Low Voltage, VOL 0.4 V IOUT = −8.0 mA, VCC = 3.3 V
High Level Output Current, IOH 0.1 1 µA VOUT = VCC
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL 0.4 V IOUT = −4.0 mA, VCC = 3.3 V
High Level Output Current, IOH 0.1 1 µA VOUT = VCC
SMBUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.4 V
Hysteresis 500 mV

ADT7460
Rev. C | Page 4 of 52
Parameter1, 2, 3Min Typ4Max Unit Test Conditions/Comments
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH 2.0 V
5.5 V Maximum input voltage
Input Low Voltage, VIL +0.8 V
−0.3 V Minimum input voltage
Hysteresis 0.5 V p-p
DIGITAL INPUT LOGIC LEVELS (THERM)
Input High Voltage, VIH 1.7 V
Input Low Voltage, VIL 0.8 V
DIGITAL INPUT CURRENT
Input High Current, IIH −1 µA VIN = VCC
Input Low Current, IIL +1 µA VIN = 0
Input Capacitance, CIN 5 pF
SERIAL BUS TIMING6
Clock Frequency, fSCLK 400 kHz See Figure 2
Glitch Immunity, tSW 50 ns
Bus Free Time, tBUF 1.3 µs See Figure 2
Start Setup Time, tSU;STA 0.6 µs See Figure 2
Start Hold Time, tHD;STA 0.6 µs See Figure 2
SCL Low Time, tLOW 1.3 µs See Figure 2
SCL High Time, tHIGH 0.6 µs See Figure 2
SCL, SDA Rise Time, tR300 ns See Figure 2
SCL, SDA Fall Time, tF300 µs See Figure 2
Data Setup Time, tSU;DAT 100 ns See Figure 2
Detect Clock Low Timeout, tTIMEOUT 15 35 ms Can be optionally disabled
3Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and at VIH = 2.0 V for a rising edge.
4Typicals are at TA= 25°C and represent the most likely parametric norm.
5The delay is the time between the round robin finishing one set of measurements and starting the next.
6Guaranteed by design, not production tested.
1All voltages are measured with respect to GND, unless otherwise specified.
2Logic inputs accept input high voltages up to VMAX even when the device is operating down to VMIN.
SCL
SD
A
PS SP
t
BUF
t
HD; STA
t
HD; DAT
t
SU; DAT
t
F
t
R
t
LOW
t
SU; STA
t
HIGH
t
HD; STA
t
SU; STO
03228-002
Figure 2. Serial Bus Timing Diagram

ADT7460
Rev. C | Page 5 of 52
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Positive Supply Voltage (VCC) 6.5 V
Voltage on Any Other Input or Output Pin −0.3 V to +6.5 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJmax) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering
IR Reflow Peak Temperature 220°C
IR Reflow Peak Temperature for Pb Free 260°C
Lead Temperature (Soldering 10 s) 300°C
ESD Rating 1500 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
16-Lead QSOP Package:
θJA = 150°C/W
θJC = 39°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

ADT7460
Rev. C | Page 6 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
03228-003
ADT7460
TOP VIEW
(Not to Scale)
1
215 PWM1/XTO
3
4
5
16
14
13
12
SCL
GND
VCC
TACH3
2/SMBALERT
SDA
+2.5VIN/SMBALERT
611
10
TACH1
7
TACH2
89
PWM3/ADDRESS ENABLE
PWM
D1+
D1–
D2+
D2–
TACH4/ADDRESS SELECT/THERM
Figure 3. Pin Configuration
Table 3. P tion Descript
Pin No. Mnemonic
in Func ions
Description
1 SCL Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
2 GND 460.Ground Pin for the ADT7
3 VCC Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is required. VCC is also
monitored through this pin. The ADT7460 can also be powered from a 5 V supply. Setting Bit 7 of
Configuration Register 1 (Reg. 0x40) rescales the VCC input attenuators to correctly measure a 5 V supply.
4 TACH3 re speed of Fan 3. Can be reconfigured as anDigital Input (Open Drain). Fan tachometer input to measu
analog input (AIN3) to measure the speed of 2-wire fans.
5 PWM2 utput (Open Drain). Requires 10 kΩ typical pull-up. Pulse-width modulated output to control
SMBALERT
Digital O
Fan 2 speed.
Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal
out-of-limit conditions.
6 TACH1 re speed of Fan 1. Can be reconfigured as anDigital Input (Open Drain). Fan tachometer input to measu
analog input (AIN1) to measure the speed of 2-wire fans.
7 TACH2 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. Can be reconfigured as an
analog input (AIN2) to measure the speed of 2-wire fans.
8 PWM3 ypicalDigital I/O (Open Drain). Pulse-width modulated output to control Fan 3/4 speed. Requires 10 kΩ t
pull-up.
ADDRESS ENABLE If pulled low on power-up, this places the ADT7460 into address select mode, and the state of Pin 9
determines the ADT7460’s slave address.
9 TACH4 put to measure speed of Fan 4. Can be reconfigured as anDigital Input (Open Drain). Fan tachometer in
analog input (AIN4) to measure the speed of 2-wire fans.
ADDRESS SELECT If in address select mode, this pin determines the SMBus device address.
THERM Alternatively, the pin may be reconfigured as a bidirectional THERM pin. Can be used to time and monit
assertions on the
or
THERM input. For example, can be connected to the PROCHOT output of Intel’s Pentium 4
processor or to the output of a trip point temperature sensor. Can be used as an output to signal
overtemperature conditions.
10 D2− Cathode Connection to Second Thermal Diode.
11 D2+ Anode Connection to Second Thermal Diode.
12 D1− Cathode Connection to First Thermal Diode.
13 D1+ Anode Connection to First Thermal Diode.
14 +2.5VIN Analog Input. Monitors 2.5 V supply, typically a chipset voltage.
SMBALERT Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal
out-of-limit conditions.
15 PWM1/XTO Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ typical
pull-up.
16 SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pull-up.

ADT7460
Rev. C | Page 7 of 52
TYPICAL PERFORMANCE CHARACTERISTICS
LEAKAGE RESISTANCE (M Ω )
REMOTE TEMPERATURE ERROR (°C)
15
10
–20 1 3.3 100.0
10.0 30.0
0
–5
–10
–15
5DXPTOGND
DXP TO V
CC
(3.3V)
03228-004
Figure 4. Remote Temperature Error vs. Leakage Resistance
DXP–DXN CAPACITANCE (nF)
REMOTE TEMPERATURE ERROR (°C)
3
1
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
2.2 3.3 4.7 10.0 22.0 47.0
–30
–33
–36
REMOTE TEMPERATURE ERROR (°C)

03228-005
Figure 5. Remote Temperature Error vs. Capacitance between D+ and D−
TEMPERATURE (°C)
REMOTE TEMPERATURE ERROR (°C)
3
–40
2
1
0
–1
–2
–3 10 60 110
–3 SIGMA
+3 SIGMA
LOW LIMIT
HIGH LIMIT
03228-006
TEMPERATURE (°C)
LOCAL TEMPERATURE ERROR (°C)
–3
–40 10 110
60
1
0
–2
–1
3
2
LOW LIMIT
HIGH LIMIT
–3 SIGMA
+3 SIGMA
03228-007
Figure 7. Local Temperature Error vs. Actual Temperature
FREQUENCY (Hz)
REMOTE TEMPERATURE ERROR (°C)
14
12
–2
100k 550k 50M
5M
6
4
0
2
10
8
100mV
250mV
03228-008
Figure 8. Remote Temperature Error vs. Power Supply Noise Frequency
RROR (°C)
12.5
10.0
–5.0
100k 550k 50M
FREQUENCY (Hz)
LOCAL TEMPERATURE
5M
5.0
2.5
–2.5
0
7.5
100mV
E
250mV
03228-009
Figure 9. Local Temperature Error vs. Power Supply Noise Frequency
Figure 6. Remote Temperature Error vs. Actual Temperature

ADT7460
Rev. C | Page 8 of 52
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
2.5
2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4
5.5
SUPPLYVOLTAGE (V)
SUPPLY CURRENT (mA)
03228-010
Figure 10. Supply Current vs. Supply Voltage
FREQUENCY (Hz)
REMOTE TEMPERATURE ERROR (°C)
16
60k
14
12
10
8
6
4
2
0
–2 110k 1M 10M 50M
10mV
20mV
03228-011
Figure 11. Remote Temperature Error vs. Differential Mode Noise Frequency
10k FREQUENCY (Hz)
REMOTE TEMPERATURE ERROR (°C)
40
35
30
25
20
15
10
5
0
–5
–10 100k 1M 10M
20mV
40mV
100mV
03228-012
Figure 12. Remote Temperature Error vs. Common-Mode Noise Frequency

ADT7460
Rev. C | Page 9 of 52
PRODUCT DESCRIPTION
The ADT7460 is a thermal monitor and multiple fan controller
for any system requiring monitoring and cooling. The device
communicates with the system via a serial System Management
Bus (SMBus). The serial bus controller has an optional address
line for device selection (Pin 9), a serial data line for reading
and writing addresses and data (Pin 16), and an input line for
the serial clock (Pin 1). All control and programming functions
of the ADT7460 are performed over the serial bus. In addition,
two of the pins can be reconfigured as an SMBALERT output to
indicate out-of-limit conditions.
MEASUREMENT INPUTS
The device has three measurement inputs, one for voltage and
two for temperature. It can also measure its own supply voltage
and can measure ambient temperature with its on-chip
temperature sensor.
Pin 14 is an analog input with an on-chip attenuator and is
configured to monitor 2.5 V.
Power is supplied to the chip via Pin 3, and the system also
monitors VCC through this pin. In PCs, this pin is normally
connected to a 3.3 V standby supply. This pin can, however, be
connected to a 5 V supply and monitor it without overranging.
Remote temperature sensing is provided by the D1± and D2±
inputs, to which diode-connected, external temperature-sensing
transistors, such as a 2N3904 or CPU thermal diode, may be
connected.
The ADC also accepts input from an on-chip band gap
temperature sensor, which monitors system ambient
temperature.
SEQUENTIAL MEASUREMENT
When the ADT7460 monitoring sequence is started, it cycles
sequentially through the measurement of 2.5 V input and the
temperature sensors. Measured values from these inputs are
stored in value registers. These can be read out over the serial
bus or can be compared with programmed limits stored in the
limit registers. The results of out-of-limit comparisons are
stored in the status registers, which can be read over the serial
bus to flag out-of-limit conditions.
RECOMMENDED IMPLEMENTATION
Configuring the ADT7460 as in Figure 13 allows the systems
designer the following features:
•Two PWM outputs for fan control of up to three fans (the
front and rear chassis fans are connected in parallel).
•Three TACH fan speed measurement inputs.
•VCC measured internally through Pin 3.
•CPU temperature measured using Remote 1 temperature
channel.
•Ambient temperature measured through Remote 2
temperature channel.
•Bidirectional THERM pin. Allows Intel Pentium 4
PROCHOT monitoring and can function as an
overtemperature THERM output.
•SMBALERT system interrupt output.
ICH
TACH2
D1+
D1–
D2+
D2–
TACH1
P
AMBIENT
TEMPERATURE
PWM3
TACH3
GND
ADT7460
SCL
SMBALERT
SDA
WM1
THERM PROCHOT
FRONT
CHASSIS
3228-013
FAN
REAR
CHASSIS
FAN
Figure 13. Recommended Implementation

ADT7460
Rev. C | Page 10 of 52
DRES
-functio
ADT7460 AD S SELECTION
n PWMPin 8 is the dual 3/ADDRESS ENABLE pin. If
ower-up, the ADT7460 reads the state of
Pin 8 is pulled low on p
ACH4/ADDRE
Pin 9 (T SS SELECT/THERM) to determine the
s. If Pin 8 i
ADT7460’s slave addres s high on power-up, the
7460 defaults to SM
ribed in more de
Table 41 to Table 81 describe the registers in more detail.
Table 4. Summary Inte
ADT Bus Slave Address 0x2E. This function
is desc tail later.
INTERNAL REGISTERS OF THE ADT7460
Table 4 summarizes the ADT7460’s principal internal registers.
rnal Registers
Register Description
Configuration These registers provide control and configuration of the ADT7460, including alternate pinout functionality.
Address Pointer This register contains the address that selects one of the other internal registers. When writing to the ADT7460, the
first byte of data is always a register address, which is written to the address pointer register.
Status Registers These registers provide the status of each limit comparison and are used to signal out-of-limit conditions on the
temperature, voltage, or fan speed channels. If Pin 14 or Pin 5 is configured as SMBALERT, this pin asserts low
whenever an unmasked status bit is set.
Interrupt Mask These registers allow each interrupt status event to be masked when Pin 14 or Pin 5 is configured as an SMBALERT
output.
Value and Limit The results of analog voltage input, temperature, and fan speed measurements are stored in these registers, along
with their limit values.
Offset These registers allow each temperature channel reading to be offset by a twos complement value written to these
registers.
TMIN These registers program the starting temperature for each fan under automatic fan speed control.
TRANGE These registers program the temperature-to-fan speed control slope in automatic fan speed control mode for each
PWM output.
Operating Point These registers define the target operating temperatures for each thermal zone when running under dynamic TMIN
control. This function allows the cooling solution to adjust dynamically in response to measured temperature and
system performance.
Enhance Acoustics These registers allow each PWM output controlling fan to be tweaked to enhance the system’s acoustics.

ADT7460
Rev. C | Page 11 of 52
THEORY OF OPERATION
SERIAL BUS INTERFACE
Control of the ADT7460 is carried out using the serial System
Management Bus (SMBus). The ADT7460 is connected to this
bus as a slave device, under the control of a master controller.
The ADT7460 has a 7-bit serial bus address. When the device is
powered up with Pin 8 (PWM3/ADDRESS ENABLE) high, the
ADT7460 has a default SMBus address of 0101110 or 0x2E. If
more than one ADT7460 is to be used in a system, each ADT7460
should be placed in address select mode by strapping Pin 8 low
on power-up. The logic state of Pin 9 then determines the
device’s SMBus address. The logic state of these pins is sampled
on power-up.
The device address is sampled and latched on the first valid
SMBus transaction, more precisely, on the low-to-high
transition at the beginning of the eighth SCL pulse, when the
serial address byte matches the selected slave address. The
selected slave address is chosen using the ADDRESS ENABLE
/ADDRESS SELECT pins. Any attempted changes in the
address has no effect after this.
Table 5. Address Select Mode
Pin 8 State Pin 9 State Address
0 Low (10 kΩ to GND) 0101100 (0x2C)
0 High (10 kΩ pull-up) 0101101 (0x2D)
1 Don’t Care 0101110 (0x2E) (default)
ADT7460
9
8
ADDR_SEL
PWM3/ADDR_EN
VCC
10k Ω
ADDRESS = 0x2E
03228-014
Figure 14. Default SMBus Address 0x2E
ADT7460
9
8
ADDR_SEL
PWM3/ADDR_EN
10k
Ω
ADDRESS = 0x2C
03228-015
ADT7460
ADDR_SEL
PWM3/ADDR_EN
ADDRESS = 0x2D
9
8
V
CC
10k Ω
03228-016
Figure 16. SMBus Address 0x2D (Pin 9 = 1)
Figure 15. SMBus Address 0x2C (Pin 9 = 0)
ADT7460
9
8
ADDR_SEL
PWM3/ADDR_EN NC
V
CC
10kΩ
DO NOT LEAVE ADDR_EN
AN
TABLE
UNCONNECTED. C
CAUSE UNPREDIC
ADDRESSES
CARE SHOULD BE TAKEN TO ENSURE THAT PIN
8
(PWM3/ADDR_EN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 8
FLOATING COULD CAUSE THE ADT7460 TO POWER UP WITH AN
UNEXPECTED ADDRESS.
NOTE THAT IF THE ADT7460 IS PLACED INTO ADDRESS SELEC
T
MODE, PINS 8 AND 9 CAN BE USED AS THE ALTERNATE FUNC
-
T
IONS (PWM3, TACH4/THERM) ONLY IF THE CORRECT CIRCUIT IS
MUXED IN AT THE CORRECT TIME.
03228-017
Figure 17. Unpredictable SMBus Address if Pin 8 is Unconnected
facility to make hardwired changes to the SMBus slav
ess allows the user to avoid conflicts with other devices
The e
addr
shar
ADT
The
1.
.
the serial bus respond to the
of
ing the same serial bus, for example, if more than one
7460 is used in a system.
serial bus protocol operates as follows:
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high
This indicates that an address/data stream will follow. All
slave peripherals connected to
star condition and shift in the next eight bits, consisting
a 7-bit address (MSB first) plus a R/Wbit, which
determine the direction of the data transfer, that is,
whether data is written to or read from the slave device.
The peripheral whose address corresponds to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known
as the Acknowledge bit. All other devices on the bus no
remain idle while the selected device
w
waits for data to be
read from or written to it. If the R/Wbit is a 0, the master
writes to the slave device. If the R/Wbit is a 1, the master
reads from the slave device.

ADT7460
Rev. C | Page 12 of 52
2.
ur
op signal. The number
ns
mode, the master pulls the data line
before the
before the 10th clock pulse, then high during the 10th clock
pulse to assert a stop condition.
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
gisters or read data
s pointer register.
llustrated in Figure 18. The device address is sent over
the bus followed by R/W
Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an Acknowledge bit
from the slave device. Transitions on the data line must occ
during the low period of the clock signal and remain stable
during the high period, as a low-to-high transition when the
clock is high may be interpreted as a st
of data bytes that can be transmitted over the serial bus in a
single read or write operation is limited only by what the
master and slave devices can handle.
3. When all data bytes have been read or written, stop conditio
are established. In write
high during the 10th clock pulse to assert a stop condition. In
read mode, the master device overrides the acknowledge bit
by pulling the data line high during the low period
ninth clock pulse. This is known as No Acknowledge. The
master then takes the data line low during the low period
the beginning and cannot subsequently be changed without
starting a new operation.
In the case of the ADT7460, write operations contain either one
or two bytes, and read operations contain one byte.
To write data to one of the device data re
from it, the address pointer register must be set so that the
correct data register is addressed. Then data can be written in
that register or read from it. The first byte of a write operation
always contains an address that is stored in the address pointer
register. If data is to be written to the device, the write operation
contains a second data byte that is written to the register
selected by the addres
This is i
being set to 0. This is followed by two
data bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the address pointer
register. The second data byte is the data to be written to the
internal data register.
R/W
0
SCL
SDA 111A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7460
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
11
ACK. BY
ADT7460
9
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7460 STOP BY
MASTER
FRAME 3
DATA
BYTE
19
SCL (CONTINUED)
SDA (CONTINUED)
03228-018
0
9
Figure 18. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register

ADT7460
Rev. C | Page 13 of 52
When reading data from a register, there are two possibilities:
•If the ADT7460’s address pointer register value is unknown
or not the desired value, it is first necessary to set it to the
correct value before data can be read from the desired data
register. This is done by performing a write to the ADT7460
as before, but only the data byte containing the register
address is sent because data is not to be written to the
register. This is shown in Figure 19.
A read operation is then performed, consisting of the serial
bus address, R/Wbit set to 1, followed by the data byte
read from the data register. This is shown in Figure 20.
•If the address pointer register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register, so Figure 19 can be omitted.
It is possible to read a data byte from a data register without first
writing to the address pointer register if the address pointer
register is already at the correct value. However, it is not possible
to write data to a register without writing to the address pointer
register because the first data byte of a write is always written to
the address pointer register.
In Figure 18 to Figure 20, the serial bus address is shown as the
default value 01011(A1)(A0), where A1 and A0 are set by the
address select mode function previously defined.
In addition to supporting the Send Byte and Receive Byte
protocols, the ADT7460 also supports the Read Byte protocol
(see System Management Bus specifications Rev. 2.0 for more
information).
If it is required to perform several read or write operations in
succession, the master can send a repeat start condition instead
of a stop condition to begin a new operation.
Write Operations
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADT7460 are discussed below. The following abbreviations are
used in the diagrams:
S—start
P—stop
R—read
W—write
A—acknowledge
A—no acknowledge
The ADT7460 uses the following SMBus write protocols:
Send Byte
In this operation, the master device sends a single command
byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
R/W
0
SCL
SDA 10
11A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7460 STOP BY MASTER
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
11
ACK. BY
ADT7460
9
03228-019
9
Figure 19. Writing to the Address Pointer Register Only
R/
0
SDA 10
11A1 A0
START BY
MASTER
SCL
D7 D6 D5 D4 D3 D2 D1 D0
NO ACK. BY
MASTER STOP BY MASTER
FRAME 1
SERIAL BUS ADDRESS
ACK
ADT7460
BYTE
11
. BY
9
FRAME 2
DATA BYTE FROM ADT7460
03228-020
W
9
ing Data from a Previously Selected Register Figure 20. Read

ADT7460
Rev. C | Page 14 of 52
7460, the send byte protocol is used to write to theFor the ADT
address pointer register for a subsequent single-byte read from
the same address. This is illustrated in Figure 21.
SLAVE WASAP REGISTER
03228-021
ADDRESS ADDRESS
231564
g a Register Address for Subsequent Read
ely after
tin art
d nd carry out a
single-byte read without asserting an intermediate stop
d
i
h ends a command byte and
1. evice asserts a start condition on SDA.
slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The maste
s ACK on SDA.
asserts ACK on SDA.
n Figure 22.
Figure 21. Settin
If it is required to read data from the register immediat
set g up the address, the master can assert a repeat st
con ition immediately after the final ACK a
con ition.
Wr te Byte
In t is operation, the master device s
one data byte to the slave device as follows:
The master d
2. The master sends the 7-bit
r sends the register address.
5. The slave assert
6. The master sends a data byte.
7. The slave
8. The master asserts a stop condition on SDA to end the
transaction.
This is illustrated i
SLAVE
ADDRESS ADDRESS
Figure
REGISTER
24653178
DATAAAWSAP
03228-022
22. Single-Byte Write to a Register
us read protocols.
e
e
regis have been set up previously. In this
operation, the master device receives a single byte from a slave
A.
2. The master sends the 7-bit ave address followed by the
read bit (
vice asserts ACK on SDA.
A.
a send byte or by write byte operation.
Read Operations
The ADT7460 uses the following SMB
Rec ive Byte
This is useful when repeatedly reading a single register. Th
ter address needs to
device as follows:
1. The master device asserts a start condition on SD
sl
high).
3. The addressed slave de
4. The master receives a data byte.
5. The master asserts NO ACK on SD
6. The master asserts a stop condition on SDA and the
transaction ends.
In the ADT7460, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by
SLAVE
ADDRESS
SWA AP
03228-023
213564
REGISTER
ADDRESS
Figure 23. Single-Byte Read from a Register
Alert Response Address
r t
allow
mul
The
Ale t response address (ARA) is a feature of SMBus devices tha
s an interrupting device to identify itself to the host when
tiple devices exist on the same bus.
SMBALERT output can be used as an interrupt output or
can be used as an SMBALERT. One or more outputs can be
ected to a commonconn SMBALERT line connected to
ter. If a device’s
the
mas SMBALERT line goes low, the following
1.
occurs:
SMBALERT is pulled low.
Master2. initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address, which must not be used as a specific device
address.
3. The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known, and it
can be interrogated in the usual way.
4. If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority in
accordance with normal SMBus arbitration.
5. Once the ADT7460 has responded to the alert response
address, the master must read the status registers and the
SMBALERT is cleared only if the error condition has gone
away.

ADT7460
Rev. C | Page 15 of 52
SMBus Timeout
The ADT7460 includes an SMBus timeout feature. If there is no
SMBus activity for 25 ms, the ADT7460 assumes that the bus is
locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it can
be disabled.
Table 6. Configuration Register 1 (Reg. 0x40)
Bit Description
<6> TODIS 0: SMBus timeout enabled (default)
<6> TODIS 1: SMBus timeout disabled
VOLTAGE MEASUREMENT INPUT
The ADT7460 has one external voltage measurement channel.
It can also measure its own supply voltage, VCC.
Pin 14 may be configured to measure a 2.5 V supply. The VCC
supply voltage measurement is carried out through the VCC pin
(Pin 3). Setting Bit 7 of Configuration Register 1 (Reg. 0x40)
allows a 5 V supply to power the ADT7460 and be measured
without overranging the VCC measurement channel. The 2.5 V
input can be used to monitor a chipset supply voltage in
computer systems.
Analog-to-Digital Converter
All analog inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter. This has a resolution
of 10 bits. The basic input range is 0 V to 2.25 V, but the input
has built-in attenuators to allow measurement of 2.5 V without
any external components. To allow the tolerance of the supply
voltage, the ADC produces an output of 3/4 full scale (768d or
0x300) for the nominal input voltage and so has adequate
headroom to deal with overvoltages.
Input Circuitry
The internal structure for the 2.5 V analog input is shown in
Figure 24. The input circuit consists of an input protection
diode, an attenuator, plus a capacitor to form a first-order low-
pass filter that gives the input immunity to high frequency
noise.
Table 7. Voltage Measurement Registers
Register Description Default
0x20 2.5 V reading 0x00
0x22 VCC reading 0x00
Associated with the voltage measurement channels are a high
and low limit register. Exceeding the programmed high or low
limit causes the appropriate status bit to be set. Exceeding either
limit can also generate SMBALERT interrupts.
Table 8. 2.5 V Limit Registers
Register Description Default
0x44 2.5 V low limit 0x00
0x45 2.5 V high limit 0xFF
0x48 VCC low limit 0x00
0x49 VCC high limit 0xFF
2.5V
IN
45kΩ
94kΩ30pF
03228-024
Figure 24. Structure of Analog Inputs
Table 9 shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 711 µs and averages 16 conversions to reduce noise; a
measurement takes nominally 11.38 ms.

ADT7460
Rev. C | Page 16 of 52
Table 9. 10-Bit A/D Output Code vs. VIN
Input Voltage A/D Output
5 VIN VCC (3.3 VIN)12.5 VIN Decimal Binary (10 Bits)
<0.0065 <0.0042 <0.0032 0 00000000 00
0.0065–0.0130 0.0042–0.0085 0.0032–0.0065 1 00000000 01
0.0130–0.0195 0.0085–0.0128 0.0065–0.0097 2 00000000 10
0.0195–0.0260 0.0128–0.0171 0.0097–0.0130 3 00000000 11
0.0260–0.0325 0.0171–0.0214 0.0130–0.0162 4 00000001 00
0.0325–0.0390 0.0214–0.0257 0.0162–0.0195 5 00000001 01
0.0390–0.0455 0.0257–0.0300 0.0195–0.0227 6 00000001 10
0.0455–0.0521 0.0300–0.0343 0.0227–0.0260 7 00000001 11
0.0521–0.0586 0.0343–0.0386 0.0260–0.0292 8 00000010 00
• • • • •
• • • • •
• • • • •
1.6675–1.6740 1.1000–1.1042 0.8325–0.8357 256 (1/4 scale) 01000000 00
• • • • •
• • • • •
• • • • •
3.3300–3.3415 2.2000–2.2042 1.6650–1.6682 512 (1/2 scale) 10000000 00
• • • • •
• • • • •
• • • • •
5.0025–5.0090 3.3000–3.3042 2.4975–2.5007 768 (3/4 scale) 11000000 00
• • • • •
• • • • •
• • • • •
6.5983–6.6048 4.3527–4.3570 3.2942–3.2974 1013 11111101 01
6.6048–6.6113 4.3570–4.3613 3.2974–3.3007 1014 11111101 10
6.6113–6.6178 4.3613–4.3656 3.3007–3.3039 1015 11111101 11
6.6178–6.6244 4.3656–4.3699 3.3039–3.3072 1016 11111110 00
6.6244–6.6309 4.3699–4.3742 3.3072–3.3104 1017 11111110 01
6.6309–6.6374 4.3742–4.3785 3.3104–3.3137 1018 11111110 10
6.6374–6.4390 4.3785–4.3828 3.3137–3.3169 1019 11111110 11
6.6439–6.6504 4.3828–4.3871 3.3169v3.3202 1020 11111111 00
6.6504–6.6569 4.3871–4.3914 3.3202–3.3234 1021 11111111 01
6.6569–6.6634 4.3914–4.3957 3.3234–3.3267 1022 11111111 10
>6.6634 >4.3957 >3.3267 1023 11111111 11
1The VCC output codes listed assume that VCC is 3.3 V. If VCC input is reconfigured for 5 V operation (by setting Bit 7 of Configuration Register 1), the VCC output codes are
the same as for the 5 VIN column.

ADT7460
Rev. C | Page 17 of 52
ADDITIONAL ADC FUNCTIONS FOR
VOLTAGE MEASUREMENTS
A number of other functions are available on the ADT7460 to
offer the systems designer increased flexibility.
Turn-Off Averaging
For each voltage measurement read from a value register, 16
readings have actually been made internally and the results
averaged before being placed into the value register. If the user
wants to speed up conversion, setting Bit 4 of Configuration
Register 2 (Reg. 0x73) turns averaging off. This effectively gives
a reading 16 times faster (711 µs), but the reading may be noisier.
Bypass Voltage Input Attenuator
Setting Bit 5 of Configuration Register 2 (Reg. 0x73) removes
the attenuation circuitry from the 2.5 V input. This allows the
user to directly connect external sensors or to rescale the analog
voltage measurement inputs for other applications. The input
range of the ADC without the attenuators is 0 V to 2.25 V.
Single-Channel ADC Conversion
Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the
ADT7460 into single-channel ADC conversion mode. In this
mode, the ADT7460 can be made to read a single voltage
channel only. If the internal ADT7460 clock is used, the selected
input is read every 711 µs. The appropriate ADC channel is
selected by writing to Bits <7:5> of the TACH1 Minimum High
Byte register (Reg. 0x55).
Table 10. Configuration Register 2 (Reg. 0x73)
Bit Description
<4> 1: averaging off
<5> 1: bypass input attenuators
<6> 1: single-channel convert mode
Table 11. TACH1 Minimum High Byte (Reg. 0x55)
Bit Description
<7:5> Selects ADC channel for single-channel convert mode
Value Channel Selected
000 2.5 V
010 VCC
TEMPERATURE MEASUREMENT SYSTEM
Local Temperature Measurement
The ADT7460 contains an on-chip band gap temperature
sensor whose output is digitized by the on-chip 10-bit ADC.
The 8-bit MSB temperature data is stored in the local
temperature register (Address 0x26). As both positive and
negative temperatures can be measured, the temperature data is
stored in twos complement format, as shown in Table 12.
Theoretically, the temperature sensor and ADC can measure
temperatures from −128°C to +127°C with a resolution of
0.25°C. However, this exceeds the operating temperature range
of the device, so local temperature measurements outside this
range are not possible.
Remote Temperature Measurement
The ADT7460 can measure the temperature of two remote
diode sensors or diode-connected transistors connected to
Pins 12 and 13, or Pins 10 and 11.
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about −2 mV/°C. Unfortunately, the absolute
value of VBE varies from device to device, and individual
calibration is required to null this out, so the technique is
unsuitable for mass production. The technique used in the
ADT7460 is to measure the change in VBE when the device is
operated at two different currents. This is given by
(
)
NInqKTVBE ×=∆
where:
Kis Boltzmann’s constant.
qis the charge on the carrier.
Tis the absolute temperature in Kelvins.
Nis the ratio of the two currents.
Figure 25 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows
the external sensor as a substrate transistor provided for
temperature monitoring on some microprocessors. It could
equally well be a discrete transistor, such as a 2N3904.
IN×II
BIAS
D+
D– LPF
V
DD
V
OUT+
V
OUT–
f
C
= 65kHz
TO ADC
03228-025
REMOTE
SENSING
TRANSISTOR
CPU
THERMDA
THERMDC BIAS
DIODE
Figure 25. Signal Conditioning for Remote Diode Temperature Sensors

ADT7460
Rev. C | Page 18 of 52
If a discrete transistor is used, the collector is not grounded, and
it should be linked to the base. If a PNP transistor is used, the
base is connected to the D− input and the emitter to the D+
input. If an NPN transistor is used, the emitter is connected to
the D− input, and the base to the D+ input. Figure 26 and
Figure 27 show how to connect the ADT7460 to an NPN or
PNP transistor for temperature measurement. To prevent
ground noise from interfering with the measurement, the more
negative terminal of the sensor is not referenced to ground but
is biased above ground by an internal diode at the D− input.
To measu re ΔVBE, the sensor is switched between operating
currents of I and N × I. The resulting waveform is passed
through a 65 kHz low-pass filter to remove noise and to a
chopper stabilized amplifier that performs the functions of
amplification and rectification of the waveform to produce a dc
voltage proportional to ΔVBE. This voltage is measured by the
ADC to give a temperature output in 10-bit, twos complement
format. To further reduce the effects of noise, digital filtering is
performed by averaging the results of 16 measurement cycles. A
remote temperature measurement takes nominally 25.5 ms. The
results of remote temperature measurements are stored in
10-bit, twos complement format, as illustrated in Table 12. The
extra resolution for the temperature measurements is held in
the Extended Resolution Register 2 (Reg. 0x77). This gives
temperature readings with a resolution of 0.25°C.
2N3904
NPN
ADT7460
D+
D–
03228-026
Figure 26. Measuring Temperature by Using an NPN Transistor
2N3906
PNP
ADT7460
D+
D–
03228-027
Table 12. Temperature Data Format
Temperature Digital Output (10-Bit)1
−128°C 1000 0000 00
−125°C 1000 0011 00
−100°C 1001 1100 00
−75°C 1011 0101 00
−50°C 1100 1110 00
−25°C 1110 0111 00
−10°C 1111 0110 00
0°C 0000 0000 00
+10.25°C 0000 1010 01
+25.5°C 0001 1001 10
+50.75°C 0011 0010 11
+75°C 0100 1011 00
+100°C 0110 0100 00
+125°C 0111 1101 00
+127°C 0111 1111 00
1Bold denotes 2 LSBs of measurement in the Extended Resolution Register 2
(Reg. 0x77) with 0.25°C resolution.
Table 13. Temperature Measurement Registers
Register Description Default
0x25 Remote 1 temperature 0x80
0x26 Local temperature 0x80
0x27 Remote 2 temperature 0x80
0x77 Extended Resolution 2 0x00
Table 14. Extended Resolution Temperature Measurement
Register Bits (Addr = 0x77)
Bit Mnemonic Description
<7:6> TDM2 Remote 2 temperature LSBs
<5:4> LTMP Local temperature LSBs
<3:2> TDM1 Remote 1 temperature LSBs
Reading Temperature from the ADT7460
It is important to note that temperature can be read from the
ADT7460 as an 8-bit value (with 1°C resolution) or as a 10-bit
value (with 0.25 C resolution). If only 1°C resolution is required,
the temperature readings can be read back at any time and in no
particular order.
Figure 27. Measuring Temperature by Using a PNP Transistor
If the 10-bit measurement is required, this involves a 2-register
read for each measurement. The extended resolution register
(Reg. 0x77) should be read first. This causes all temperature
reading registers to be frozen until all temperature reading
registers have been read from. This prevents an MSB reading
from being updated while its two LSBs are being read, and vice
versa.

ADT7460
Rev. C | Page 19 of 52
Nulling Out Temperature Errors
As CPUs run faster, it becomes more difficult to avoid high
frequency clocks when routing the D+, D− traces around a
system board. Even when recommended layout guidelines are
followed, there may still be temperature errors attributed to
noise being coupled onto the D+/D− lines. High frequency
noise generally has the effect of giving temperature measure-
ments that are too high by a constant amount. The ADT7460
has temperature offset registers at Addresses 0x70, 0x72 for the
Remote 1 and Remote 2 temperature channels. By doing a one-
time calibration of the system, one can determine the offset
caused by system board noise and null it out using the offset
registers. The offset registers automatically add a twos
complement 8-bit reading to every temperature measurement.
The LSB adds 0.25°C offset to the temperature reading so the
8-bit register effectively allows temperature offsets of up to
±32°C with a resolution of 0.25°C. This ensures that the
readings in the temperature measurement registers are as
accurate as possible.
Table 15. Temperature Offset Registers
Register Description Default
0x70 Remote 1 temperature offset 0x00 (0°C)
0x71 Local temperature offset 0x00 (0°C)
0x72 Remote 2 temperature offset 0x00 (0°C)
Temperature Measurement Limit Registers
Associated with each temperature measurement channel are
high and low limit registers. Exceeding the programmed high or
low limit causes the appropriate status bit to be set. Exceeding
either limit can also generate SMBALERT interrupts.
Table 16. Temperature Measurement Limit Registers
Register Description Default
0x4E Remote 1 temperature low limit 0x81
0x4F Remote 1 temperature high limit 0x7F
0x50 Local temperature low limit 0x81
0x51 Local temperature high limit 0x7F
0x52 Remote 2 temperature low limit 0x81
0x53 Remote 2 temperature high limit 0x7F
Overtemperature Events
Overtemperature events on any of the temperature channels can
be detected and dealt with automatically in automatic fan speed
control mode. Registers 0x6A to 0x6C are the THERM limits.
When a temperature exceeds its THERM limit, all fans run at
100% duty cycle. The fans continue running at 100% until the
temperature drops below THERM – Hysteresis. (This can be
disabled by setting the BOOST bit in Configuration Register 3,
Bit 2, Register 0x78). The hysteresis value for that THERM limit
is the value programmed into Registers 0x6D and 0x6E
(hysteresis registers). The default hysteresis value is 4°C.
FANS
TEMPERATURE
100%
HYSTERESIS = (°C)
THERM LIMIT
03228-028
Figure 28.
THERM Limit Operation
ADDITIONAL ADC FUNCTIONS FOR
TEMPERATURE MEASUREMENT
A number of other functions are available on the ADT7460 to
offer the systems designer increased flexibility:
ion
g. 0x73) turns averaging off. This takes a reading
ent takes
s 1.4 ms.
e-Ch versions
g Bit eg. 0x73) places the
DT7460 into single-channel ADC conversion mode. In this
ode, the ADT7460 can be made to read a single temperature
y writing
its < CH1 minimum high byte register
x
17 iguration Register 2 (
Turn-Off Averaging
For each temperature measurement read from a value register,
16 readings have actually been made internally and the results
averaged before being placed into the value register. Sometimes
it may be necessary to take a very fast measurement, for
example, of CPU temperature. Setting Bit 4 of Configurat
Register 2 (Re
every 15.5 ms. Each remote temperature measurem
4 ms and the local temperature measurement take
Singl annel ADC Con
Settin 6 of Configuration Register 2 (R
A
m
channel only. The appropriate ADC channel is selected b
to B 7:5> of the TA
(Reg. 0 55).
Table . Conf Reg. 0x73)
Bit Description
<4> 1: Averaging off
<6> 1: single-channel convert mode
Table 18. TACH1 Minimum High Byte (Reg. 0x55)
it DescriptionB
<7:5> Selects ADC channel for single-channel convert mode
Value Channel Selected
101 Remote 1 temp
110 Local temp
111 Remote 2 temp

ADT7460
Rev. C | Page 20 of 52
AND INTERRUPTS
ues
ated with ea t channel on the ADT7460
h and low li rm the basis of
monitoring: e set for any out it
ion and dete the device. Altern ,
BALERT
LIMITS, STATUS REGISTERS,
Limit Val
Associ ch measuremen
are hig mits. These can fo system
status a status bit can b -of-lim
condit cted by polling atively
SM interrupts can be generated to flag a processor or
.
its
llowing is 6
Table 19. Volta it Registers
er lt
microcontroller of out-of-limit conditions
8-Bit Lim
The fo a list of 8-bit limits on the ADT74 0.
ge Lim
Regist Description Defau
0x44 2.5 V low limit 0x00
0x45 2.5 V high limit 0xFF
0x48 VCC low limit 0x00
0x49 VCC high limit 0xFF
Table 20. Temp e Limit Registers
er lt
eratur
Regist Description Defau
0x4E Remote 1 temperature low limit 0x81
0x4F Remote 1 temperature high 0x7F
limit
0x6A Remote 1 THERM limit 0x64
0x50 Local temperature low limit 0x81
0x51 Local temperature high limit 0x7F
0x6B Local THERM limit 0x64
0x52 Remote 2 temperature low limit 0x81
0x53 Remote 2 temperature high
limit
0x7F
0x6C Remote 2 THERM limit 0x64
Table 21. THERM Timer Limit Register
Register Description Default
0x7A THERM timer limit 0x00
16-Bit Limits
TACH ults. The fa CH
re also 1 yte and lo .
ans run re norma nly
ions of in r fan TA
n TACH asured, ex g
The fan measurements are 16-bit res n TA
limits a
Since f
6 bits, consisting of a high b
ning under speed or stalled a
w byte
lly the o
condit terest, only high limits exist fo CHs.
Since fa period is actually being me
fan.
ceedin
the limit indicates a slow or stalled
Table 22. Fan Limit Registers
Register Description Default
0x54 TACH1 minimum low byte 0xFF
0x55 TACH1 minimum high byte 0xFF
0x56 TACH2 minimum low byte 0xFF
0x57 TACH2 minimum high byte 0xFF
0x58 TACH3 minimum low byte 0xFF
0x59 TACH3 minimum high byte 0xFF
0x5A TACH4 minimum low byte 0xFF
0x5B TACH4 minimum high byte 0xFF
Out-of-Limit Comparisons
Once all limits have been programmed, the ADT7460 can be
enabled for monitoring. The ADT7460 measures all parameters
in round-robin format and sets the appropriate status bit for
out-of-limit conditions. Comparisons are done differently
depending on whether the measured value is being compared to
a high or low limit.
•High limit: > comparison performed
•Low limit: < or = comparison performed
03228-029
NO INT
LOW LIMIT
TEMP > LOW LIMIT
Figure 29. Temperature > Low Limit: No INT
INT
LOW LIMIT
TEMP = LOW LIMIT
03228-030
Figure 30. Temperature = Low Limit: INT Occurs