Analog Devices ADAV4622 User manual

Audio Processor for Advanced TV with
Sound IF Demodulator and Stereo Decoder
ADAV4622
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: [phone] www.analog.com
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FEATURES
Sound IF (SIF) processor
SIF demodulator and broadcast stereo decoder
NICAM (BG, DK, I, L), A2 (BG, DK, M), BTSC (M, N), EIAJ (M)
Automatic sound IF standard detection
Fully programmable 28-bit audio processor for enhanced
ATV sound—default TV audio flow loaded on reset
Implements Analog Devices and third-party branded audio
algorithms
Adjustable digital delay line for audio/video
Synchronization for up to 200 ms stereo delay
High performance 24-bit ADC and DAC
94 dB DNR performance on DAC channels
95 dB DNR performance on ADC channels
Dual headphone outputs with integrated amplifiers
High performance pulse-width modulation (PWM) digital
outputs
Multichannel digital baseband I/O
4 stereo synchronous digital I2S input channels
One 6-channel sample rate converter (SRC) and one
stereo SRC supporting input sample rates from
5 kHz to 50 kHz
One stereo synchronous digital I2S output
S/PDIF output with S/PDIF input mux capability
Fast I2C control
Operates from 3.3 V (analog), 1.8 V (digital core), and 3.3 V
(digital interface)
Available in 80-lead LQFP
APPLICATIONS
General-purpose consumer audio postprocessing
Home audio
DVD recorders
Home theater in a box (HTIB) systems and DVD receivers
Audio processing subsystems for DTV-ready TVs
Analog broadcast capability for iDTVs
PRODUCT OVERVIEW
The ADAV4622 is an enhanced audio processor targeting
advanced TV applications with full support for digital and
analog baseband audio as well as multistandard broadcast SIF
demodulation and decoding.
The audio processor, by default, loads a dedicated TV audio
flow that incorporates full matrix switching (any input to any
output), automatic volume control that compensates for volume
changes during advertisements or when switching channels,
dynamic bass, a multiband equalizer, and up to 200 ms of stereo
delay memory for audio-video synchronization.
Alternatively, Analog Devices, Inc., offers an award-winning
graphical programming tool (SigmaStudio™) that allows custom
flows to be quickly developed and evaluated. This allows the
creation of customer-specific audio flows, including use of the
Analog Devices library of third-party algorithms.
The analog I/O integrates Analog Devices proprietary
continuous-time, multibit Σ-Δ architecture to bring a higher
level of performance to ATV systems, required by third-party
algorithm providers to meet system branding certification. The
analog input is provided by 95 dB dynamic range (DNR) ADCs,
and analog output is provided by 94 dB DNR DACs.
The main speaker outputs can be supplied as a digitally
modulated PWM stream to support digital amplifiers.
The ADAV4622 includes multichannel digital inputs and
outputs. In addition, digital input channels can be routed
through integrated sample rate converters (SRC), which are
capable of supporting any arbitrary sample rate from 5 kHz
to 50 kHz.

ADAV4622
Rev. B | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Product Overview............................................................................. 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Performance Parameters ............................................................. 4
Timing Specifications .................................................................. 9
Timing Diagrams........................................................................ 10
Absolute Maximum Ratings.......................................................... 12
Thermal Resistance .................................................................... 12
Thermal Conditions................................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions........................... 13
Typical Performance Characteristics ........................................... 16
Terminology .................................................................................... 18
Pin Functions .................................................................................. 19
SDIN0, SDIN1, SDIN2, and SDIN3/SPDIF_IN0................... 19
LRCLK0, BCLK0, LRCLK1, BCLK1, LRCLK2, and BCLK2 19
SDO0/AD0 .................................................................................. 19
SPDIF_OUT (SDO1) ................................................................. 19
MCLKI/XIN................................................................................ 19
XOUT........................................................................................... 19
MCLK_OUT ............................................................................... 19
SDA............................................................................................... 19
SCL ............................................................................................... 20
MUTE .......................................................................................... 20
RESET .......................................................................................... 20
AUXIN1L, AUXIN2L, AUXIN1R, and AUXIN2R................ 20
AUXOUT1L, AUXOUT2L, AUXOUT3L, AUXOUT4L,
AUXOUT1R, AUXOUT2R, AUXOUT3R, and AUXOUT4R
....................................................................................................... 20
HPOUT1L, HPOUT2L, HPOUT1R, and HPOUT2R .......... 20
PLL_LF......................................................................................... 20
VREF............................................................................................ 20
FILTA and FILTD....................................................................... 20
PWM1A, PWM1B, PWM2A, PWM2B, PWM3A, PWM3B,
PWM4A, and PWM4B.............................................................. 20
PWM_READY ........................................................................... 20
AVDD .......................................................................................... 20
DVDD.......................................................................................... 20
ODVDD....................................................................................... 20
DGND.......................................................................................... 20
AGND.......................................................................................... 20
ODGND ...................................................................................... 20
SIF_REFP, SIF_REFCM, and SIF_REFN ................................ 20
SIF_IN1 and SIF_IN2 ................................................................ 20
SIF_PGA_REF ............................................................................ 20
ISET.............................................................................................. 20
Functional Descriptions ................................................................ 21
SIF Processor............................................................................... 21
Master Clock Oscillator............................................................. 21
I2C Interface ................................................................................ 22
ADC Inputs................................................................................. 22
I2S Digital Audio Inputs ............................................................ 22
DAC Voltage Outputs ................................................................ 23
PWM Outputs ............................................................................ 24
Headphone Outputs................................................................... 24
I2S Digital Audio Outputs ......................................................... 24
S/PDIF Input/Output................................................................. 25
Hardware Mute Control ............................................................ 25
Audio Processor ......................................................................... 25
Graphical Programming Environment ................................... 25
Application Layer ....................................................................... 25
Loading a Custom Audio Processing Flow............................. 26
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
7/09—Rev. A to Rev. B
Added Advantiv Logo ...................................................................... 1
Change to PWM Outputs Section................................................ 24
Change to Hardware Mute Control, Graphical Programming
Environment, and Application Layer Sections........................... 25
Changes to Ordering Guide .......................................................... 28
11/08—Revision A: Initial Version

ADAV4622
Rev. B | Page 3 of 28
FUNCTIONAL BLOCK DIAGRAM
AUDIO
PROCESSOR
ADAV4622
A-V
SYNCHRONOUS
DELAY
MEMORY
I
2
C INTERFACE
SIF PROCESSOR
AD0
SYNCHRONOUS
MULTICHANNEL
DIGITAL INPUTS
6-CHANNEL SRC
ASYNCHRONOUS
DIGITAL INPUT
2-CHANNEL SRC
ASYNCHRONOUS
DIGITAL INPUT
SYSTEM
CLOCKS
PLL
SPDIF_IN0
SPDIF_IN1
SPDIF_IN2
SPDIF_IN3
SPDIF_IN4
SPDIF_IN5
SPDIF_IN6
SPDIF_OUT/SDO1
S/PDIF I/O
PWM
DIGITAL
OUTPUT
PWM1A
PWM1B
PWM2A
PWM2B
PWM3A
PWM3B
PWM4A
PWM4B
PWM_READY
BCLK1
LRCLK1
SDO0/AD0
HPOUT2L
HPOUT2R
AUXOUT2L
AUXOUT2R DAC
HPOUT1L
AUXOUT4R
AUXOUT4L
HPOUT1R
DAC
AUXOUT1L
AUXOUT1R
DAC
AUXOUT3L
AUXOUT3R
DAC
SCL
SDA
BCLK2
LRCLK2
BCLK0
LRCLK0
SDIN0
SDIN1
SDIN2
SDIN3
XOUT
MCLKI/XIN
MCLK_OUT
SIF_IN1
SIF_IN2
AUXIN2L
AUXIN2R
ADC
AUXIN1L
AUXIN1R
ADC
DIGITAL
OUTPUTS
BCLK1
LRCLK1
MUTE
07068-001
Figure 1. ADAV4622 with PWM-Based Speaker Outputs

ADAV4622
Rev. B | Page 4 of 28
SPECIFICATIONS
AVDD = 3.3 V, DVDD = 1.8 V, ODVDD = 3.3 V, operating temperature = −40°C to +85°C, master clock = 24.576 MHz, measurement
bandwidth = 20 Hz to 20 kHz, ADC input signal = DAC output signal = 1 kHz, unless otherwise noted.
PERFORMANCE PARAMETERS
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
SIF ADC INPUT SECTION
Analog Input Frequency Range 10 MHz
Recommended Analog Input Level 90 ± 18 dB dBu FM, AGC in PGA priority mode
Maximum Analog Input Range 1.6 V p-p Default setting
Input Impedance 12 kΩ PGA Gain = 0 dB
6 KΩ PGA Gain = 10 dB
2.3 kΩ PGA Gain = 20 dB
DC Bias Level 1.9 V
SIF Input Isolation 60 dB SIF_IN1 to SIF_ IN2
FM Limiting Sensitivity 32 dBu A2 (DK), Mono, deviation mode = 100%, fFM = 400 Hz,
Δf = 50 kHz, BW = 20 Hz to 15 kHz, rms detector
31 dBu A2 (I), Mono, deviation mode = 100%, fFM = 400 Hz,
Δf = 50 kHz, BW = 20 Hz to 15 kHz, rms detector
31 dBu A2 (BG), Mono, deviation mode = 100%, fFM = 400 Hz,
Δf = 50 kHz, BW = 20 Hz to 15 kHz, rms detector
34 dBu BTSC (M, N), Mono, deviation mode = 100%,
fFM = 400 Hz, Δf = 25 kHz, BW = 20 Hz to 15 kHz,
rms detector
28.5 dBu A2 (M), Mono, deviation mode = 100%, fFM = 400 Hz,
Δf = 25 kHz, BW = 20 Hz to 15 kHz, rms detector
30 dBu EIAJ (M), Mono, deviation mode = 100%, fFM = 400 Hz,
Δf = 25 kHz, BW = 20 Hz to 15 kHz, rms detector
FM Output Level at 25% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 12.5 kHz, rms detector
53.6 % FS BTSC (M, N), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 6.25 kHz, rms detector
56.3 % FS A2 (M), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 6.25 kHz, rms detector
56.7 % FS EIAJ (M), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 6.25 kHz, rms detector
FM Output Level at 50% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 25 kHz, rms detector
53.6 % FS BTSC (M, N), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 12.5 kHz, rms detector
56.3 % FS A2 (M), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 12.5 kHz, rms detector
56.7 % FS EIAJ (M), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 12.5 kHz, rms detector
FM Output Level at 100% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 50 kHz, rms detector
53.6 % FS BTSC (M, N), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 25 kHz, rms detector
56.3 % FS A2 (M), Mono, VSIF = 100 mV, fFM = 400 Hz, Δf = 25 kHz,
rms detector
56.7 % FS EIAJ (M), Mono, VSIF = 100 mV, fFM = 400 Hz, Δf = 25 kHz,
rms detector
FM Output Level at 200% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, VSIF =100 mV, fFM = 400 Hz,
Δf = 100 kHz, rms detector
53.6 % FS BTSC (M, N), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 50 kHz, rms detector
56.3 % FS A2 (M), Mono, VSIF = 100 mV, fFM = 400 Hz, Δf = 50 kHz,
rms detector
56.7 % FS EIAJ (M), Mono, VSIF = 100 mV, fFM = 400 Hz, Δf = 50 kHz,
rms detector

ADAV4622
Rev. B | Page 5 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
FM Output Level at 400% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 200 kHz, rms detector
53.6 % FS BTSC (M, N), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 100 kHz, rms detector
56.4 % FS A2 (M), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 100 kHz, rms detector
56.7 % FS EIAJ (M), Mono, VSIF = 100 mV, fFM = 400 Hz, Δf = 100 kHz,
rms detector
FM Output Level at 800% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 400 kHz, rms detector
53.6 % FS BTSC (M, N), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 200 kHz, rms detector
56.3 % FS A2 (M), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 200 kHz, rms detector
56.7 % FS EIAJ (M), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 200 kHz, rms detector
AM Rejection Ratio 69.5 dB A2 (DK), Mono, deviation mode = 100%, VSIF = 100 mV,
fFM = 400 Hz, Δf = 27 kHz, fAM = 400 Hz, MODAM = 30%,
BW = 20 Hz to 15 kHz, rms detector
70 dB A2 (I), Mono, deviation mode = 100%, VSIF = 100 mV,
fFM = 400 Hz, Δf = 27 kHz, fAM = 400 Hz, MODAM = 30%,
BW = 20 Hz to 15 kHz, rms detector
70 dB A2 (BG), Mono, deviation mode = 100%, VSIF = 100 mV,
fFM = 400 Hz, Δf = 27 kHz, fAM = 400 Hz, MODAM = 30%,
BW = 20 Hz to 15 kHz, rms detector
70.5 dB Mono (M), deviation mode = 100%, VSIF = 100 mV,
fFM = 400 Hz, Δf = 13.5 kHz, fAM = 400 Hz, MODAM = 30%,
BW = 20 Hz to 15 kHz, rms detector
AM Sensitivity 40 dBu Mono (L), fAM = 400 Hz, MOD = 30%, BW = 20 Hz to 15 kHz,
rms detector, (S + N)/N = 10 dB
BTSC (M) PERFORMANCE Measured at analog audio output, video = 75% color bar,
fSC = 4.5 MHz, fFM = 1 kHz, Δf = 25 kHz (100%), deemphasis =
75 μs, measuring BW = 20 Hz to 15 kHz with dBX NR
Dynamic Range
Stereo Channel 62 dB Stereo L or R (L = −R), 100%, 1 kHz
SAP Channel 68 dB SAP channel with Mono 100%, 1 kHz
Total Harmonic Distortion + Noise
Stereo Channel −46 dB Stereo L or R (L = −R), 100%, 1 kHz
SAP Channel −40 dB SAP 100%, 1 kHz
Frequency Response fFM = 20 Hz to 12 kHz
Stereo Channel +0.1/−0.7 dB Stereo L or R, 50%, (L = −R)
SAP Channel +2.5/−2.5 dB SAP 50%, Mono 100%, 1 kHz
Crosstalk
Stereo-to-SAP Channel −74 dB L or R 50%, 1 kHz
SAP-to-Stereo Channel −71 dB SAP 50%, 1 kHz
Stereo Separation dBX 30 dB L off, R 50%, 1 kHz
EIAJ (M) PERFORMANCE Measured at analog audio output, video = 75% color bar,
fSC = 4.5 MHz, fFM = 1 kHz, Δf = 25 kHz (100%),
deemphasis = 75 μs, measuring BW = 20 Hz to 15 kHz
Dynamic Range
Stereo Channel 58 dB Stereo L or R, 100%, 1 kHz
Dual Channel 56 dB Dual channel with Mono 100%, 1 kHz
Total Harmonic Distortion + Noise
Stereo Channel −56 dB Stereo L or R, 100%, 1 kHz
Dual Channel −47 dB Dual 50%, 1 kHz
Frequency Response fFM = 20 Hz to 10 kHz
Stereo Channel +0.03/−0.53 dB Stereo L or R, 100%
Dual Channel +0.17/−1.4 dB Dual 100%, Mono 100%, 1 kHz
Crosstalk
Main-to-Dual Channel −75 dB Main 100%, 1 kHz
Dual-to-Main Channel −83 dB Dual 100%, 1 kHz
Stereo Separation 39 dB Stereo L or R, 100%, 1 kHz

ADAV4622
Rev. B | Page 6 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
A2 (M) PERFORMANCE Measured at analog audio output, video = 75% color bar,
fSC1 = 4.5 MHz, fSC2 = 4.724 MHz, fFM = 1 kHz, Δf = 25 kHz
(100%), deemphasis = 75 μs, measuring BW = 20 Hz to
15 kHz
Dynamic Range 60 dB Mono 100%, 1 kHz
Total Harmonic Distortion + Noise −64 dB Mono 100%, 1 kHz
Frequency Response +0.4/−0.05 dB Mono 100%, fFM = 25 Hz to 15 kHz
Crosstalk (Dual) −88 dB Mono or dual off, 100%, 1 kHz
Channel Separation (Stereo) 66 dB Stereo L off, R 50%, 1 kHz
A2 (DK1/DK2/DK3) PERFORMANCE Measured at analog audio output, video = 75% color bar,
fSC1 = 6.5 MHz, fSC2 = 6.742 MHz, (DK2 worst case),
fFM = 1 kHz, Δf = 50 kHz (100%), deemphasis = 50 μs,
measuring BW = 20 Hz to 15 kHz
Dynamic Range 74 dB Mono 100%, 1 kHz
Total Harmonic Distortion + Noise −66 dB Mono 100%, 1 kHz
Frequency Response +0.1/−0.3 dB Mono 100%, fFM = 20 Hz to 15 kHz
Crosstalk (Dual) −88 dB Mono or dual off, 100%, 1 kHz
Channel Separation (Stereo) 77 dB Stereo L off, R 50%, 1 kHz
A2 (BG) PERFORMANCE Measured at analog audio output, video = 75% color bar,
fSC1 = 5.5 MHz, fSC2 = 5.742 MHz, fFM = 1 kHz,
Δf = 50 kHz (100%), deemphasis = 50 μs,
measuring BW = 20 Hz to 15 kHz
Dynamic Range 74 dB Mono 100%, 1 kHz
Total Harmonic Distortion + Noise −61 dB Mono 100%, 1 kHz
Frequency Response +0.1/−0.3 dB Mono 100%, fFM = 25 Hz to 15 kHz
Crosstalk (Dual) −89 dB Mono or dual off, 100%, 1 kHz
Channel Separation (Stereo) 70 dB Stereo L off, R 50%, 1 kHz
NICAM (I) PERFORMANCE Measured at analog audio output, video = 75% color bar,
1 kHz, unweighted, deemphasis = J17, measuring BW = 20
Hz to 15 kHz
Dynamic Range 72 dB Stereo L or R, 0 dB, 1 kHz
Total Harmonic Distortion + Noise −63 dB Stereo L or R, 0 dB, 1 kHz
Frequency Response −1.3/+0.07 dB Stereo L or R, 0 dB
Crosstalk −80 dB Mono or dual, 0 dB, 1 kHz
Stereo Separation 73 dB L or R, 0 dB, 1 kHz
Bit Error Rate 0 FM and NICAM nominal conditions
NICAM (BG, DK, L) PERFORMANCE Measured at analog audio output, video = 75% color bar,
1 kHz, unweighted, deemphasis = J17, measuring BW =
20 Hz to 15 kHz
Dynamic Range 72 dB Stereo L or R, 0 dB, 1 kHz
Total Harmonic Distortion + Noise −63 dB Stereo L or R, 0 dB, 1 kHz
Frequency Response −1.3/+0.07 dB Stereo L or R, 0 dB
Crosstalk −80 dB Mono or dual, 0 dB, 1 kHz
Stereo Separation 74 dB L or R, 0 dB, 1 kHz
Bit Error Rate 0 FM and NICAM nominal conditions
AM PERFORMANCE Measured at analog audio output, 1 kHz,
AM carrier 6.5 MHz measuring BW = 20 Hz to 15 kHz
Dynamic Range
RMS/FLAT 55 dB AM = 54% modulation
QP/CCIR 35 dB CCIR filter, AM = 54% modulation
Total Harmonic Distortion + Noise −49 dB AM = 54% modulation
Frequency Response +0.03/−1.2 dB AM = 54% modulation
REFERENCE SECTION
Absolute Voltage VREF 1.53 V
VREF Temperature Coefficient 100 ppm/°C

ADAV4622
Rev. B | Page 7 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
ADC SECTION
Number of Channels 4 Two stereo channels
Full-Scale Input Level 100 μA rms
Resolution 24 Bits
Dynamic Range (Stereo Channel)
A-Weighted 95 dB −60 dBFS with respect to full-scale analog input
Total Harmonic Distortion + Noise (Stereo
Channel)
−90 dB −3 dBFS with respect to full-scale analog input
Gain Mismatch 0.2 dB Left- and right-channel gain mismatch
Crosstalk (Left to Right, Right to Left) −110 dB
Gain Error −1 dB Input signal is 100 μA rms
Current Setting Resistor (RISET) 20 kΩ External resistor to set current input range of ADC for
nominal 2.0 V rms input signal
Power Supply Rejection −87 dB 1 kHz, 300 mV p-p signal at AVDD
ADC DIGITAL DECIMATOR FILTER
CHARACTERISTICS
At 48 kHz, guaranteed by design
Pass Band 22.5 kHz
Pass-Band Ripple ±0.0002 dB
Stop Band 26.5 kHz
Stop-Band Attenuation 100 dB
Group Delay 1040 μs
PWM SECTION
Frequency 384 kHz Guaranteed by design
Modulation Index 0.976 Guaranteed by design
Dynamic Range
A-Weighted 98 dB −60 dB with respect to full-scale code input
Total Harmonic Distortion + Noise −78 dB −3 dB with respect to full-scale code input
DAC SECTION
Number of Auxiliary Output Channels 8 Four stereo channels
Resolution 24 Bits
Full-Scale Analog Output 1 V rms
Dynamic Range
A-Weighted 94 dB −60 dBFS with respect to full-scale code input
Total Harmonic Distortion + Noise −86 dB −3 dBFS with respect to full-scale code input
Crosstalk (Left to Right, Right to Left) −102 dB
Interchannel Gain Mismatch 0.1 dB Left- and right-channel gain mismatch
Gain Error 0.525 dB 1 V rms output
DC Bias 1.53 V
Power Supply Rejection −90 dB 1 kHz, 300 mV p-p signal at AVDD
Output Impedance 235 Ω
DAC DIGITAL INTERPOLATION FILTER
CHARACTERISTICS
At 48 kHz, guaranteed by design
Pass Band 21.769 kHz
Pass-Band Ripple ±0.01 dB
Transition Band 23.95 kHz
Stop Band 26.122 kHz
Stop-Band Attenuation 75 dB
Group Delay 580 μs
HEADPHONE AMPLIFIER Measured at headphone output with 32 Ω load
Number of Channels 4 Two stereo channels
Full-Scale Output Power 31 mW rms 1 V rms output
Dynamic Range
A-Weighted 93 dB −60 dBFS with respect to full-scale code input
Total Harmonic Distortion + Noise −83 dB −3 dBFS with respect to full-scale code input
Interchannel Gain Mismatch 0.1 dB
DC Bias 1.53 V
Power Supply Rejection −85 dB 1 kHz, 300 mV p-p signal at AVDD

ADAV4622
Rev. B | Page 8 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
SRC
Number of Channels 8 Two channels (SRC1), six channels (SRC2)
Dynamic Range
A-Weighted 115 dB −60 dBFS input (worst-case input fS= 50 kHz)
Total Harmonic Distortion + Noise −113 dB −3 dBFS input (worst-case input fS= 50 kHz)
Sample Rate 5 50 kHz
SRC DIGITAL INTERPOLATION FILTER
CHARACTERISTICS
At 48 kHz, guaranteed by design
Pass Band 21.678 kHz
Pass-Band Ripple 0.005 dB
Stop Band 26.232 kHz
Stop-Band Attenuation 110 dB
Group Delay 876 μs
DIGITAL INPUT/OUTPUT
Input Voltage High (VIH) 2.0 ODVDD V
Input Voltage Low (VIL) 0.8 V
Input Leakage
IIH (SDIN0, SDIN1, SDIN2, SDIN3, LRCLK0,
LRCLK1, LRCLK2, BCLK0, BCLK1, BCLK2,
SPDIF_OUT, SPDIF_IN)
40 μA VIH = ODVDD, equivalent to a 90 kΩ pull-up resistor
IIH (RESET) 13.5 μA VIH = ODVDD, equivalent to a 266 kΩ pull-up resistor
IIL (SDO0, SCL, SDA) −40 μA VIL = 0 V, equivalent to a 90 kΩ pull-down resistor
Output Voltage High (VOH) 2.4 V IOH = 0.4 mA
Output Voltage Low (VOL) 0.4 V IOL = −2 mA
Output Voltage High (VOH) (MCLK_OUT) 1.4 V IOH = 0.4 mA
Output Voltage Low (VOL) (MCLK_OUT) 0.4 V IOL = −3.2 mA
Input Capacitance 10 pF
SUPPLIES
Analog Supplies (AVDD) 3.0 3.3 3.6 V
Digital Supplies (DVDD) 1.65 1.8 2.0 V
Interface Supply (ODVDD) 3.0 3.3 3.6 V
Supply Currents MCLK = 24 MHz, ADCs and DACs active, headphone
outputs active and driving a 16 Ω load
Analog Current 260 mA
Digital Current 350 mA
Interface Current 2 mA
Power Dissipation 1.495 W
Standby Currents ADC, DAC, and headphone outputs floating, RESET low,
MCLK = 24 MHz
Analog Current 10 mA
Digital Current 4 mA
Interface Current 1.6 mA
TEMPERATURE RANGE
Operating Temperature −40 +85 °C
Storage Temperature −65 +150 °C

ADAV4622
Rev. B | Page 9 of 28
TIMING SPECIFICATIONS
Table 2.
Parameter Description Min Max Unit Comments
MASTER CLOCK AND RESET
fMCLKI MCLKI frequency 3.072 24.576 MHz
tMCH MCLKI high 10 ns
tMCL MCLKI low 10 ns
tRESET RESET low 200 ns
MASTER CLOCK OUTPUT
tJIT Period jitter 800 ps
tCH MCLK_OUT high 45 55 %
tCL MCLK_OUT low 45 55 %
I2C PORT
fSCL SCL clock frequency 400 kHz
tSCLH SCL high 600 ns
tSCLL SCL low 1.3 μs
Start Condition
tSCS Setup time 600 ns Relevant for repeated start condition
tSCH Hold time 600 ns After this period, the first clock is generated
tDS Data setup time 100 ns
tSCR SCL rise time 300 ns
tSCF SCL fall time 300 ns
tSDR SDA rise time 300 ns
tSDF SDA fall time 300 ns
Stop Condition
tSCS Setup time 0 ns
SERIAL PORTS
Slave Mode
tSBH BCLK high 40 ns
tSBL BCLK low 40 ns
fSBF BCLK frequency 64 × fS
tSLS LRCLK setup 10 ns To BCLK rising edge
tSLH LRCLK hold 10 ns From BCLK rising edge
tSDS SDIN setup 10 ns To BCLK rising edge
tSDH SDIN hold 10 ns From BCLK rising edge
tSDD SDO delay 50 ns From BCLK falling edge
Master Mode
tMLD LRCLK delay 25 ns From BCLK falling edge
tMDD SDO delay 15 ns From BCLK falling edge
tMDS SDIN setup 10 ns From BCLK rising edge
tMDH SDIN hold 10 ns From BCLK rising edge

ADAV4622
Rev. B | Page 10 of 28
TIMING DIAGRAMS
MCLKI
RESET
t
MP = 1/
f
MCLKI
t
RESET
07068-004
Figure 2. Master Clock and Reset Timing
07068-036
t
JIT
t
CH
t
CL
t
CK
DVDD
GND
Figure 3. Master Clock Output Timing
LRCLK1
BCLK1
SDINx
SDO0
tSLS
tSLH
tSDS tSDH
tSDD
07068-002
Figure 4. Serial Port Slave Mode Timing
LRCLK1
BCLK1
SDINx
SDO0
tMLD
tMDS tMDH
tMDD
07068-003
Figure 5. Serial Port Master Mode Timing
07068-033
ODVDD
100µA I
OL
100µA I
OH
TO OUTPUT
PIN
50pF
Figure 6. Load Circuit for Digital Output Timing Specifications