Analog Devices ADAV4622 User manual

Audio Processor for Advanced TV with
Sound IF Demodulator and Stereo Decoder
ADAV4622
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: [phone] www.analog.com
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FEATURES
Sound IF (SIF) processor
SIF demodulator and broadcast stereo decoder
NICAM (BG, DK, I, L), A2 (BG, DK, M), BTSC (M, N), EIAJ (M)
Automatic sound IF standard detection
Fully programmable 28-bit audio processor for enhanced
ATV sound—default TV audio flow loaded on reset
Implements Analog Devices and third-party branded audio
algorithms
Adjustable digital delay line for audio/video
Synchronization for up to 200 ms stereo delay
High performance 24-bit ADC and DAC
94 dB DNR performance on DAC channels
95 dB DNR performance on ADC channels
Dual headphone outputs with integrated amplifiers
High performance pulse-width modulation (PWM) digital
outputs
Multichannel digital baseband I/O
4 stereo synchronous digital I2S input channels
One 6-channel sample rate converter (SRC) and one
stereo SRC supporting input sample rates from
5 kHz to 50 kHz
One stereo synchronous digital I2S output
S/PDIF output with S/PDIF input mux capability
Fast I2C control
Operates from 3.3 V (analog), 1.8 V (digital core), and 3.3 V
(digital interface)
Available in 80-lead LQFP
APPLICATIONS
General-purpose consumer audio postprocessing
Home audio
DVD recorders
Home theater in a box (HTIB) systems and DVD receivers
Audio processing subsystems for DTV-ready TVs
Analog broadcast capability for iDTVs
PRODUCT OVERVIEW
The ADAV4622 is an enhanced audio processor targeting
advanced TV applications with full support for digital and
analog baseband audio as well as multistandard broadcast SIF
demodulation and decoding.
The audio processor, by default, loads a dedicated TV audio
flow that incorporates full matrix switching (any input to any
output), automatic volume control that compensates for volume
changes during advertisements or when switching channels,
dynamic bass, a multiband equalizer, and up to 200 ms of stereo
delay memory for audio-video synchronization.
Alternatively, Analog Devices, Inc., offers an award-winning
graphical programming tool (SigmaStudio™) that allows custom
flows to be quickly developed and evaluated. This allows the
creation of customer-specific audio flows, including use of the
Analog Devices library of third-party algorithms.
The analog I/O integrates Analog Devices proprietary
continuous-time, multibit Σ-Δ architecture to bring a higher
level of performance to ATV systems, required by third-party
algorithm providers to meet system branding certification. The
analog input is provided by 95 dB dynamic range (DNR) ADCs,
and analog output is provided by 94 dB DNR DACs.
The main speaker outputs can be supplied as a digitally
modulated PWM stream to support digital amplifiers.
The ADAV4622 includes multichannel digital inputs and
outputs. In addition, digital input channels can be routed
through integrated sample rate converters (SRC), which are
capable of supporting any arbitrary sample rate from 5 kHz
to 50 kHz.

ADAV4622
Rev. B | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Product Overview............................................................................. 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Performance Parameters ............................................................. 4
Timing Specifications .................................................................. 9
Timing Diagrams........................................................................ 10
Absolute Maximum Ratings.......................................................... 12
Thermal Resistance .................................................................... 12
Thermal Conditions................................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions........................... 13
Typical Performance Characteristics ........................................... 16
Terminology .................................................................................... 18
Pin Functions .................................................................................. 19
SDIN0, SDIN1, SDIN2, and SDIN3/SPDIF_IN0................... 19
LRCLK0, BCLK0, LRCLK1, BCLK1, LRCLK2, and BCLK2 19
SDO0/AD0 .................................................................................. 19
SPDIF_OUT (SDO1) ................................................................. 19
MCLKI/XIN................................................................................ 19
XOUT........................................................................................... 19
MCLK_OUT ............................................................................... 19
SDA............................................................................................... 19
SCL ............................................................................................... 20
MUTE .......................................................................................... 20
RESET .......................................................................................... 20
AUXIN1L, AUXIN2L, AUXIN1R, and AUXIN2R................ 20
AUXOUT1L, AUXOUT2L, AUXOUT3L, AUXOUT4L,
AUXOUT1R, AUXOUT2R, AUXOUT3R, and AUXOUT4R
....................................................................................................... 20
HPOUT1L, HPOUT2L, HPOUT1R, and HPOUT2R .......... 20
PLL_LF......................................................................................... 20
VREF............................................................................................ 20
FILTA and FILTD....................................................................... 20
PWM1A, PWM1B, PWM2A, PWM2B, PWM3A, PWM3B,
PWM4A, and PWM4B.............................................................. 20
PWM_READY ........................................................................... 20
AVDD .......................................................................................... 20
DVDD.......................................................................................... 20
ODVDD....................................................................................... 20
DGND.......................................................................................... 20
AGND.......................................................................................... 20
ODGND ...................................................................................... 20
SIF_REFP, SIF_REFCM, and SIF_REFN ................................ 20
SIF_IN1 and SIF_IN2 ................................................................ 20
SIF_PGA_REF ............................................................................ 20
ISET.............................................................................................. 20
Functional Descriptions ................................................................ 21
SIF Processor............................................................................... 21
Master Clock Oscillator............................................................. 21
I2C Interface ................................................................................ 22
ADC Inputs................................................................................. 22
I2S Digital Audio Inputs ............................................................ 22
DAC Voltage Outputs ................................................................ 23
PWM Outputs ............................................................................ 24
Headphone Outputs................................................................... 24
I2S Digital Audio Outputs ......................................................... 24
S/PDIF Input/Output................................................................. 25
Hardware Mute Control ............................................................ 25
Audio Processor ......................................................................... 25
Graphical Programming Environment ................................... 25
Application Layer ....................................................................... 25
Loading a Custom Audio Processing Flow............................. 26
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
7/09—Rev. A to Rev. B
Added Advantiv Logo ...................................................................... 1
Change to PWM Outputs Section................................................ 24
Change to Hardware Mute Control, Graphical Programming
Environment, and Application Layer Sections........................... 25
Changes to Ordering Guide .......................................................... 28
11/08—Revision A: Initial Version

ADAV4622
Rev. B | Page 3 of 28
FUNCTIONAL BLOCK DIAGRAM
AUDIO
PROCESSOR
ADAV4622
A-V
SYNCHRONOUS
DELAY
MEMORY
I
2
C INTERFACE
SIF PROCESSOR
AD0
SYNCHRONOUS
MULTICHANNEL
DIGITAL INPUTS
6-CHANNEL SRC
ASYNCHRONOUS
DIGITAL INPUT
2-CHANNEL SRC
ASYNCHRONOUS
DIGITAL INPUT
SYSTEM
CLOCKS
PLL
SPDIF_IN0
SPDIF_IN1
SPDIF_IN2
SPDIF_IN3
SPDIF_IN4
SPDIF_IN5
SPDIF_IN6
SPDIF_OUT/SDO1
S/PDIF I/O
PWM
DIGITAL
OUTPUT
PWM1A
PWM1B
PWM2A
PWM2B
PWM3A
PWM3B
PWM4A
PWM4B
PWM_READY
BCLK1
LRCLK1
SDO0/AD0
HPOUT2L
HPOUT2R
AUXOUT2L
AUXOUT2R DAC
HPOUT1L
AUXOUT4R
AUXOUT4L
HPOUT1R
DAC
AUXOUT1L
AUXOUT1R
DAC
AUXOUT3L
AUXOUT3R
DAC
SCL
SDA
BCLK2
LRCLK2
BCLK0
LRCLK0
SDIN0
SDIN1
SDIN2
SDIN3
XOUT
MCLKI/XIN
MCLK_OUT
SIF_IN1
SIF_IN2
AUXIN2L
AUXIN2R
ADC
AUXIN1L
AUXIN1R
ADC
DIGITAL
OUTPUTS
BCLK1
LRCLK1
MUTE
07068-001
Figure 1. ADAV4622 with PWM-Based Speaker Outputs

ADAV4622
Rev. B | Page 4 of 28
SPECIFICATIONS
AVDD = 3.3 V, DVDD = 1.8 V, ODVDD = 3.3 V, operating temperature = −40°C to +85°C, master clock = 24.576 MHz, measurement
bandwidth = 20 Hz to 20 kHz, ADC input signal = DAC output signal = 1 kHz, unless otherwise noted.
PERFORMANCE PARAMETERS
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
SIF ADC INPUT SECTION
Analog Input Frequency Range 10 MHz
Recommended Analog Input Level 90 ± 18 dB dBu FM, AGC in PGA priority mode
Maximum Analog Input Range 1.6 V p-p Default setting
Input Impedance 12 kΩ PGA Gain = 0 dB
6 KΩ PGA Gain = 10 dB
2.3 kΩ PGA Gain = 20 dB
DC Bias Level 1.9 V
SIF Input Isolation 60 dB SIF_IN1 to SIF_ IN2
FM Limiting Sensitivity 32 dBu A2 (DK), Mono, deviation mode = 100%, fFM = 400 Hz,
Δf = 50 kHz, BW = 20 Hz to 15 kHz, rms detector
31 dBu A2 (I), Mono, deviation mode = 100%, fFM = 400 Hz,
Δf = 50 kHz, BW = 20 Hz to 15 kHz, rms detector
31 dBu A2 (BG), Mono, deviation mode = 100%, fFM = 400 Hz,
Δf = 50 kHz, BW = 20 Hz to 15 kHz, rms detector
34 dBu BTSC (M, N), Mono, deviation mode = 100%,
fFM = 400 Hz, Δf = 25 kHz, BW = 20 Hz to 15 kHz,
rms detector
28.5 dBu A2 (M), Mono, deviation mode = 100%, fFM = 400 Hz,
Δf = 25 kHz, BW = 20 Hz to 15 kHz, rms detector
30 dBu EIAJ (M), Mono, deviation mode = 100%, fFM = 400 Hz,
Δf = 25 kHz, BW = 20 Hz to 15 kHz, rms detector
FM Output Level at 25% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 12.5 kHz, rms detector
53.6 % FS BTSC (M, N), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 6.25 kHz, rms detector
56.3 % FS A2 (M), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 6.25 kHz, rms detector
56.7 % FS EIAJ (M), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 6.25 kHz, rms detector
FM Output Level at 50% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 25 kHz, rms detector
53.6 % FS BTSC (M, N), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 12.5 kHz, rms detector
56.3 % FS A2 (M), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 12.5 kHz, rms detector
56.7 % FS EIAJ (M), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 12.5 kHz, rms detector
FM Output Level at 100% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 50 kHz, rms detector
53.6 % FS BTSC (M, N), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 25 kHz, rms detector
56.3 % FS A2 (M), Mono, VSIF = 100 mV, fFM = 400 Hz, Δf = 25 kHz,
rms detector
56.7 % FS EIAJ (M), Mono, VSIF = 100 mV, fFM = 400 Hz, Δf = 25 kHz,
rms detector
FM Output Level at 200% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, VSIF =100 mV, fFM = 400 Hz,
Δf = 100 kHz, rms detector
53.6 % FS BTSC (M, N), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 50 kHz, rms detector
56.3 % FS A2 (M), Mono, VSIF = 100 mV, fFM = 400 Hz, Δf = 50 kHz,
rms detector
56.7 % FS EIAJ (M), Mono, VSIF = 100 mV, fFM = 400 Hz, Δf = 50 kHz,
rms detector

ADAV4622
Rev. B | Page 5 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
FM Output Level at 400% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 200 kHz, rms detector
53.6 % FS BTSC (M, N), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 100 kHz, rms detector
56.4 % FS A2 (M), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 100 kHz, rms detector
56.7 % FS EIAJ (M), Mono, VSIF = 100 mV, fFM = 400 Hz, Δf = 100 kHz,
rms detector
FM Output Level at 800% Deviation Mode 53.7 % FS A2 (DK, I, BG), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 400 kHz, rms detector
53.6 % FS BTSC (M, N), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 200 kHz, rms detector
56.3 % FS A2 (M), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 200 kHz, rms detector
56.7 % FS EIAJ (M), Mono, VSIF = 100 mV, fFM = 400 Hz,
Δf = 200 kHz, rms detector
AM Rejection Ratio 69.5 dB A2 (DK), Mono, deviation mode = 100%, VSIF = 100 mV,
fFM = 400 Hz, Δf = 27 kHz, fAM = 400 Hz, MODAM = 30%,
BW = 20 Hz to 15 kHz, rms detector
70 dB A2 (I), Mono, deviation mode = 100%, VSIF = 100 mV,
fFM = 400 Hz, Δf = 27 kHz, fAM = 400 Hz, MODAM = 30%,
BW = 20 Hz to 15 kHz, rms detector
70 dB A2 (BG), Mono, deviation mode = 100%, VSIF = 100 mV,
fFM = 400 Hz, Δf = 27 kHz, fAM = 400 Hz, MODAM = 30%,
BW = 20 Hz to 15 kHz, rms detector
70.5 dB Mono (M), deviation mode = 100%, VSIF = 100 mV,
fFM = 400 Hz, Δf = 13.5 kHz, fAM = 400 Hz, MODAM = 30%,
BW = 20 Hz to 15 kHz, rms detector
AM Sensitivity 40 dBu Mono (L), fAM = 400 Hz, MOD = 30%, BW = 20 Hz to 15 kHz,
rms detector, (S + N)/N = 10 dB
BTSC (M) PERFORMANCE Measured at analog audio output, video = 75% color bar,
fSC = 4.5 MHz, fFM = 1 kHz, Δf = 25 kHz (100%), deemphasis =
75 μs, measuring BW = 20 Hz to 15 kHz with dBX NR
Dynamic Range
Stereo Channel 62 dB Stereo L or R (L = −R), 100%, 1 kHz
SAP Channel 68 dB SAP channel with Mono 100%, 1 kHz
Total Harmonic Distortion + Noise
Stereo Channel −46 dB Stereo L or R (L = −R), 100%, 1 kHz
SAP Channel −40 dB SAP 100%, 1 kHz
Frequency Response fFM = 20 Hz to 12 kHz
Stereo Channel +0.1/−0.7 dB Stereo L or R, 50%, (L = −R)
SAP Channel +2.5/−2.5 dB SAP 50%, Mono 100%, 1 kHz
Crosstalk
Stereo-to-SAP Channel −74 dB L or R 50%, 1 kHz
SAP-to-Stereo Channel −71 dB SAP 50%, 1 kHz
Stereo Separation dBX 30 dB L off, R 50%, 1 kHz
EIAJ (M) PERFORMANCE Measured at analog audio output, video = 75% color bar,
fSC = 4.5 MHz, fFM = 1 kHz, Δf = 25 kHz (100%),
deemphasis = 75 μs, measuring BW = 20 Hz to 15 kHz
Dynamic Range
Stereo Channel 58 dB Stereo L or R, 100%, 1 kHz
Dual Channel 56 dB Dual channel with Mono 100%, 1 kHz
Total Harmonic Distortion + Noise
Stereo Channel −56 dB Stereo L or R, 100%, 1 kHz
Dual Channel −47 dB Dual 50%, 1 kHz
Frequency Response fFM = 20 Hz to 10 kHz
Stereo Channel +0.03/−0.53 dB Stereo L or R, 100%
Dual Channel +0.17/−1.4 dB Dual 100%, Mono 100%, 1 kHz
Crosstalk
Main-to-Dual Channel −75 dB Main 100%, 1 kHz
Dual-to-Main Channel −83 dB Dual 100%, 1 kHz
Stereo Separation 39 dB Stereo L or R, 100%, 1 kHz

ADAV4622
Rev. B | Page 6 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
A2 (M) PERFORMANCE Measured at analog audio output, video = 75% color bar,
fSC1 = 4.5 MHz, fSC2 = 4.724 MHz, fFM = 1 kHz, Δf = 25 kHz
(100%), deemphasis = 75 μs, measuring BW = 20 Hz to
15 kHz
Dynamic Range 60 dB Mono 100%, 1 kHz
Total Harmonic Distortion + Noise −64 dB Mono 100%, 1 kHz
Frequency Response +0.4/−0.05 dB Mono 100%, fFM = 25 Hz to 15 kHz
Crosstalk (Dual) −88 dB Mono or dual off, 100%, 1 kHz
Channel Separation (Stereo) 66 dB Stereo L off, R 50%, 1 kHz
A2 (DK1/DK2/DK3) PERFORMANCE Measured at analog audio output, video = 75% color bar,
fSC1 = 6.5 MHz, fSC2 = 6.742 MHz, (DK2 worst case),
fFM = 1 kHz, Δf = 50 kHz (100%), deemphasis = 50 μs,
measuring BW = 20 Hz to 15 kHz
Dynamic Range 74 dB Mono 100%, 1 kHz
Total Harmonic Distortion + Noise −66 dB Mono 100%, 1 kHz
Frequency Response +0.1/−0.3 dB Mono 100%, fFM = 20 Hz to 15 kHz
Crosstalk (Dual) −88 dB Mono or dual off, 100%, 1 kHz
Channel Separation (Stereo) 77 dB Stereo L off, R 50%, 1 kHz
A2 (BG) PERFORMANCE Measured at analog audio output, video = 75% color bar,
fSC1 = 5.5 MHz, fSC2 = 5.742 MHz, fFM = 1 kHz,
Δf = 50 kHz (100%), deemphasis = 50 μs,
measuring BW = 20 Hz to 15 kHz
Dynamic Range 74 dB Mono 100%, 1 kHz
Total Harmonic Distortion + Noise −61 dB Mono 100%, 1 kHz
Frequency Response +0.1/−0.3 dB Mono 100%, fFM = 25 Hz to 15 kHz
Crosstalk (Dual) −89 dB Mono or dual off, 100%, 1 kHz
Channel Separation (Stereo) 70 dB Stereo L off, R 50%, 1 kHz
NICAM (I) PERFORMANCE Measured at analog audio output, video = 75% color bar,
1 kHz, unweighted, deemphasis = J17, measuring BW = 20
Hz to 15 kHz
Dynamic Range 72 dB Stereo L or R, 0 dB, 1 kHz
Total Harmonic Distortion + Noise −63 dB Stereo L or R, 0 dB, 1 kHz
Frequency Response −1.3/+0.07 dB Stereo L or R, 0 dB
Crosstalk −80 dB Mono or dual, 0 dB, 1 kHz
Stereo Separation 73 dB L or R, 0 dB, 1 kHz
Bit Error Rate 0 FM and NICAM nominal conditions
NICAM (BG, DK, L) PERFORMANCE Measured at analog audio output, video = 75% color bar,
1 kHz, unweighted, deemphasis = J17, measuring BW =
20 Hz to 15 kHz
Dynamic Range 72 dB Stereo L or R, 0 dB, 1 kHz
Total Harmonic Distortion + Noise −63 dB Stereo L or R, 0 dB, 1 kHz
Frequency Response −1.3/+0.07 dB Stereo L or R, 0 dB
Crosstalk −80 dB Mono or dual, 0 dB, 1 kHz
Stereo Separation 74 dB L or R, 0 dB, 1 kHz
Bit Error Rate 0 FM and NICAM nominal conditions
AM PERFORMANCE Measured at analog audio output, 1 kHz,
AM carrier 6.5 MHz measuring BW = 20 Hz to 15 kHz
Dynamic Range
RMS/FLAT 55 dB AM = 54% modulation
QP/CCIR 35 dB CCIR filter, AM = 54% modulation
Total Harmonic Distortion + Noise −49 dB AM = 54% modulation
Frequency Response +0.03/−1.2 dB AM = 54% modulation
REFERENCE SECTION
Absolute Voltage VREF 1.53 V
VREF Temperature Coefficient 100 ppm/°C

ADAV4622
Rev. B | Page 7 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
ADC SECTION
Number of Channels 4 Two stereo channels
Full-Scale Input Level 100 μA rms
Resolution 24 Bits
Dynamic Range (Stereo Channel)
A-Weighted 95 dB −60 dBFS with respect to full-scale analog input
Total Harmonic Distortion + Noise (Stereo
Channel)
−90 dB −3 dBFS with respect to full-scale analog input
Gain Mismatch 0.2 dB Left- and right-channel gain mismatch
Crosstalk (Left to Right, Right to Left) −110 dB
Gain Error −1 dB Input signal is 100 μA rms
Current Setting Resistor (RISET) 20 kΩ External resistor to set current input range of ADC for
nominal 2.0 V rms input signal
Power Supply Rejection −87 dB 1 kHz, 300 mV p-p signal at AVDD
ADC DIGITAL DECIMATOR FILTER
CHARACTERISTICS
At 48 kHz, guaranteed by design
Pass Band 22.5 kHz
Pass-Band Ripple ±0.0002 dB
Stop Band 26.5 kHz
Stop-Band Attenuation 100 dB
Group Delay 1040 μs
PWM SECTION
Frequency 384 kHz Guaranteed by design
Modulation Index 0.976 Guaranteed by design
Dynamic Range
A-Weighted 98 dB −60 dB with respect to full-scale code input
Total Harmonic Distortion + Noise −78 dB −3 dB with respect to full-scale code input
DAC SECTION
Number of Auxiliary Output Channels 8 Four stereo channels
Resolution 24 Bits
Full-Scale Analog Output 1 V rms
Dynamic Range
A-Weighted 94 dB −60 dBFS with respect to full-scale code input
Total Harmonic Distortion + Noise −86 dB −3 dBFS with respect to full-scale code input
Crosstalk (Left to Right, Right to Left) −102 dB
Interchannel Gain Mismatch 0.1 dB Left- and right-channel gain mismatch
Gain Error 0.525 dB 1 V rms output
DC Bias 1.53 V
Power Supply Rejection −90 dB 1 kHz, 300 mV p-p signal at AVDD
Output Impedance 235 Ω
DAC DIGITAL INTERPOLATION FILTER
CHARACTERISTICS
At 48 kHz, guaranteed by design
Pass Band 21.769 kHz
Pass-Band Ripple ±0.01 dB
Transition Band 23.95 kHz
Stop Band 26.122 kHz
Stop-Band Attenuation 75 dB
Group Delay 580 μs
HEADPHONE AMPLIFIER Measured at headphone output with 32 Ω load
Number of Channels 4 Two stereo channels
Full-Scale Output Power 31 mW rms 1 V rms output
Dynamic Range
A-Weighted 93 dB −60 dBFS with respect to full-scale code input
Total Harmonic Distortion + Noise −83 dB −3 dBFS with respect to full-scale code input
Interchannel Gain Mismatch 0.1 dB
DC Bias 1.53 V
Power Supply Rejection −85 dB 1 kHz, 300 mV p-p signal at AVDD

ADAV4622
Rev. B | Page 8 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
SRC
Number of Channels 8 Two channels (SRC1), six channels (SRC2)
Dynamic Range
A-Weighted 115 dB −60 dBFS input (worst-case input fS= 50 kHz)
Total Harmonic Distortion + Noise −113 dB −3 dBFS input (worst-case input fS= 50 kHz)
Sample Rate 5 50 kHz
SRC DIGITAL INTERPOLATION FILTER
CHARACTERISTICS
At 48 kHz, guaranteed by design
Pass Band 21.678 kHz
Pass-Band Ripple 0.005 dB
Stop Band 26.232 kHz
Stop-Band Attenuation 110 dB
Group Delay 876 μs
DIGITAL INPUT/OUTPUT
Input Voltage High (VIH) 2.0 ODVDD V
Input Voltage Low (VIL) 0.8 V
Input Leakage
IIH (SDIN0, SDIN1, SDIN2, SDIN3, LRCLK0,
LRCLK1, LRCLK2, BCLK0, BCLK1, BCLK2,
SPDIF_OUT, SPDIF_IN)
40 μA VIH = ODVDD, equivalent to a 90 kΩ pull-up resistor
IIH (RESET) 13.5 μA VIH = ODVDD, equivalent to a 266 kΩ pull-up resistor
IIL (SDO0, SCL, SDA) −40 μA VIL = 0 V, equivalent to a 90 kΩ pull-down resistor
Output Voltage High (VOH) 2.4 V IOH = 0.4 mA
Output Voltage Low (VOL) 0.4 V IOL = −2 mA
Output Voltage High (VOH) (MCLK_OUT) 1.4 V IOH = 0.4 mA
Output Voltage Low (VOL) (MCLK_OUT) 0.4 V IOL = −3.2 mA
Input Capacitance 10 pF
SUPPLIES
Analog Supplies (AVDD) 3.0 3.3 3.6 V
Digital Supplies (DVDD) 1.65 1.8 2.0 V
Interface Supply (ODVDD) 3.0 3.3 3.6 V
Supply Currents MCLK = 24 MHz, ADCs and DACs active, headphone
outputs active and driving a 16 Ω load
Analog Current 260 mA
Digital Current 350 mA
Interface Current 2 mA
Power Dissipation 1.495 W
Standby Currents ADC, DAC, and headphone outputs floating, RESET low,
MCLK = 24 MHz
Analog Current 10 mA
Digital Current 4 mA
Interface Current 1.6 mA
TEMPERATURE RANGE
Operating Temperature −40 +85 °C
Storage Temperature −65 +150 °C

ADAV4622
Rev. B | Page 9 of 28
TIMING SPECIFICATIONS
Table 2.
Parameter Description Min Max Unit Comments
MASTER CLOCK AND RESET
fMCLKI MCLKI frequency 3.072 24.576 MHz
tMCH MCLKI high 10 ns
tMCL MCLKI low 10 ns
tRESET RESET low 200 ns
MASTER CLOCK OUTPUT
tJIT Period jitter 800 ps
tCH MCLK_OUT high 45 55 %
tCL MCLK_OUT low 45 55 %
I2C PORT
fSCL SCL clock frequency 400 kHz
tSCLH SCL high 600 ns
tSCLL SCL low 1.3 μs
Start Condition
tSCS Setup time 600 ns Relevant for repeated start condition
tSCH Hold time 600 ns After this period, the first clock is generated
tDS Data setup time 100 ns
tSCR SCL rise time 300 ns
tSCF SCL fall time 300 ns
tSDR SDA rise time 300 ns
tSDF SDA fall time 300 ns
Stop Condition
tSCS Setup time 0 ns
SERIAL PORTS
Slave Mode
tSBH BCLK high 40 ns
tSBL BCLK low 40 ns
fSBF BCLK frequency 64 × fS
tSLS LRCLK setup 10 ns To BCLK rising edge
tSLH LRCLK hold 10 ns From BCLK rising edge
tSDS SDIN setup 10 ns To BCLK rising edge
tSDH SDIN hold 10 ns From BCLK rising edge
tSDD SDO delay 50 ns From BCLK falling edge
Master Mode
tMLD LRCLK delay 25 ns From BCLK falling edge
tMDD SDO delay 15 ns From BCLK falling edge
tMDS SDIN setup 10 ns From BCLK rising edge
tMDH SDIN hold 10 ns From BCLK rising edge

ADAV4622
Rev. B | Page 10 of 28
TIMING DIAGRAMS
MCLKI
RESET
t
MP = 1/
f
MCLKI
t
RESET
07068-004
Figure 2. Master Clock and Reset Timing
07068-036
t
JIT
t
CH
t
CL
t
CK
DVDD
GND
Figure 3. Master Clock Output Timing
LRCLK1
BCLK1
SDINx
SDO0
tSLS
tSLH
tSDS tSDH
tSDD
07068-002
Figure 4. Serial Port Slave Mode Timing
LRCLK1
BCLK1
SDINx
SDO0
tMLD
tMDS tMDH
tMDD
07068-003
Figure 5. Serial Port Master Mode Timing
07068-033
ODVDD
100µA I
OL
100µA I
OH
TO OUTPUT
PIN
50pF
Figure 6. Load Circuit for Digital Output Timing Specifications

ADAV4622
Rev. B | Page 11 of 28
07068-034
DVDD
1.8V
0V
3.3V
0V
AVDD
ODVDD
1.0s MAX
1.0s MAX
1.65V
3.0V
0.33V
0.18V
Figure 7. Power-Up Sequence Timing
07068-035
DVDD
1.8V
0V
3.3V
0V
AVDD
ODVDD
1.0s MAX
1.0s MAX
1.65V
3.0V
0.33V
0.18V
Figure 8. Power-Down Sequence Timing

ADAV4622
Rev. B | Page 12 of 28
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
DVDD to DGND 0 V to 2.2 V
ODVDD to DGND 0 V to 4 V
AVDD to AGND 0 V to 4 V
AGND to DGND −0.3 V to +0.3 V
Digital Inputs DGND − 0.3 V to ODVDD + 0.3 V
Analog Inputs AGND − 0.3 V to AVDD + 0.3 V
Reference Voltage Indefinite short circuit to ground
Soldering (10 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance1
Package Type θJA θ
JC Unit
80-Lead LQFP 38.1 7.6 °C/W
1 Based on JEDEC 2S2P PCB.
THERMAL CONDITIONS
To ensure correct operation of the device, the case temperature
(TCASE) must be kept below 121°C to keep the junction tempera-
ture (TJ) below the maximum allowed, 125°C.
ESD CAUTION

ADAV4622
Rev. B | Page 13 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VREF
AGND
AVDD
SIF_REFN
SIF_REFCM
SIF_REFP
FILTA
SIF_IN1
SIF_PGA_REF
SIF_IN2
AVDD
DGND
DVDD
MUTE
SDA
SCL
SPDIF_IN5/LRCLK2
SPDIF_IN6/BCLK2
DGND
2
3
4
7
6
5
1
8
9
10
12
13
14
15
16
17
18
19
20
11
AGND
AVDD
HPOUT1R
HPOUT1L
PLL_LF
AGND
AGND
HPOUT2L
AVDD
DGND
DVDD
PWM4B
PWM4A
PWM3B
PWM3A
PWM2B
PWM2A
PWM1B
PWM1A
DGND
59
58
57
54
55
56
60
53
52
51
49
48
47
46
45
44
43
42
41
50
RESET
21
DVDD
22
SDIN0
23
SDIN1
24
SDIN2
25
SPDIF_IN0/SDIN3
26
SPDIF_IN1/LRCLK0
27
SPDIF_IN2/BCLK0
28
ODGND
29
ODVDD
30
MCLK_OUT
31
DVDD
32
DGND
33
MCLKI/XIN
34
XOUT
35
SPDIF_IN4/BCLK1
36
SPDIF_IN3/LRCLK1
37
SDO0/AD0
38
SPDIF_OUT/SDO1
39
PWM_READY
40
DVDD
ISET AUXIN1R AUXIN1L AUXIN2R AUXIN2L AUXOUT2R AUXOUT2L AUXOUT1R AUXOUT1L AVDD AGND AGND AVDD FILTD NC AUXOUT4R AUXOUT4L AUXOUT3R AUXOUT3L HPOUT2R
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PIN 1
ADAV4622
TOP VIEW
(Not to Scale)
07068-006
NC = NO CONNECT
Figure 9. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 FILTA ADC Filter Capacitor.
2 VREF Reference Capacitor.
3 AGND ADC Ground.
4 AVDD ADC Supply (3.3 V).
5 SIF_REFP SIF ADC Positive Reference (Typical 1.4 V).
6 SIF_REFCM SIF ADC Common-Mode Reference (Typical 1 V).
7 SIF_REFN SIF ADC Negative Reference (Typical 0.6 V).
8 SIF_IN1 SIF Input 1.
9 SIF_PGA_REF SIF PGA Reference.
10 SIF_IN2 SIF Input 2.
11 AGND SIF AGND.
12 AVDD SIF Supply (3.3 V).
13 DGND Digital Ground.
14 DVDD Digital Supply (1.8 V).
15 MUTE Active Low Mute Request Input Signal.

ADAV4622
Rev. B | Page 14 of 28
Pin No. Mnemonic Description
16 SDA I2C Data.
17 SCL I2C Clock.
18 SPDIF_IN5/LRCLK2 External Input to S/PDIF Mux/Left/Right Clock for SRC2 (Default).
19 SPDIF_IN6/BCLK2 External Input to S/PDIF Mux/Bit Clock for SRC2 (Default).
20 DGND Digital Ground.
21 DVDD Digital Supply (1.8 V).
22 SDIN0 Serial Data Input 0/SRC Data Input.
23 SDIN1 Serial Data Input 1/SRC Data Input.
24 SDIN2 Serial Data Input 2/SRC Data Input.
25 SPDIF_IN0/SDIN3 External Input to S/PDIF Mux/SRC Data Input/Serial Data Input 3 (Default).
26 SPDIF_IN1/LRCLK0 External Input to S/PDIF Mux/Left/Right Clock for SRC1 (Default).
27 SPDIF_IN2/BCLK0 External Input to S/PDIF Mux/Bit Clock for SRC1 (Default).
28 ODGND Digital Ground.
29 ODVDD Digital Interface Supply (3.3 V).
30 MCLK_OUT Master Clock Output.
31 DVDD Digital Supply (1.8 V).
32 DGND Digital Ground.
33 MCLKI/XIN Master Clock/Crystal Input.
34 XOUT Crystal Output.
35 SPDIF_IN4/BCLK1 External Input to S/PDIF Mux/Bit Clock for Serial Data I/O (Default).
36 SPDIF_IN3/LRCLK1 External Input to S/PDIF Mux/Left/Right Clock for Serial Data I/O (Default).
37 SDO0/AD0 Serial Data Output. This pin acts as the I2C address select on reset. It has an internal pull-down
resistor.
38 SPDIF_OUT/SDO1 Output of S/PDIF Mux/Serial Data Output.
39 PWM_READY PWM Ready Flag.
40 DVDD Digital Supply (1.8 V).
41 DGND Digital Ground.
42 PWM1A Pulse-Width Modulated Output 1A.
43 PWM1B Pulse-Width Modulated Output 1B.
44 PWM2A Pulse-Width Modulated Output 2A.
45 PWM2B Pulse-Width Modulated Output 2B.
46 PWM3A Pulse-Width Modulated Output 3A.
47 PWM3B Pulse-Width Modulated Output 3B.
48 PWM4A Pulse-Width Modulated Output 4A.
49 PWM4B Pulse-Width Modulated Output 4B.
50 RESET Reset Analog and Digital Cores.
51 DVDD Digital Supply (1.8 V).
52 DGND Digital Ground.
53 AVDD PLL Supply (3.3 V).
54 PLL_LF PLL Loop Filter.
55 AGND PLL Ground.
56 AGND Headphone Driver Ground.
57 HPOUT1L Left Headphone Output 1.
58 HPOUT1R Right Headphone Output 1.
59 AVDD Headphone Driver Supply (3.3 V).
60 HPOUT2L Left Headphone Output 2.
61 HPOUT2R Right Headphone Output 2.
62 AUXOUT3L Left Auxiliary Output 3.
63 AUXOUT3R Right Auxiliary Output 3.
64 AUXOUT4L Left Auxiliary Output 4.
65 AUXOUT4R Right Auxiliary Output 4.
66 NC No Connection to this Pin Allowed.
67 FILTD DAC Filter Capacitor.

ADAV4622
Rev. B | Page 15 of 28
Pin No. Mnemonic Description
68 AVDD DAC Supply (3.3 V).
69 AGND DAC Ground.
70 AGND DAC Ground.
71 AVDD DAC Supply (3.3 V).
72 AUXOUT1L Left Auxiliary Output 1.
73 AUXOUT1R Right Auxiliary Output 1.
74 AUXOUT2L Left Auxiliary Output 2.
75 AUXOUT2R Right Auxiliary Output 2.
76 AUXIN2L Left Auxiliary Input 2.
77 AUXIN2R Right Auxiliary Input 2.
78 AUXIN1L Left Auxiliary Input 1.
79 AUXIN1R Right Auxiliary Input 1.
80 ISET ADC Current Setting.

ADAV4622
Rev. B | Page 16 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
0
–180
–160
07
MAGNITUDE (dB)
FREQUENCY (kHz)
192 384 576
–140
–120
–100
–80
–60
–40
–20
68
07068-007
Figure 10. DAC Composite Filter Response (48 kHz)
0
–160
09
MAGNITUDE (dB)
FREQUENCY (kHz)
24 48 72
–140
–120
–100
–80
–60
–40
–20
6
07068-008
Figure 11. DAC Band-Pass Filter Response (48 kHz)
0.6
–0.6
–0.4
–0.2
0
0.2
0.4
02
MAGNITUDE (dB)
FREQUENCY (kHz)
816 4
07068-009
Figure 12. DAC Pass-Band Ripple (48 kHz)
0
–30
–60
–90
–120
–150
–180
–210
–240
–270
–300
03
MAGNITUDE (dB)
FREQUENCY (kHz)
128 256 84
07068-010
Figure 13. ADC Composite Filter Response (48 kHz)
0
–180
–150
–120
–90
–60
–30
09
MAGNITUDE (dB)
FREQUENCY (kHz)
24 48 72 6
07068-011
Figure 14. ADC Band-Pass Filter Response (48 kHz)
0.04
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0.03
02
MAGNITUDE (dB)
FREQUENCY (kHz)
816 4
07068-012
Figure 15. ADC Pass-Band Ripple (48 kHz)

ADAV4622
Rev. B | Page 17 of 28
0
–160
0 20000
MAGNITUDE (dBV)
FREQUENCY (Hz)
4000 8000 12000 16000
–140
–120
–100
–80
–60
–40
–20
07068-013
Figure 16. DAC Dynamic Range
0
–160
020000
MAGNITUDE (dBV)
FREQUENCY (Hz)
4000 8000 12000 16000
–140
–120
–100
–80
–60
–40
–20
07068-014
Figure 17. DAC Total Harmonic Distortion + Noise
0
–160
MAGNITUDE (dBV)
–140
–120
–100
–80
–60
–40
–20
07068-015
0 20000
FREQUENCY (Hz)
4000 8000 12000 16000
Figure 18. ADC Dynamic Range
0
–160
MAGNITUDE (dBV)
–140
–120
–100
–80
–60
–40
–20
07068-016
0 20000
FREQUENCY (Hz)
4000 8000 12000 16000
Figure 19. ADC Total Harmonic Distortion + Noise
0
–140
–120
–100
–80
–60
–40
–20
010.90.80.70.60.50.40.30.20.1
GAIN (dB)
NORMALIZED FREQUENCY
.0
07068-017
Figure 20. Sample Rate Converter Transfer Function

ADAV4622
Rev. B | Page 18 of 28
TERMINOLOGY
Dynamic Range
The ratio of a full-scale input signal to the integrated input
noise in the pass band (20 Hz to 20 kHz), expressed in decibels
(dB). Dynamic range is measured with a −60 dB input signal
and is equal to (S/[THD+N]) + 60 dB. Note that spurious
harmonics are below the noise with a −60 dB input, so the noise
level establishes the dynamic range. The dynamic range is
specified with and without an A-weight filter applied.
Pass Band
The region of the frequency spectrum unaffected by the
attenuation of the digital decimator’s filter.
Pass-Band Ripple
The peak-to-peak variation in amplitude response from equal
amplitude input signal frequencies within the pass band,
expressed in decibels.
Stop Band
The region of the frequency spectrum attenuated by the digital
decimator’s filter to the degree specified by stop-band
attenuation.
Gain Error
With a near full-scale input, the ratio of the actual output to the
expected output, expressed in dB.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of the outputs of
the two stereo channels, expressed in decibels.
Crosstalk
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine wave input on the other channel, expressed
in decibels.
Power Supply Rejection
With no analog input, the signal present at the output when a
300 mV p-p signal is applied to power supply pins, expressed
in decibels of full scale.
Group Delay
Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in milliseconds (ms).
More precisely, the derivative of radian phase with respect to
radian frequency at a given frequency.
SIF Input Isolation
The level of the crosstalk between the SIF inputs in dB.
FM Limiting Sensitivity
FM limiting sensitivity is given by the modulated carrier level
that gives half the power to the FM demodulator’s output
amplitude comparing to that when the carrier level satisfies
the demodulator’s limiting level.
Deviation Mode
In some regions, the transmitted signal can deviate from the
specification. In order for the ADAV4622 to decode these high
deviation signals correctly, the appropriate modulation level
must be selected.
AM Rejection Ratio
AM rejection ratio is given by the ratio of FM (deviation = 54%)
demodulated audio level vs. residual AM (modulation = 27%)
demodulated audio level at the same carrier level. It is the ability
of the receiver to not mistake an AM signal for an FM signal.
AM Sensitivity
AM sensitivity is a measure of how well the receiver picks up
very weak AM signals.

ADAV4622
Rev. B | Page 19 of 28
PIN FUNCTIONS
Tabl e 5 shows the pin numbers, mnemonics, and descriptions
for the ADAV4622. The input pins have a logic threshold
compatible with 3.3 V input levels.
SDIN0, SDIN1, SDIN2, AND SDIN3/SPDIF_IN0
Serial data inputs. These input pins provide the digital audio
data to the signal processing core. Any of the inputs can be
routed to either of the SRCs for conversion; this input is then
not available as a synchronous input to the audio processor but
only as an input through the selected SRC. The serial format
for the synchronous data is selected by Bits [3:2] of the serial
port control register. If the SRCs are required, the serial format
is selected by Bits [12:9] of the same register. The synchronous
inputs are capable of using any pair of serial clocks LRCLK0/
BCLK0, LRCLK1/BCLK1, or LRCLK2/BCLK2. By default,
they use LRCLK1 and BCLK1. See Figure 24 for more details
regarding the configuration of the synchronous inputs.
SDIN3 is a shared pin with SPDIF_IN0. If SDIN3 is not in use,
this pin can be used to connect an S/PDIF signal from an
external source, such as an MPEG decoder, to the ADAV4622
on-chip S/PDIF output multiplexer. If SPDIF_OUT is selected
from one of the SPDIF_IN (external) signals, the signal is
simply passed through from input to output.
LRCLK0, BCLK0, LRCLK1, BCLK1, LRCLK2, AND
BCLK2
By default, LRCLK1 and BCLK1 are associated with the
synchronous inputs, LRCLK0 and BCLK0 are associated with
SRC1, and LRCLK2 and BCLK2 are associated with SRC2.
However, the SRCs and synchronous inputs can use any of the
serial clocks (see Figure 24 for more details). LRCLK0, BCLK0,
LRCLK1, BCLK1, LRCLK2, and BCLK2 are shared pins with
SPDIF_IN1, SPDIF_IN2, SPDIF_IN3, SPDIF_IN4, SPDIF_IN5,
and SPDIF_IN6, respectively. If LRCLK0/LRCLK1/LRCLK2 or
BCLK0/BCLK1/BCLK2 are not in use, these pins can be used to
connect an S/PDIF signal from an external source, such as an
MPEG decoder, to the ADAV4622 on-chip S/PDIF output
multiplexer. If SPDIF_OUT is selected from one of the
SPDIF_IN (external) signals, the signal is simply passed
through from input to output.
SDO0/AD0
Serial data output. This pin can output two channels of digital
audio using a variety of standard 2-channel formats. The clocks
for SDO0 are always the same as those used by the synchronous
inputs; this means that LRCLK1 and BCLK1 are used by default,
although SDO0 is capable of using any pair of serial clocks,
LRCLK0/BCLK0, LRCLK1/BCLK1, or LRCLK2/BCLK2.
The serial port control register selects the serial format for the
synchronous output. On reset, the SDO0 pin duplicates as the
I2C® address select pin. In this mode, the logical state of the pin
is polled for four MCLKI cycles following reset. The address
select bit is set as the majority poll of the pin’s logic level after
the four MCLKI cycles.
SPDIF_OUT (SDO1)
The ADAV4622 contains an S/PDIF multiplexer functionality
that allows the SPDIF_OUT signal to be chosen from an
internally generated S/PDIF signal or from the S/PDIF signal
from an external source, which is connected via one of the
SPDIF_IN pins. This pin can also be configured as an
additional serial data output (SDO1) as an alternate function.
MCLKI/XIN
Master clock input. The ADAV4622 uses a PLL to generate the
appropriate internal clock for the audio processing core. A clock
signal of a suitable frequency can be connected directly to this
pin, or a crystal can be connected between MCLKI/XIN and
XOUT together with the appropriate capacitors to DGND to
generate a suitable clock signal.
XOUT
This pin is used in conjunction with MCLKI/XIN to generate a
clock signal for the ADAV4622.
MCLK_OUT
This pin can be used to output MCLKI or one of the internal
system clocks. It should be noted that the output level of this
pin is referenced to DVDD (1.8 V) and not ODVDD (3.3 V)
like all other digital inputs and outputs.
SDA
Serial data input for the I2C control port. SDA features a glitch
elimination filter that removes spurious pulses that are less than
50 ns wide.

ADAV4622
Rev. B | Page 20 of 28
SCL
Serial clock for the I2C control port. SCL features a glitch
elimination filter that removes spurious pulses that are less
than 50 ns wide.
MUTE
Mute input request. This active-low input pin controls the
muting of the output ports (both analog and digital) from the
ADAV4622. When low, it asserts mute on the outputs that are
enabled in the audio flow.
RESET
Active-low reset signal. After RESET goes high, all the circuit
blocks are powered down. The blocks can be individually
powered up with software. When the part is powered up, it
takes approximately 3072 internal clocks to initialize the
internal circuitry. The internal system clock is equal to MCLKI
until the PLL is powered and enabled, after which the internal
system clock becomes 2560 × fS(122.88 MHz). Once the PLL
is powered up and enabled after reset, it takes approximately
3 ms to lock. When the audio processor is enabled, it takes
approximately 32,768 internal system clocks to initialize and
load the default flow to the audio processor memory. The audio
processor is not available during this time.
AUXIN1L, AUXIN2L, AUXIN1R, AND AUXIN2R
Analog inputs to the on-chip ADCs.
AUXOUT1L, AUXOUT2L, AUXOUT3L, AUXOUT4L,
AUXOUT1R, AUXOUT2R, AUXOUT3R, AND
AUXOUT4R
Auxiliary DAC analog outputs. These pins can be programmed
to supply the outputs of the internal audio processing for line
out or record use.
HPOUT1L, HPOUT2L, HPOUT1R, AND HPOUT2R
Analog outputs from the headphone amplifiers.
PLL_LF
PLL loop filter connection. A 100 nF capacitor and a 2 kΩ
resistor in parallel with a 1 nF capacitor tied to AVDD are
required for the PLL loop filter to operate correctly.
VREF
Voltage reference for DACs and ADCs. This pin is driven by an
internal 1.5 V reference voltage.
FILTA AND FILTD
Decoupling nodes for the ADC and DAC. Decoupling
capacitors should be connected between these nodes and
AGND, typically 47 μF/0.1 μF and 10 μF/0.1 μF, respectively.
PWM1A, PWM1B, PWM2A, PWM2B, PWM3A,
PWM3B, PWM4A, AND PWM4B
Differential pulse-width modulation outputs are suitable for
driving Class-D amplifiers.
PWM_READY
This pin is set high when PWM is enabled and stable.
AVDD
Analog power supply pins. These pins should be connected to
3.3 V. Each pin should be decoupled with 10 μF and 0.1 μF
capacitors to AGND, as close to the pin as possible.
DVDD
Digital power supply. This pin is connected to a 1.8 V digital
supply. Connecting 10 μF and 0.1 μF decoupling capacitors to
DGND, as close to the pin as possible, is strongly recommended
for optimal performance.
ODVDD
Digital interface power supply pin. This pin should be
connected to a 3.3 V digital supply. The pin should be
decoupled with 10 μF and 0.1 μF capacitors to DGND, as
close to the pin as possible.
DGND
Digital ground.
AGND
Analog ground.
ODGND
Ground for the digital interface power supply.
SIF_REFP, SIF_REFCM, AND SIF_REFN
Decoupling nodes for the SIF block.
SIF_IN1 AND SIF_IN2
Analog inputs for the SIF block.
SIF_PGA_REF
PGA reference output. This pin should be decoupled to AGND
with 10 μF and 0.1 μF capacitors.
ISET
ADC current setting resistor.