Analog Devices SHARC ADSP-2136 Series Application guide

a
ADSP-2136x SHARC® Processor
Hardware Reference
Includes ADSP-21362, ADSP-21363,
ADSP-21364, ADSP-21365, ADSP-21366
Revision 2.0, June 2009
Part Number
82-000501-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
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Copyright Information
© 2008 Analog Devices, Inc., ALL RIGHTS RESERVED. This
document may not be reproduced in any form without prior, express writ-
ten consent from Analog Devices, Inc.
Printed in the USA.
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The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, the SHARC
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All other brand and product names are trademarks or service marks of
their respective owners.
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CONTENTS
PREFACE
Purpose of This Manual ............................................................... xxxi
Intended Audience ....................................................................... xxxi
Manual Contents ........................................................................ xxxii
What’s New in This Manual ....................................................... xxxiv
Technical or Customer Support .................................................. xxxvi
Supported Processors ................................................................. xxxvii
Product Information ................................................................. xxxvii
MyAnalog.com ................................................................... xxxviii
Processor Product Information ............................................ xxxviii
Related Documents .............................................................. xxxix
Online Technical Documentation .............................................. xl
Accessing Documentation From VisualDSP++ ....................... xl
Accessing Documentation From Windows ............................ xli
Accessing Documentation From the Web .............................. xli
Conventions ................................................................................. xlii
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Contents
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INTRODUCTION
ADSP-2136x SHARC Design Advantages ..................................... 1-1
SHARC Family Product Offerings ........................................... 1-5
Processor Architectural Overview .................................................. 1-6
Processor Core ........................................................................ 1-7
Processor Peripherals ............................................................... 1-7
I/O Processor ..................................................................... 1-7
Digital Applications Interface (DAI) ................................... 1-9
Development Tools ..................................................................... 1-10
Architecture Enhancements ......................................................... 1-10
Parallel Port Enhancements ................................................... 1-10
I/O Architecture Enhancements ............................................ 1-11
Instruction Set Enhancements ............................................... 1-11
I/O PROCESSOR
DMA Controller Operation .......................................................... 2-2
DMA Transfers Between Internal Memory ............................... 2-3
General Procedure for Configuring DMA ...................................... 2-4
Summary ................................................................................ 2-5
IOP Registers ............................................................................... 2-5
Standard DMA Parameter Registers ......................................... 2-6
Standard DMA Status Registers ............................................... 2-8
Chaining DMA Status Registers .............................................. 2-9
Data Buffers ........................................................................... 2-9
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Contents
DMA Channel Allocation ..................................................... 2-10
DMA Channel Priority ............................................................... 2-11
DMA Channel Arbitration Modes ......................................... 2-14
Peripheral DMA Bus ......................................................... 2-14
Rotating Priority by Group .................................................... 2-15
DMA Channel Interrupts ...................................................... 2-16
Internal Transfer Completion ............................................ 2-16
DMA Channel Interrupt Priorities ......................................... 2-16
Interrupt Versus Channel Priorities .................................... 2-17
DMA Controller Addressing .................................................. 2-18
Internal Index Register Addressing ......................................... 2-18
DMA Chaining ........................................................................... 2-20
TCB Memory Storage ............................................................ 2-20
Chain Pointer Register ...................................................... 2-21
Chain Assignment ................................................................. 2-22
Starting Chain Loading ......................................................... 2-24
TCB Chain Loading Priority ................................................. 2-25
Chain Insert Mode (SPORTs Only) ................................... 2-25
DMA Start and Stop Conditions ................................................. 2-25
Configuring IOP/Core Interaction .............................................. 2-26
Interrupt-Driven I/O ............................................................. 2-27
Polling DMA Channel Status ................................................. 2-28
Standard DMA Status ....................................................... 2-29
Chaining DMA Status ....................................................... 2-29
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TCB Storage ............................................................................... 2-30
Serial Port TCB .................................................................... 2-30
Parallel Port TCB .................................................................. 2-30
SPI TCB ............................................................................... 2-31
I/O Processor Register Access ...................................................... 2-32
IOP Access Conditions .......................................................... 2-32
Interrupt Latency ............................................................. 2-33
TCB Chain Loading Access ................................................... 2-34
IOP Register Access Arbitration ............................................. 2-34
IOP Performance .................................................................. 2-35
MEMORY-TO-MEMORY PORT DMA
Features ........................................................................................ 3-2
Functional Description ................................................................. 3-2
DMA Channels ....................................................................... 3-2
Buffer ..................................................................................... 3-3
Interrupts ............................................................................... 3-3
Data Throughput ......................................................................... 3-3
Programming Model ..................................................................... 3-4
Programming Example .................................................................. 3-4
PARALLEL PORT
Features ........................................................................................ 4-2
Pin Descriptions ........................................................................... 4-3
Multiplexed Pin Functions ...................................................... 4-4
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Contents
Functional Description ............................................................ 4-4
Multiplexed Operation ........................................................ 4-4
Address Cycles .................................................................... 4-4
Data Cycles ......................................................................... 4-5
Data Buffers ............................................................................ 4-6
Read Path ........................................................................... 4-6
Write Path .......................................................................... 4-7
Operation Modes .................................................................... 4-8
8-Bit Mode ......................................................................... 4-8
16-Bit Mode ....................................................................... 4-9
Parallel Port Registers .................................................................. 4-10
Control Register (PPCTL) ..................................................... 4-11
Data Buffer Register (RXPP/TXPP) ....................................... 4-11
Data Transfer Types .................................................................... 4-11
DMA Transfers ...................................................................... 4-12
DMA Internal Word Count Register (ICPP) ...................... 4-12
External Word Count Register (ECPP) .............................. 4-12
Chained DMA Transfers ........................................................ 4-13
DMA Chain Pointer Register (PPCP) ................................ 4-13
DMA Transfer Rules ......................................................... 4-13
Core-Driven Transfers ........................................................... 4-14
Interrupt Driven Accesses .................................................. 4-15
Status-Driven Transfers (Polling) ....................................... 4-16
Known-Duration Accesses ................................................. 4-16
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Core-Stall Driven Transfers ............................................... 4-17
Interrupts ................................................................................... 4-18
DMA Interrupts .................................................................... 4-19
Core Interrupts ..................................................................... 4-19
Throughput ................................................................................ 4-19
8-Bit Access .......................................................................... 4-20
16-Bit Access ........................................................................ 4-21
8-Bit Versus 16-Bit SRAM Modes ......................................... 4-22
Parallel Port Effect Latency .................................................... 4-23
Programming Model ................................................................... 4-23
Configuring the Parallel Port for DMA .................................. 4-24
Configuring a Chained DMA ................................................ 4-24
Configuring the Parallel Port for Core Access ......................... 4-25
Programming Examples .............................................................. 4-26
DIGITAL APPLICATION INTERFACE
Features ........................................................................................ 5-1
Functional Description ................................................................. 5-3
Signal Naming Conventions ......................................................... 5-5
DAI Peripherals ............................................................................ 5-6
I/O Pin Buffers ....................................................................... 5-7
Pin Buffers as Signal Output ............................................... 5-8
Pin Buffers as Signal Input ................................................ 5-10
Programmable Pull-Up Resistors ....................................... 5-11
Pin Buffers as Open Drain ................................................ 5-11
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Contents
Miscellaneous Buffers ............................................................ 5-12
Signal Routing Matrix by Groups ........................................... 5-13
DAI Group Routing .............................................................. 5-14
Rules for SRU Connections ................................................... 5-16
Making SRU Connections ..................................................... 5-16
Routing Capabilities .............................................................. 5-20
Default Routing .......................................................................... 5-21
Interrupt Controller .................................................................... 5-24
System versus Exception Interrupts ........................................ 5-24
Functional Description .......................................................... 5-25
Interrupt Channels ................................................................ 5-25
Interrupt Priorities ................................................................ 5-25
Miscellaneous Interrupts ........................................................ 5-26
Core versus DAI Interrupts .................................................... 5-26
Interrupt Events .................................................................... 5-27
Servicing Interrupts ............................................................... 5-28
Debug Features ........................................................................... 5-29
Shadow Registers ................................................................... 5-29
Loop Back Routing ................................................................ 5-30
Programming Model ................................................................... 5-31
SERIAL PORTS
Features ........................................................................................ 6-4
Pin Descriptions ........................................................................... 6-6
SRU Configuration ....................................................................... 6-6
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SRU SPORT Receive Master ................................................... 6-7
SRU SPORT Signal Integrity .................................................. 6-7
Functional Description ................................................................. 6-9
Registers ..................................................................................... 6-10
Control Registers (SPCTLx) .................................................. 6-12
Multichannel Control Registers (SPMCTLxy) ....................... 6-12
Data Buffers ......................................................................... 6-13
Transmit Buffers (TXSPxA/B) ........................................... 6-13
Transmit Path ............................................................... 6-14
Receive Buffers (RXSPxA/B) ............................................. 6-14
Receive Path ................................................................. 6-15
Buffer Status ..................................................................... 6-15
Multichannel Buffer Status ............................................... 6-17
Selecting Operating Modes ......................................................... 6-18
Mode Selection ..................................................................... 6-19
Data Word Formats .................................................................... 6-20
Word Length (SLEN) ............................................................ 6-20
Endian Format (LSBF) .......................................................... 6-21
Data Packing (PACK) ........................................................... 6-21
Data Type (DTYPE) ............................................................. 6-22
Companding the Data Stream ............................................... 6-23
Companding As a Function ................................................... 6-24
Clock Signal Options .................................................................. 6-25
Master Clock Divider Registers (DIVx) ................................. 6-25
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Contents
Master Clock .................................................................... 6-25
Master Frame Sync ............................................................ 6-26
Slave Mode ....................................................................... 6-26
Clock Source (ICLK, MSTR) ................................................ 6-27
Sampling Edge (CKRE) ......................................................... 6-27
Frame Sync Options .................................................................... 6-28
Framed Versus Unframed Frame Syncs ................................... 6-28
Internal Versus External Frame Syncs
(IFS, IMFS, MSTR) ........................................................... 6-29
Logic Level Frame Syncs (LFS, LMFS) ................................... 6-30
Early Versus Late Frame Syncs (LAFS) ................................... 6-31
Data-Independent Frame Sync (One Channel) ....................... 6-32
Data Independent Frame Sync (Two Channels) ...................... 6-33
Operating Modes ........................................................................ 6-34
Standard Serial Mode ............................................................. 6-34
Timing Control Bits .......................................................... 6-34
Clocking Options ............................................................. 6-35
Frame Sync Options .......................................................... 6-35
Left-Justified Mode ............................................................... 6-36
Master Serial Clock and Frame Sync Rates ......................... 6-36
Left-Justified Mode Timing Control Bits ........................... 6-37
Frame Sync Channel First (L_FIRST) ................................ 6-37
I2S Mode .............................................................................. 6-38
I2S Mode Timing Control Bits .......................................... 6-39
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Selecting Transmit and Receive Channel Order
(L_FIRST) .................................................................... 6-39
Multichannel Operation ........................................................ 6-40
Frame Syncs Signals .......................................................... 6-42
Transmit Valid Signals ...................................................... 6-43
Multichannel Mode Control Bits ...................................... 6-44
Number of Channels (NCH) ............................................ 6-45
Frame Delay (MFD) ......................................................... 6-45
Channel Selection Registers ................................................... 6-45
Companding Selection ...................................................... 6-46
Transmit Selection Registers .............................................. 6-46
Receive Selection Registers ................................................ 6-47
Data Transfer Types .................................................................... 6-47
Core Transfers ....................................................................... 6-47
Single Word Transfers ....................................................... 6-47
Internal Memory DMA Transfers .......................................... 6-48
Standard DMA ..................................................................... 6-50
DMA Chaining ..................................................................... 6-51
DMA Chain Insertion Mode ................................................. 6-52
Interrupts ................................................................................... 6-52
Internal Transfer Completion ................................................ 6-52
Shared Channels ................................................................... 6-53
Debug Features ........................................................................... 6-54
SPORT Loopback ................................................................. 6-54
Loopback Routing ............................................................ 6-55
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Contents
Buffer Hang Disable (BHD) .................................................. 6-55
Effect Latency ....................................................................... 6-55
Programming Model ................................................................... 6-56
Setting Up and Starting Chained DMA .................................. 6-56
Enter DMA Chain Insertion Mode ........................................ 6-57
Programming Examples ............................................................... 6-57
SERIAL PERIPHERAL INTERFACE PORTS
Features ........................................................................................ 7-1
Pin Descriptions ........................................................................... 7-3
SRU Programming ........................................................................ 7-4
Functional Description ................................................................. 7-5
Single Master Systems .............................................................. 7-7
Broadcast Access ...................................................................... 7-8
Multi Master Systems .............................................................. 7-8
Register Descriptions .................................................................. 7-10
Control Register (SPICTLx) .................................................. 7-10
Transfer Initiate Mode (TIMOD) ...................................... 7-11
Input Slave Select Enable (ISSEN) ..................................... 7-12
Disable MISO (DMISO) .................................................. 7-12
Word Lengths (WL) .......................................................... 7-13
Modes (CLKPL, CPHASE) ............................................... 7-14
Open Drain Mode (OPD) ................................................. 7-17
Enable (SPIEN) ................................................................ 7-17
Packing (PACKEN) .......................................................... 7-18
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Status Register (SPISTATx) ................................................... 7-18
Multi Master Error (MME) ............................................... 7-19
Transmission Error Bit (TUNF) ........................................ 7-20
Reception Error Bit (ROVF) ............................................. 7-20
Transmit Collision Error Bit (TXCOL) ............................. 7-20
BAUD Rate Register (SPIBAUDx) ........................................ 7-21
DMA Control Register (SPIDMACx) .................................... 7-21
Data Transfer Types .................................................................... 7-21
Core Transfers ....................................................................... 7-22
DMA Transfers ..................................................................... 7-22
Slave DMA Transfer Preparation ....................................... 7-24
DMA Chaining ................................................................ 7-25
Setting Up and Starting Chained DMA ......................... 7-25
Core and DMA Transfers ...................................................... 7-26
Changing Configuration ................................................... 7-26
Starting and Stopping Data Transfers ................................ 7-27
Interrupts ................................................................................... 7-28
Interrupt Sources .................................................................. 7-28
Internal Transfer Completion ............................................ 7-30
DMA Error Interrupts ...................................................... 7-30
Slave Select Timing ..................................................................... 7-31
Debug Features ........................................................................... 7-32
Shadow Register .................................................................... 7-32
Internal Loopback Mode ....................................................... 7-33
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Contents
Loopback Routing ............................................................ 7-33
Programming Model ................................................................... 7-33
Master Mode Core Transfers .................................................. 7-33
Slave Mode Core Transfers ..................................................... 7-35
Master Mode DMA Transfers ................................................. 7-36
Slave Mode DMA Transfers ................................................... 7-38
Chained DMA Transfers ........................................................ 7-39
Stopping Core Transfers ......................................................... 7-40
Stopping DMA Transfers ....................................................... 7-40
Switching from Transmit To Transmit/Receive DMA .............. 7-41
Switching from Receive to Receive/Transmit DMA ................. 7-42
Programming Examples ............................................................... 7-44
INPUT DATA PORT
Features ........................................................................................ 8-1
Functional Description ................................................................. 8-3
Serial Input Port ........................................................................... 8-4
Pin Descriptions ...................................................................... 8-5
SRU Descriptions .................................................................... 8-5
Input Data Formats ................................................................. 8-6
Register Descriptions ............................................................... 8-9
Control Registers (IDP_CTLx) ........................................... 8-9
Status Registers (DAI_STAT0) ............................................ 8-9
Parallel Data Acquisition Port (PDAP) ........................................... 8-9
Port Selection ........................................................................ 8-10
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Pin Descriptions ................................................................... 8-11
SRU Programming ........................................................... 8-12
Register Descriptions ............................................................ 8-12
Control Register (IDP_PP_CTL) ...................................... 8-12
PDAP Data Packing .............................................................. 8-13
Mode 11 (No Packing) ..................................................... 8-13
Mode 10 (Packing by 2) .................................................... 8-14
Mode 01 (Packing by 3) .................................................... 8-14
Mode 00 (Packing by 4) .................................................... 8-14
Timing ................................................................................. 8-15
Data Buffer ...................................................................... 8-17
Data Transfer Types .................................................................... 8-18
Core Transfers ....................................................................... 8-18
DMA Transfers ..................................................................... 8-19
DMA Channel Priority ..................................................... 8-19
Standard DMA ................................................................. 8-20
Ping-Pong DMA ............................................................... 8-20
Data Input Format ........................................................... 8-21
Multichannel DMA Operation ......................................... 8-22
Multichannel FIFO Status ................................................ 8-22
Interrupts ............................................................................. 8-23
Core FIFO Threshold Interrupts ....................................... 8-23
DMA Interrupts ............................................................... 8-23
FIFO Overflow Interrupts ................................................ 8-24
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Contents
Servicing Interrupts ........................................................... 8-24
Debug Features ........................................................................... 8-24
Buffer Hang Disable .............................................................. 8-25
Shadow Registers ................................................................... 8-25
Core FIFO Write ................................................................... 8-25
IDP Effect Latency ...................................................................... 8-26
Programming Model ................................................................... 8-26
Setting Miscellaneous Bits ..................................................... 8-26
Starting Core Interrupt-Driven Transfer ................................. 8-27
Starting A Standard DMA Transfer ........................................ 8-27
Starting a Ping-Pong DMA Transfer ....................................... 8-28
Servicing Interrupts for DMA ................................................ 8-29
Programming Example ................................................................ 8-31
PERIPHERAL TIMERS
Features ........................................................................................ 9-1
Pin Descriptions ........................................................................... 9-3
SRU Programming ........................................................................ 9-4
Functional Description ................................................................. 9-4
Register Descriptions .................................................................... 9-5
Count Registers ....................................................................... 9-5
Counter Registers (TMxCNT) ............................................ 9-6
Period Registers (TMxPRD) ................................................ 9-6
Pulse Width Register (TMxW) ............................................ 9-6
Status and Control Registers .................................................... 9-7
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Operation .................................................................................... 9-7
Mode Selection ....................................................................... 9-8
Pulse Width Modulation Mode (PWM_OUT) .................... 9-9
PWM Waveform Generation ......................................... 9-12
Single-Pulse Generation ................................................ 9-13
Pulse Mode ................................................................... 9-13
Pulse Width Count and Capture Mode (WDTH_CAP) .... 9-14
External Event Watchdog Mode (EXT_CLK) .................... 9-17
Interrupts ................................................................................... 9-19
Sources ................................................................................. 9-19
Watchdog Functionality ........................................................ 9-20
Effect Latency ....................................................................... 9-20
Debug Features ........................................................................... 9-21
Loopback Routing ................................................................ 9-21
Programming Model ................................................................... 9-22
PWM Out Mode .................................................................. 9-22
WDTH_CAP Mode ............................................................. 9-23
EXT_CLK Mode .................................................................. 9-24
Programming Examples .............................................................. 9-25
PULSE WIDTH MODULATION
Features ...................................................................................... 10-1
Pin Descriptions ......................................................................... 10-4
Functional Description ............................................................... 10-4
Register Descriptions .................................................................. 10-5
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Contents
Operation Modes ........................................................................ 10-6
Groups Synchronization ........................................................ 10-6
PWM Timer ..................................................................... 10-7
Edge-Aligned Mode .......................................................... 10-8
Center-Aligned Mode ........................................................ 10-9
Switching Frequencies ......................................................... 10-11
Dead Time .......................................................................... 10-12
Duty Cycles ........................................................................ 10-13
Duty Cycles and Dead Time ............................................ 10-13
Over-Modulation ............................................................ 10-18
Update Modes ..................................................................... 10-20
Single-Update ................................................................. 10-20
Double-Update ............................................................... 10-20
Configuring Polarity ................................................................. 10-20
Accuracy ................................................................................... 10-21
Duty Cycle .......................................................................... 10-22
Output Enable .................................................................... 10-22
Crossover Mode .................................................................. 10-23
Interrupts ................................................................................. 10-24
Debug Features ......................................................................... 10-24
Programming Example .............................................................. 10-24
SONY/PHILIPS DIGITAL INTERFACE
Features ...................................................................................... 11-2
S/PDIF Transmitter .................................................................... 11-3
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Pin Descriptions ................................................................... 11-3
SRU Programming ................................................................ 11-4
Functional Description ......................................................... 11-5
Input Data Format ................................................................ 11-7
Output Data Mode ............................................................... 11-8
Operation Modes .................................................................. 11-9
Standalone Mode .............................................................. 11-9
Full Serial Mode ............................................................... 11-9
Register Descriptions ............................................................ 11-9
Control Register (DITCTL) ............................................. 11-9
Channel Status Registers (DITCHANAx/Bx) .................. 11-10
S/PDIF Receiver ....................................................................... 11-10
Pin Descriptions ................................................................. 11-11
SRU Programming .............................................................. 11-12
Functional Description ....................................................... 11-13
Output Data Format ........................................................... 11-13
PLL Selection for Clock Recovery ........................................ 11-13
Register Descriptions .......................................................... 11-14
Receiver Control Register (DIRCTL) .............................. 11-14
Receiver Status Register (DIRSTAT) ............................... 11-15
Clock Recovery ................................................................... 11-17
Channel Decoding .................................................................... 11-17
Channel Status .................................................................... 11-17
Compressed or Non-linear Audio Data ................................ 11-18
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