Analog Devices SHARC ADSP-2136 Series Application guide

a
ADSP-2136x SHARC® Processor
Hardware Reference
Includes ADSP-21362, ADSP-21363,
ADSP-21364, ADSP-21365, ADSP-21366
Revision 2.0, June 2009
Part Number
82-000501-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
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Copyright Information
© 2008 Analog Devices, Inc., ALL RIGHTS RESERVED. This
document may not be reproduced in any form without prior, express writ-
ten consent from Analog Devices, Inc.
Printed in the USA.
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Trademark and Service Mark Notice
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their respective owners.
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ADSP-2136x SHARC Processor Hardware Reference iii
for the ADSP-21362/3/4/5/6 Processors
CONTENTS
PREFACE
Purpose of This Manual ............................................................... xxxi
Intended Audience ....................................................................... xxxi
Manual Contents ........................................................................ xxxii
What’s New in This Manual ....................................................... xxxiv
Technical or Customer Support .................................................. xxxvi
Supported Processors ................................................................. xxxvii
Product Information ................................................................. xxxvii
MyAnalog.com ................................................................... xxxviii
Processor Product Information ............................................ xxxviii
Related Documents .............................................................. xxxix
Online Technical Documentation .............................................. xl
Accessing Documentation From VisualDSP++ ....................... xl
Accessing Documentation From Windows ............................ xli
Accessing Documentation From the Web .............................. xli
Conventions ................................................................................. xlii
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Contents
iv ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
INTRODUCTION
ADSP-2136x SHARC Design Advantages ..................................... 1-1
SHARC Family Product Offerings ........................................... 1-5
Processor Architectural Overview .................................................. 1-6
Processor Core ........................................................................ 1-7
Processor Peripherals ............................................................... 1-7
I/O Processor ..................................................................... 1-7
Digital Applications Interface (DAI) ................................... 1-9
Development Tools ..................................................................... 1-10
Architecture Enhancements ......................................................... 1-10
Parallel Port Enhancements ................................................... 1-10
I/O Architecture Enhancements ............................................ 1-11
Instruction Set Enhancements ............................................... 1-11
I/O PROCESSOR
DMA Controller Operation .......................................................... 2-2
DMA Transfers Between Internal Memory ............................... 2-3
General Procedure for Configuring DMA ...................................... 2-4
Summary ................................................................................ 2-5
IOP Registers ............................................................................... 2-5
Standard DMA Parameter Registers ......................................... 2-6
Standard DMA Status Registers ............................................... 2-8
Chaining DMA Status Registers .............................................. 2-9
Data Buffers ........................................................................... 2-9
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ADSP-2136x SHARC Processor Hardware Reference v
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Contents
DMA Channel Allocation ..................................................... 2-10
DMA Channel Priority ............................................................... 2-11
DMA Channel Arbitration Modes ......................................... 2-14
Peripheral DMA Bus ......................................................... 2-14
Rotating Priority by Group .................................................... 2-15
DMA Channel Interrupts ...................................................... 2-16
Internal Transfer Completion ............................................ 2-16
DMA Channel Interrupt Priorities ......................................... 2-16
Interrupt Versus Channel Priorities .................................... 2-17
DMA Controller Addressing .................................................. 2-18
Internal Index Register Addressing ......................................... 2-18
DMA Chaining ........................................................................... 2-20
TCB Memory Storage ............................................................ 2-20
Chain Pointer Register ...................................................... 2-21
Chain Assignment ................................................................. 2-22
Starting Chain Loading ......................................................... 2-24
TCB Chain Loading Priority ................................................. 2-25
Chain Insert Mode (SPORTs Only) ................................... 2-25
DMA Start and Stop Conditions ................................................. 2-25
Configuring IOP/Core Interaction .............................................. 2-26
Interrupt-Driven I/O ............................................................. 2-27
Polling DMA Channel Status ................................................. 2-28
Standard DMA Status ....................................................... 2-29
Chaining DMA Status ....................................................... 2-29
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Contents
vi ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
TCB Storage ............................................................................... 2-30
Serial Port TCB .................................................................... 2-30
Parallel Port TCB .................................................................. 2-30
SPI TCB ............................................................................... 2-31
I/O Processor Register Access ...................................................... 2-32
IOP Access Conditions .......................................................... 2-32
Interrupt Latency ............................................................. 2-33
TCB Chain Loading Access ................................................... 2-34
IOP Register Access Arbitration ............................................. 2-34
IOP Performance .................................................................. 2-35
MEMORY-TO-MEMORY PORT DMA
Features ........................................................................................ 3-2
Functional Description ................................................................. 3-2
DMA Channels ....................................................................... 3-2
Buffer ..................................................................................... 3-3
Interrupts ............................................................................... 3-3
Data Throughput ......................................................................... 3-3
Programming Model ..................................................................... 3-4
Programming Example .................................................................. 3-4
PARALLEL PORT
Features ........................................................................................ 4-2
Pin Descriptions ........................................................................... 4-3
Multiplexed Pin Functions ...................................................... 4-4
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ADSP-2136x SHARC Processor Hardware Reference vii
for the ADSP-21362/3/4/5/6 Processors
Contents
Functional Description ............................................................ 4-4
Multiplexed Operation ........................................................ 4-4
Address Cycles .................................................................... 4-4
Data Cycles ......................................................................... 4-5
Data Buffers ............................................................................ 4-6
Read Path ........................................................................... 4-6
Write Path .......................................................................... 4-7
Operation Modes .................................................................... 4-8
8-Bit Mode ......................................................................... 4-8
16-Bit Mode ....................................................................... 4-9
Parallel Port Registers .................................................................. 4-10
Control Register (PPCTL) ..................................................... 4-11
Data Buffer Register (RXPP/TXPP) ....................................... 4-11
Data Transfer Types .................................................................... 4-11
DMA Transfers ...................................................................... 4-12
DMA Internal Word Count Register (ICPP) ...................... 4-12
External Word Count Register (ECPP) .............................. 4-12
Chained DMA Transfers ........................................................ 4-13
DMA Chain Pointer Register (PPCP) ................................ 4-13
DMA Transfer Rules ......................................................... 4-13
Core-Driven Transfers ........................................................... 4-14
Interrupt Driven Accesses .................................................. 4-15
Status-Driven Transfers (Polling) ....................................... 4-16
Known-Duration Accesses ................................................. 4-16
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Contents
viii ADSP-2136x SHARC Processor Hardware Reference
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Core-Stall Driven Transfers ............................................... 4-17
Interrupts ................................................................................... 4-18
DMA Interrupts .................................................................... 4-19
Core Interrupts ..................................................................... 4-19
Throughput ................................................................................ 4-19
8-Bit Access .......................................................................... 4-20
16-Bit Access ........................................................................ 4-21
8-Bit Versus 16-Bit SRAM Modes ......................................... 4-22
Parallel Port Effect Latency .................................................... 4-23
Programming Model ................................................................... 4-23
Configuring the Parallel Port for DMA .................................. 4-24
Configuring a Chained DMA ................................................ 4-24
Configuring the Parallel Port for Core Access ......................... 4-25
Programming Examples .............................................................. 4-26
DIGITAL APPLICATION INTERFACE
Features ........................................................................................ 5-1
Functional Description ................................................................. 5-3
Signal Naming Conventions ......................................................... 5-5
DAI Peripherals ............................................................................ 5-6
I/O Pin Buffers ....................................................................... 5-7
Pin Buffers as Signal Output ............................................... 5-8
Pin Buffers as Signal Input ................................................ 5-10
Programmable Pull-Up Resistors ....................................... 5-11
Pin Buffers as Open Drain ................................................ 5-11
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Contents
Miscellaneous Buffers ............................................................ 5-12
Signal Routing Matrix by Groups ........................................... 5-13
DAI Group Routing .............................................................. 5-14
Rules for SRU Connections ................................................... 5-16
Making SRU Connections ..................................................... 5-16
Routing Capabilities .............................................................. 5-20
Default Routing .......................................................................... 5-21
Interrupt Controller .................................................................... 5-24
System versus Exception Interrupts ........................................ 5-24
Functional Description .......................................................... 5-25
Interrupt Channels ................................................................ 5-25
Interrupt Priorities ................................................................ 5-25
Miscellaneous Interrupts ........................................................ 5-26
Core versus DAI Interrupts .................................................... 5-26
Interrupt Events .................................................................... 5-27
Servicing Interrupts ............................................................... 5-28
Debug Features ........................................................................... 5-29
Shadow Registers ................................................................... 5-29
Loop Back Routing ................................................................ 5-30
Programming Model ................................................................... 5-31
SERIAL PORTS
Features ........................................................................................ 6-4
Pin Descriptions ........................................................................... 6-6
SRU Configuration ....................................................................... 6-6
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Contents
x ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
SRU SPORT Receive Master ................................................... 6-7
SRU SPORT Signal Integrity .................................................. 6-7
Functional Description ................................................................. 6-9
Registers ..................................................................................... 6-10
Control Registers (SPCTLx) .................................................. 6-12
Multichannel Control Registers (SPMCTLxy) ....................... 6-12
Data Buffers ......................................................................... 6-13
Transmit Buffers (TXSPxA/B) ........................................... 6-13
Transmit Path ............................................................... 6-14
Receive Buffers (RXSPxA/B) ............................................. 6-14
Receive Path ................................................................. 6-15
Buffer Status ..................................................................... 6-15
Multichannel Buffer Status ............................................... 6-17
Selecting Operating Modes ......................................................... 6-18
Mode Selection ..................................................................... 6-19
Data Word Formats .................................................................... 6-20
Word Length (SLEN) ............................................................ 6-20
Endian Format (LSBF) .......................................................... 6-21
Data Packing (PACK) ........................................................... 6-21
Data Type (DTYPE) ............................................................. 6-22
Companding the Data Stream ............................................... 6-23
Companding As a Function ................................................... 6-24
Clock Signal Options .................................................................. 6-25
Master Clock Divider Registers (DIVx) ................................. 6-25
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