Beck IPC SC123 User manual

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 1
Hardware Manual
IPC@CHIP Embedded Controller Family
SC123/SC143
High Performance, 80186-Compatible,
16-Bit Embedded Microcontroller
Single Chip PC with Flash, RAM, Watchdog
Order No. IPC@CHIP
Embedded Controller SC123:
541094
Embedded Controller SC123-LF:
543257
Embedded Controller SC123-IEC:
541528
Embedded Controller SC123-IEC-LF:
543259
Embedded Controller SC143:
541529
Embedded Controller SC143-LF:
543258
Embedded Controller SC143-IEC:
541530
Embedded Controller SC143-IEC-LF:
543260

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 2
Copyright & Trademark
IPC@CHIP® is a registered trademark of Beck IPC. Ethernet is a
registered trademark of Xerox Corporation. All other product names,
company names, logos or other designations mentioned herein are
trademarks of their respective owners.
AM186 is a trademark of Advanced Micro Devices, Inc.
Ethernet is a registered trademark of Xerox Corporation.
SPI is a trademark of Motorola, Inc.
No part of this guide may be reproduced or transmitted in any form for
any purpose other than the purchaser's personal use, without the express
written permission of Beck IPC.
Beck IPC GmbH
Grüninger Weg 24
35415 Pohlheim-Garbenteich / Germany
Phone: [phone]
Fax: [phone]
Technical Support
Phone: [phone]
Fax: [phone]
Online: www.beck-ipc.com
E-mail: [email protected]

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 3
Table of Contents
1Overview .................................................................................................................... 7
2Features..................................................................................................................... 8
3Block Diagram............................................................................................................ 9
4Pin Description ......................................................................................................... 10
4.1 Pin Configuration ........................................................................................................................ 10
4.2 System Interface......................................................................................................................... 11
4.3 Chip Selects................................................................................................................................ 13
4.4 DMA............................................................................................................................................ 14
4.5 Interrupts..................................................................................................................................... 14
4.6 UART0 Interface......................................................................................................................... 14
4.7 UART1 Interface......................................................................................................................... 15
4.8 UART2 Interface......................................................................................................................... 15
4.9 I²C Bus........................................................................................................................................ 16
4.10 Pure PIOs ................................................................................................................................... 16
4.11 SPI Bus / UART3........................................................................................................................ 17
4.12 Timers......................................................................................................................................... 17
4.13 CAN Bus Interface...................................................................................................................... 18
4.14 USB Interface ............................................................................................................................. 18
4.15 JTAG Interface............................................................................................................................ 18
4.16 Ethernet 0 Interface (Internal PHY) ............................................................................................ 19
4.17 MII Ethernet 1 Interface (External PHY)..................................................................................... 19
4.18 PHY Power (Internal PHY) ......................................................................................................... 20
4.19 Power.......................................................................................................................................... 20
4.20 Programmable I/O Pins .............................................................................................................. 21
5System Start-up Configuration.................................................................................. 22
5.1 PIO Pins...................................................................................................................................... 22
5.2 Address Pins............................................................................................................................... 22
5.3 PFI Pin........................................................................................................................................ 23
6Functional Description.............................................................................................. 24
6.1 CPU ............................................................................................................................................ 24
6.1.1 Registers ............................................................................................................................................... 24
6.1.2 Memory Organization ............................................................................................................................ 25
6.1.3 24-Bit Address Mode............................................................................................................................. 25
6.1.4 Peripheral Accesses through the Address-/Databus ............................................................................. 26
6.2 UARTs ........................................................................................................................................ 32
6.2.1 RTOS Update via serial ports................................................................................................................ 32
6.3 SPI.............................................................................................................................................. 33
6.4 I²C............................................................................................................................................... 35
6.5 CAN ............................................................................................................................................ 36
6.5.1 Introduction............................................................................................................................................ 36
6.5.2 TX Channels.......................................................................................................................................... 37
6.5.3 RX Channel ........................................................................................................................................... 37
6.6 USB............................................................................................................................................. 38
6.7 Power Fail Interrupt .................................................................................................................... 39
6.7.1 Description............................................................................................................................................. 39

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 4
6.7.2 Storing non-volatile data to internal flash memory................................................................................. 39
6.7.3 Storing non-volatile data to external memory ........................................................................................ 39
6.8 Mapping external memory.......................................................................................................... 40
6.9 MII Interface................................................................................................................................ 40
6.10 Timers......................................................................................................................................... 41
6.11 Reset........................................................................................................................................... 41
7System Overview...................................................................................................... 42
7.1 Memory map............................................................................................................................... 42
7.2 System interrupts........................................................................................................................ 43
7.3 Watchdog.................................................................................................................................... 43
8Characteristics.......................................................................................................... 44
8.1 Absolute Maximum Ratings........................................................................................................ 44
8.2 Recommended Operating Ranges............................................................................................. 44
8.2.1 Voltage and Temperature...................................................................................................................... 44
8.2.2 Supply Current....................................................................................................................................... 44
8.2.3 Inputs..................................................................................................................................................... 45
8.2.4 Outputs.................................................................................................................................................. 45
8.2.5 Programmable Input/Output Pins .......................................................................................................... 45
8.2.6 XIN/XOUT Pins...................................................................................................................................... 45
8.2.7 PHY Receiver Input Characteristics ...................................................................................................... 46
8.2.8 100Base-TX Transceiver Characteristics .............................................................................................. 46
8.3 AC Characteristics...................................................................................................................... 47
8.3.1 Timing Parameter List............................................................................................................................ 47
8.3.2 System bus timing ................................................................................................................................. 48
8.3.3 Reset timing........................................................................................................................................... 49
9Routing and Placement Rules.................................................................................. 50
9.1 PCB Board Design suggestion for SC123/SC143...................................................................... 50
9.2 Routing and placement rules for Ethernet components ............................................................. 51
9.3 Suggested Magnetics ................................................................................................................. 51
10 Package Information.............................................................................................. 52
10.1 Dimensions................................................................................................................................. 52
10.2 Cover Description ....................................................................................................................... 53
11 Application Examples ............................................................................................ 54
11.1 Minimum Circuit Requirements .................................................................................................. 54
11.2 Ethernet Example Circuit............................................................................................................ 55
11.3 External memory......................................................................................................................... 56
11.4 Traffic/Link/Speed LEDs............................................................................................................. 57
11.5 SC1x3 Socket............................................................................................................................. 58
11.6 Custom series programming of SC1x3....................................................................................... 58
12 CPUCLK handling ................................................................................................. 59
13 Reflow Profile ........................................................................................................ 60
14 History ................................................................................................................... 61

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 5
List of Figures
Figure 3-1: Block Diagram............................................................................................................................................... 9
Figure 4-1: Ball Grid Array Looking through Top of Package ........................................................................................ 10
Figure 5-1: power on flowchart with power fail interrupt enabled................................................................................... 23
Figure 6-1: 24-Bit Address Generation.......................................................................................................................... 25
Figure 6-2: Contiguously segments in memory ............................................................................................................. 25
Figure 6-3: 8 Bit read access from C00h, CSBE = 0, Read = 0x55 ............................................................................... 26
Figure 6-4: 16 Bit read access from C00h, CSBE = 0, Read = 0x1234.......................................................................... 26
Figure 6-5: 16 Bit read access from C01h, CSBE = 0, Read = 0x5678.......................................................................... 27
Figure 6-6: 8 Bit read access from C01h, CSBE = 0, Read = 0x55 ............................................................................... 27
Figure 6-7: 8 Bit write access to C00h, CSBE = 0, Write = 0x23.................................................................................... 28
Figure 6-8: 16 Bit write access to C00h, CSBE = 0, Write = 0x1234.............................................................................. 28
Figure 6-9: 16 Bit write access to C01h, CSBE = 0, Write = 0x5678.............................................................................. 29
Figure 6-10: 8 Bit write access to C01h, CSBE = 0, Write = 0x23 ................................................................................. 29
Figure 6-11: 8 Bit write access to C00h, CSBE = 1, Write = 0x23 ................................................................................. 30
Figure 6-12: 8 Bit write access to C01h, CSBE = 1, Write = 0x23 ................................................................................. 30
Figure 6-13: 16 Bit write access to C00h, CSBE = 1, Write = 0x1234............................................................................ 31
Figure 6-14: 16 Bit write access to C01h, CSBE = 1, Write = 0x5678............................................................................ 31
Figure 6-15: TX Message Routing................................................................................................................................. 37
Figure 6-16: Pullup-/down Resistors for USB full-speed device.................................................................................... 38
Figure 6-17: Sketch of the logic to decode the chip select for an external memory....................................................... 40
Figure 6-18: Internal reset processing........................................................................................................................... 41
Figure 7-1: Memory Map............................................................................................................................................... 42
Figure 8-1: System bus timing....................................................................................................................................... 48
Figure 8-2: Reset Timing............................................................................................................................................... 49
Figure 9-1: PCB Board Design suggestion.................................................................................................................... 50
Figure 9-2: PCB Board Design suggestion.................................................................................................................... 50
Figure 10-1: Package Dimensions ................................................................................................................................ 52
Figure 10-2: Cover......................................................................................................................................................... 53
Figure 11-1: Minimum Circuit Requirements for SC1x3 ................................................................................................ 54
Figure 11-2: Ethernet Example Circuit........................................................................................................................... 55
Figure 11-3: Example circuit for connecting an external memory.................................................................................. 56
Figure 11-4: Circuit Example for two bi-coloured LEDs................................................................................................. 57
Figure 11-5: Circuit Example for four mono-coloured LEDs.......................................................................................... 57
Figure 11-6: SC1x3-Socket........................................................................................................................................... 58
Figure 13-1: Reflow Profile............................................................................................................................................ 60

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 6
List of Tables
Table 4-1: Pin Description of System Interface ............................................................................................................. 12
Table 4-2: Pin Description of Chip Selects.................................................................................................................... 13
Table 4-3: Pin Description of DMA Request Pins.......................................................................................................... 14
Table 4-4: Pin Description of Interrupts......................................................................................................................... 14
Table 4-5: Pin Description of UART0............................................................................................................................. 14
Table 4-6: Pin Description of UART1............................................................................................................................. 15
Table 4-7: Pin Description of UART2............................................................................................................................. 15
Table 4-8: Pin Description of I²C Bus ............................................................................................................................ 16
Table 4-9: Pin Description of Pure PIO pins.................................................................................................................. 16
Table 4-10: Pin Description of SPI Bus / UART3........................................................................................................... 17
Table 4-11: Pin Description of Timers ........................................................................................................................... 17
Table 4-12: Pin Description of CAN Bus........................................................................................................................ 18
Table 4-13: Pin Description of USB............................................................................................................................... 18
Table 4-14: Pin Description of JTAG............................................................................................................................. 18
Table 4-15: Pin Description of internal PHY.................................................................................................................. 19
Table 4-16: Pin Description of MII ................................................................................................................................. 19
Table 4-17: Pin Description of PHY Power Pins............................................................................................................ 20
Table 4-18: Pin Description of Power Pins.................................................................................................................... 20
Table 4-19: List of PIO sharing designations................................................................................................................. 21
Table 6-1: General Purpose Registers.......................................................................................................................... 24
Table 6-2: Segment, Status and Control Registers....................................................................................................... 24
Table 6-3: Segment Register Selection Rules............................................................................................................... 25
Table 6-4:Context between SDO and SDI to MOSI and MISO in different modes ........................................................ 34
Table 6-5: Provided CAN baud rates............................................................................................................................. 36
Table 6-6: Truth Table of FLSSEL and UCSOUT# and external memory..................................................................... 40
Table 8-1: Absolute Maximum Ratings.......................................................................................................................... 44
Table 8-2: Recommended Operating Ranges............................................................................................................... 44
Table 8-3: Supply Current ............................................................................................................................................. 44
Table 8-4: Inputs ........................................................................................................................................................... 45
Table 8-5: Outputs......................................................................................................................................................... 45
Table 8-6: PIOs............................................................................................................................................................. 45
Table 8-7: 3. I/O Characteristics Xin/Xout Pins ............................................................................................................. 45
Table 8-8: PHY Receiver Input Characteristics............................................................................................................. 46
Table 8-9: 100Base-TX Transceiver Characteristics..................................................................................................... 46
Table 8-10: AC Characteristics...................................................................................................................................... 47
Table 10-1: Package Dimensions.................................................................................................................................. 52
Table 13-1: Typical Reflow Profile Conditions............................................................................................................... 60

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 7
1 Overview
The IPC@CHIP® SC1X3 family is a combination of hardware and software including the preinstalled real time
operating system, TCP/IP stack, Web server, FTP server, Telnet server, enable designers to reduce the size, power
consumption, and cost of embedded systems, while increasing reliability, functionality, performance and time to
market.
The IPC@CHIP® SC1x3 family of System on Chip microcontrollers are embedded controllers that come with a 16-bit
186 processor and are designed to WEB- or LAN-enable products. The operating frequency is up to 96 MHz, the
package is a BGA-177 package.
The IPC@CHIP® SC1x3 family is the ideal solution for new designs requiring Ethernet TCP/IP communication over
twisted pair and/or through any serial interface. They come with an integrated 8MByte RAM and up to 8MByte FLASH,
thus reducing memory subsystem costs. The minimum endurance of the Flash memory is 100.000 write cycles
(depending on environmental stress e.g. temperature, used space and file size).
The IPC@CHIP® SC1X3 family microcontrollers also integrate the functions of the CPU, address bus, data bus, two
independent timers, watchdog timer, chip selects, interrupt controller, DMA controller, four asynchronous serial ports,
and programmable I/O pins on one chip. It also supports I²C-Bus and SPI (Serial Peripheral Interface). The USB
device interface supports user specific connections to standard USB hosts like PCs.
The IPC@CHIP® SC1X3 family is a highly integrated design that provides all Media Access Control (MAC) and
Encode-Decode (ENDEC) functions in accordance with the IEEE 802.3, 802.3u, and 802.3af standard. The integrated
10/100Base-T PHY makes IPC@CHIP® SC1X3 more cost-effective.
The IPC@CHIP® SC1X3 has been designed to meet the most common requirements of embedded products
developed for the communications, office automation, mass storage, and general embedded markets. Specific
applications would include industrial controls, data collection, protocol conversion, process monitoring and internet
connectivity.
As an option it can also be used in combination with an IEC61131-3 CoDeSys Run Time System.
IPC@CHIP
RAM
FLASH
CoDeSys license included
SC123
8 MByte
2 MByte
no
SC123-IEC
8 MByte
2 MByte
yes
SC143
8 MByte
8 MByte
no
SC143-IEC
8 MByte
8 MByte
yes

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 8
2 Features
16-bit SC186-EX CPU
Software compatible with SC186/AM186
(x86 instruction set)
Programmable PLL provides up to 96 MHz
using one 25MHz Clock
256 KByte internal fast SRAM (zero wait state
operation)
Embedded boot loader in ROM
Full external system bus interface
24-bit address bus
16-bit data bus
Programmable Chip Selects
Embedded Ethernet controllers
Two 10/100Mbps Ethernet Controllers with
one built-in PHY and one MII PHY interface,
32 byte FIFOs
Four high performance serial ports
RS232/422/485 RTS/CTS and DMA
Enhanced receive FIFOs (4 deep)
Additional handshake control
Two CAN V2.0B 1 Mbps controllers
hardware priority queuing and data filtering
features
One Universal Serial Bus (USB) 1.1 Port
One 3-wire Serial Peripheral Interface (SPI)
controller (48MHz)
One 2-wire I²C serial controller
JTAG interface
In-circuit emulator support with breakpoints
and trace buffer
Four DMA channels, interrupt controller, 2
independent timers, and external memory
select logic
Watchdog-timer and power-on reset logic
Internal 8 MByte SDRAM memory
Up to 8 MByte Flash memory
Expandable through external Flash memory
Special NV-SRAM interface supports external
non-volatile memory
31 GPIO pins
Package 25x25 mm 177 PBGA, 1.27 pitch, lead
free, RoHS compliant
Temperature range: -25°C to 85°C ambient
Power Dissipation < 2 W
Pre-installed Real Time Operating System
(IPC@CHIP RTOS)
Software-compatible with the 80C186
microcontrollers and IPC@CHIP family
SC11/12/13 with widely available native
development tools, applications, and system
software

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Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 9
3 Block Diagram
Figure 3-1: Block Diagram
SDRAM
FLASH
RX, TX
10/100 Ethernet
MII Interface 1
PIO24:0
PIO31:26
PLL
XIN, XOUT,
CPUCLK, PLLBYP
LED 3:0
Reset
Generator,
Watchdog
PHY
Ethernet MAC 1:0
System Interface
ARDY
Asynch.
Serial
Ports
TXD 3,2,1,0
RXD 3,2,1,0
RTS 3,2,1,0
CTS 3,2,1,0
DMA
Controller
PIO Unit
Timer
Controller
TMRIN 1:0
TMROUT 1:0
Interrupt
Controller
INT 1,3,5#
PFI
Chip-
Select Unit
USB
CAN
Controller
I²C
Controller
SPI
Controller
RSTIN, RSTOUT
USBP, USBN
CANTXD 1:0
CANRXD 1:0
I2CCLK, I2CDTA
PCS7:0, MCS0
UCSOUT#, FLSSEL
SDI, SDO, SCK,
SLVSEL
WR#
WRL#
RD#
WRH#
D15:0
A22:1
UCSIN#
DRQ 3:0

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 10
4 Pin Description
4.1 Pin Configuration
Figure 4-1: Ball Grid Array Looking through Top of Package
DNC Do Not Connect !

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 11
4.2 System Interface
Ball Pin
Name
Ball
Pin
Type
Description
CPUCLK
R8
OUT [24mA]
CPU Clock Output
This pin is driven from the output of the internal PLL.
If it used as output, don’t connect anything with more than 1pF
capacitive load ! See chapter 12.
PLLBYP#
L2
IN
PLL Bypass Input (Active LOW with Pull-up)
PLLBYP# is not supported anymore! See history, chapter 14.
This input, when pulled LOW, bypasses the internal PLL and uses
the CPUCLK pin as the source for the CPU.
WR#
T1
OUT [16mA]
Write Output (Active LOW with Pull-up)
This pin indicates that the current bus cycle is a memory or I/O write
cycle.
RD#
P2
OUT [16mA]
Read Output (Active LOW with Pull-up)
This pin indicates that the current bus cycle is a memory or I/O read
cycle.
WRH#
M1
OUT [16mA]
Write High Output (Active Low with Pull-up)
This pin indicates that the current bus cycle is a memory or I/O write
cycle and that the upper byte is being driven with valid data.
It can be used as BHE# (see chapter 5).
WRL#
L1
OUT [16mA]
Write Low Output (Active LOW with Pull-up)
This pin indicates that the current bus cycle is a memory or I/O write
cycle and that the lower byte is being driven with valid data.
It can be used as A0 (see chapter 5).
PIO17(1)
HOLD(1) (2)
D3
I/O [4mA]
IN
Hold (Active HIGH)
Hold is not supported anymore! See history, chapter 14.
This pin can be used as HOLD input. When driven HIGH by an
external bus master, the CPU responds with HLDA and releases the
bus for external use.
It can also be used as PIO[17].
HLDA(2)
B1
OUT [4mA]
Hold Acknowledge (Active HIGH)
HLDA is not supported anymore! See history, chapter 14.
This pin goes HIGH to indicate the bus has been released for use by
an external bus master.
PIO6(1)
ARDY(1)
B3
I/O [4mA]
IN
Asynchronous Ready (Active HIGH)
This pin can be used with an external ready source. ARDY is double
synchronized internally using the falling edge of CPUCLK. It can be
used to extend external accesses.
It can also be used as PIO[6].
LCS#(2)
D1
IN
Lower Chip Select (Schmitt Trigger Input Active LOW with Pull-up)
LCS# is not supported anymore! See history, chapter 14.
This pin is used by an external bus master to enable reading and
writing the internal SRAM.
RSTIN#(1)
J1
IN
Reset Input (Schmitt Trigger Input, Active LOW with Pull-up)
This pin causes the CPU to perform a reset. When this pin is
asserted, the CPU immediately terminates any current bus cycles,
resets internal logic and prepares for executing code at the reset
address FFFFE0h.
RSTIN# is synchronized internally and extended internally to allow
~200 ms for the startup configuration (chapter 5) to settle to the
values driven by there individual resistors. This input is provided
with a Schmitt trigger to power-on via an RC network.
RSTOUT#
U1
OUT [4mA]
Reset Output (Active LOW)
This pin indicates whether the CPU is being reset. It indicates that
the internal logic is being reset and is to be used to reset any
external peripherals.

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©2000-2008 BECK IPC GmbH Page 12
Ball Pin
Name
Ball
Pin
Type
Description
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
T2
R2
U2
T3
U3
R4
T4
U4
U14
U15
U16
U17
T15
T16
T17
R16
I/O [8mA]
CPU Data Bus (Active HIGH with Pull-downs)
These pins supply the data to the memory or I/O of the system.
A[22]
A[21]
A[20]
A[19]
A[18]
A[17]
A[16]
A[15]
A[14]
A[13]
A[12]
A[11]
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
U11
T8
T11
U10
R9
T7
U7
T5
R6
R7
R10
U9
T10
R11
T9
U13
U12
R12
T12
R14
T13
T14
OUT [8mA]
Address Bus (with Pull-ups and Pull-downs)
These pins supply the address to memory or I/O of the system.
Table 4-1: Pin Description of System Interface
Note 1: 5V tolerant

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4.3 Chip Selects
Ball Pin
Name
Ball
Pin
Type
Description
MCS[0]#
U8
OUT [8mA]
Middle Memory Chip Select Output [8mA] (Active LOW)
This pin indicates an access to the internal SDRAM. (Do not
connect).
PCS[3]#
PCS[2]#
PCS[1]#
PCS[0]#
G3
F2
M3
F1
OUT [8mA]
OUT [8mA]
OUT [8mA]
OUT [8mA]
Peripheral Chip Select Output (Active LOW)
These pins indicate to the system that a bus cycle is in progress to
the corresponding region of the peripheral space.
PIO5(1)
PCS[7]#
P3
I/O [4mA]
OUT [4mA]
Peripheral Chip Select Output [4mA] (Active LOW)
This pin indicates to the system that a bus cycle is in progress to
address 0xE00 of the peripheral space.
It can also be used as PIO[5].
PIO4(1)
PCS[4]#
H3
I/O [4mA]
OUT [4mA]
Peripheral Chip Select Output (Active LOW)
This pin indicates to the system that a bus cycle is in progress to
address 0x800 of the peripheral space.
It can also be used as PIO[4].
PIO3(1)
PCS[5]#
K3
I/O [4mA]
OUT [4mA]
Peripheral Chip Select Output (Active LOW)
This pin indicates to the system that a bus cycle is in progress to
address 0xA00 of the peripheral space.
It can also be used as PIO[3].
PIO2(1)
PCS[6]#
K2
I/O [4mA]
OUT [4mA]
Peripheral Chip Select Output (Active LOW)
This pin indicates to the system that a bus cycle is in progress to
address 0xC00 of the peripheral space.
It can also be used as PIO[2].
UCSIN#
U5
IN
Upper Memory Chip Select Input (Active LOW)
This pin should ALWAYS be connected to UCSOUT#, except when
an additional external memory (NV-SRAM, Flash) is used (e.g. see
chapter 11.3).
UCSOUT#
U6
OUT [4mA]
Upper Memory Chip Select Output (Active LOW)
This pin should always be connected to UCSIN#, except when an
additional external memory (NV-SRAM, Flash) is used (e.g. see
chapter 11.3).
FLSSEL
J3
OUT [4mA]
Flash Select
This pin is for selecting external memory. If this pin is high, the
internal flash is selected. When low, external memory can be
accessed
(E.g. see chapter 11.3).
Table 4-2: Pin Description of Chip Selects
Note 1: 5V tolerant

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 14
4.4 DMA
Ball Pin
Name
Ball
Pin
Type
Description
PIO12(1)
DRQ0(1)
C7
I/O [4mA]
IN
Direct Memory Request 0 (Schmitt Input with Pull-up)
This pin can be used with DMA channel 0 as DRQ0.
It can also be used as PIO[12].
PIO29(1)
DRQ1(1)
A6
I/O [4mA]
IN
Direct Memory Request 1 (Schmitt Input with Pull-up)
This pin can be used with DMA request 1 as DRQ1.
It can also be used as PIO[29].
PIO7(1)
DRQ2(1)
B6
I/O [4mA]
IN
Direct Memory Request 2 (Schmitt Input with Pull-up)
This pin can be used with DMA channel 2 as DRQ2.
It can also be used as PIO[7].
PIO8(1)
DRQ3(1)
A4
I/O [4mA]
IN
Direct Memory Request 3 (Schmitt Input with Pull-up)
This pin can be used with DMA channel 3 as DRQ3.
It can also be used as PIO[8].
Table 4-3: Pin Description of DMA Request Pins
4.5 Interrupts
Ball Pin
Name
Ball
Pin
Type
Description
PIO9(1)
PFI(1)
E1
I/O [4mA]
IN
Power-fail Interrupt (Schmitt Trigger Input, Active HIGH with Pull-
up)
This pin can be used as a power fail interrupt.
PFI is a non-maskable interrupt (NMI). It can be used to save non-
volatile data to the internal flash or external memory devices (see
chapter 6.7).
It can also be used as PIO[9].
INT3(1)
INT1(1)
C4
B5
IN
IN
Interrupt In (Schmitt Trigger Input, Active HIGH with Pull-down)
These pins are external interrupt input requests.
Note: INT3 is shared with the USB controller and INT1 is shared
with the MAC 1 controller.
PIO30(1)
INT5#(1)
A3
I/O [4mA]
IN
Interrupt In (Schmitt Input with Pull-up, Active LOW)
This pin can be used as INT5. Note: This interrupt is shared with
UART 3.
It can also be used as PIO[30].
Table 4-4: Pin Description of Interrupts
4.6 UART0 Interface
Ball Pin
Name
Ball
Pin
Type
Description
TXD0(1)
A8
OUT [2mA]
Transmit Data 0 Out
This pin provides serial Transmit Data to the system from serial
port 0.
RXD0(1)
C8
IN
Receive Data 0 In (Schmitt Trigger Input, Active HIGH with Pull-up)
This pin provides serial Receive Data from the system to serial
port 0.
RTS0#(1)
A7
OUT [2mA]
Ready to Send 0 Out
This pin provides the Ready to Send output for serial port 0. This pin
provides the handshaking output for serial port 0.
CTS0#(1)
B7
IN
Clear to Send 0 In (Schmitt Trigger Input, Active High with Pull up)
This pin provides the Clear to Send input for serial port 0. This pin
provides the handshaking input for serial port 0.
Table 4-5: Pin Description of UART0
Note 1: 5V tolerant

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 15
4.7 UART1 Interface
Ball Pin
Name
Ball
Pin
Type
Description
TXD1(1)
B10
OUT [2mA]
Transmit Data 1 Out
This pin provides serial Transmit data to the system from serial port 1.
RXD1(1)
C9
IN
Receive Data 1 In (Schmitt Trigger Input, Active HIGH with Pull-up)
This pin provides serial Receive Data from the system to serial port 1.
RTS1#(1)
A9
OUT [2mA]
Ready to send 1 Out
This pin provides the Ready to Send output for serial port 1. It
provides the handshaking output for serial port 1.
CTS1#(1)
B8
IN
Clear to Send 1 In (Schmitt Trigger Input, Active HIGH with Pull-up)
This pin provides the Clear to Send input for serial port 1. It provides
the handshaking input for serial port 1.
Table 4-6: Pin Description of UART1
4.8 UART2 Interface
Ball Pin
Name
Ball
Pin
Type
Description
PIO22(1)
TXD2
A11
I/O [4mA]
OUT [4mA]
Transmit Data 2 Out (Schmitt Input with Pull-up)
This pin can be used with UART 2 as Transmit Data (TXD2).
It can also be used as PIO[22].
PIO23(1)
RXD2(1)
C10
I/O [4mA]
IN
Receive Data 2 In (Schmitt Input with Pull-up)
This pin can be used with UART 2 as Receive Data (RXD2).
It can also be used as PIO[23].
PIO20(1)
RTS2#
A10
I/O [4mA]
OUT [4mA]
Ready to send 2 Out (Schmitt Input with Pull-up)
This pin can be used with UART 2 as Ready to Send (RTS2#).
It can also be used as PIO[20].
PIO21(1)
CTS2#(1)
B9
I/O [4mA]
IN
Clear to Send 2 In (Schmitt Input with Pull-up)
This pin can be used with UART 2 as Clear to Send (CTS2#).
It can also be used as PIO[21].
Table 4-7: Pin Description of UART2

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 16
4.9 I²C Bus
Ball Pin
Name
Ball
Pin
Type
Description
PIO31(1)
I2CCLK(1)
D16
I/O [4mA]
I/O [4mA]
I²C bus Clock (Schmitt Input with Pull-up)
This pin can be used with the I²C block as the I2CLK.
It can also be used as PIO[31].
PIO13(1)
I2CDTA(1)
D15
I/O [4mA]
I/O [4mA]
I²C bus Data (Schmitt Input with Pull-up)
This pin can be used with the I²C block as the I2CDTA.
It can also be used as PIO[13].
Table 4-8: Pin Description of I²C Bus
4.10 Pure PIOs
Ball Pin
Name
Ball
Pin
Type
Description
PIO16(1)
J2
I/O [4mA]
Programmable Input/Output
PIO bit [16] must be programmed for PIO operation.
PIO17(1)
D3
I/O [4mA]
Programmable Input/Output
PIO bit [17] must be programmed for PIO operation.
PIO24(1)
L3
I/O [4mA]
Programmable Input/Output
PIO bit [24] must be programmed for PIO operation.
PIO26(1)
T6
I/O [4mA]
Programmable Input/Output
PIO bit [26] must be programmed for PIO operation.
Table 4-9: Pin Description of Pure PIO pins
Note 1: 5V tolerant

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 17
4.11 SPI Bus / UART3
Ball Pin
Name
Ball
Pin
Type
Description
PIO28(1)
RXD3(1)
SDI(1)
B11
I/O [4mA]
IN
IN
Serial Data In / Receive Data 3 In (Schmitt Input with Pull-up)
This pin can be used with:
The SPI controller. This pin connects to the serial data in of the
SPI controller,
UART 3 as Receive Data (RXD3),
PIO[28].
PIO27(1)
TXD3
SDO
A12
I/O [4mA]
OUT [4mA]
OUT [4mA]
Serial Data Out / Transmit Data 3 Out (Schmitt Input with Pull-up)
This pin can be used with:
The SPI controller. This pin connects to the serial data out of the
SPI controller,
UART 3 as Transmit Data (TXD3),
PIO[27].
PIO19(1)
RTS3#
SCK(1)
B12
I/O [4mA]
OUT [4mA]
I/O [4mA]
Serial Clock / Ready to send 3 Out (Schmitt Input with Pull-up)
This pin can be used with:
The SPI controller. This pin connects to the serial clock (SCK) of
the SPI controller,
UART 3 as Ready to Send (RTS3#),
PIO[19].
PIO18(1)
CTS3#(1)
SLVSEL#(1)
C11
I/O [4mA]
IN
IN
Slave Select / Clear to Send 3 In (Schmitt Input with Pull-up)
This pin can also be used with:
The SPI controller. This pin connects to the slave select input
(SLVSEL#) of the SPI controller,
UART 3 as Clear to Send (CTS3#),
PIO[18].
Table 4-10: Pin Description of SPI Bus / UART3
4.12 Timers
Ball Pin
Name
Ball
Pin
Type
Description
PIO11(1)
TMR0IN(1)
A2
I/O [4mA]
IN
Timer In 0 (Schmitt Input with Pull-up)
This pin can be used with Timer Channel 0 as TMR0IN.
It can also be used as PIO[11].
PIO0(1)
TMR1IN(1)
C2
I/O [4mA]
IN
Timer In 1 (Schmitt Input with Pull-up)
This pin can be used with Timer Channel 1 as TMR1IN.
It can also be used as PIO[0].
PIO10(1)
TMR0OUT
A5
I/O [4mA]
OUT [4mA]
Timer Out 0 (Schmitt Input with Pull-up)
This pin can be used with Timer Channel 0 as TMR0OUT.
It can also be used as PIO[10].
PIO1(1)
TMR1OUT
B4
I/O [4mA]
OUT [4mA]
Timer Out 1 (Schmitt Input with Pull-up)
This pin can be used with Timer Channel 1 as TMR1OUT.
It can also be used as PIO[1].
Table 4-11: Pin Description of Timers
Note 1: 5V tolerant

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 18
4.13 CAN Bus Interface
Ball Pin
Name
Ball
Pin
Type
Description
PIO15(1)
CAN1RXD(1)
G2
I/O [4mA]
IN
CAN Receiver 1 (Schmitt Input with Pull-up)
This pin can be used as CAN controller 1 Receive.
It can also be used as PIO[15].
PIO14(1)
CAN1TXD
G1
I/O [4mA]
OUT [4mA]
CAN Transmit 1 (Schmitt Input with Pull-up)
This pin can be used as CAN controller 1 Transmit.
It can also be used as PIO[14].
CAN0RXD(1)
F16
IN
CAN Receiver 0 (Schmitt Input with Pull-up)
This pin can be used as CAN controller 0 Receive.
CAN0TXD(1)
E16
OUT [2mA]
CAN Transmit 0
This pin can be used as CAN controller 0 Transmit
Table 4-12: Pin Description of CAN Bus
4.14 USB Interface
Ball Pin
Name
Ball
Pin
Type
Description
USBP
N2
I/O
USB 1.1 Plus
USB Transceiver Positive Signal
USBN
N1
I/O
USB 1.1 Negative
USB Transceiver Negative Signal
Table 4-13: Pin Description of USB
4.15 JTAG Interface
Ball Pin
Name
Ball
Pin
Type
Description
TCK(1)
P16
IN
Test Clock (Schmitt Trigger Input and Pull-up)
TDI(1)
N17
IN
Test Data Input (Schmitt Trigger Input and Pull-up)
TDO(1)
P17
OUT [4mA]
Test Data Output
TMS(1)
M15
IN
Test Mode Select (Schmitt Trigger Input and Pull-up)
TRST#(1)
R17
IN
Test Reset (Schmitt Trigger Input and Pull-up)
BSCEN(1)
M16
IN
TEST TAP Select (Schmitt Trigger Input and Pull-up)
This pin can be pulled LOW to enable internal JTAG debugger.
Pull HIGH or left open, to enable the internal boundary scan tap
control.
TEST#(1)
N16
IN
TEST pin (Schmitt Trigger Input and Pull-up)
When this pin is pulled LOW, internal test modes may be input using
address line 1 to 7. When HIGH, test is disabled.
Table 4-14: Pin Description of JTAG
Note 1: 5V tolerant

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 19
4.16 Ethernet 0 Interface (Internal PHY)
Ball Pin
Name
Ball
Pin
Type
Description
XIN(1)
XOUT
H1
H2
IN
OUT
Ethernet Clock (25 MHz Crystal)
These pins provide the connections for a fundamental mode parallel
resonant crystal.
LED0(1)
K17
OUT [8mA]
LED0 Driver
LED1(1)
J17
OUT [8mA]
LED1 Driver
LED2(1)
L17
OUT [8mA]
LED2 Driver
LED3(1)
G15
OUT [8mA]
LED3 Driver
TXP
D17
OUT
Ethernet Transmit Plus
TXN
E17
OUT
Ethernet Transmit Negative
RXP
G17
IN
Ethernet Receive Plus
RXN
F17
IN
Ethernet Receive Negative
Table 4-15: Pin Description of internal PHY
4.17 MII Ethernet 1 Interface (External PHY)
Ball Pin
Name
Ball
Pin
Type
Description
MDIO(1)
A17
I/O [4mA]
Ethernet MII 1 Management Data
MDC(1)
B17
OUT [4mA]
Ethernet MII 1 Clock Out
TXCLK(1)
C16
IN
Ethernet Transmit Clock
TXEN(1)
P15
OUT [4mA]
Ethernet Transmit Enable
TXER(1)
C17
OUT [4mA]
Ethernet Transmit Error
TXD[3](1)
B16
OUT [4mA]
Ethernet Transmit Data Bus Bit [3]
TXD[2](1)
A16
OUT [4mA]
Ethernet Transmit Data Bus Bit [2]
TXD[1](1)
B15
OUT [4mA]
Ethernet Transmit Data Bus Bit [1]
TXD[0](1)
A15
OUT [4mA]
Ethernet Transmit Data Bus Bit [0]
RXCLK(1)
E2
IN
Ethernet Receive Clock
RXDV(1)
C1
IN
Ethernet Receive Data Valid
RXER(1)
D2
IN
Ethernet Receive Error
RXD[3](1)
C14
IN
Ethernet Receive Data Bus Bit [3]
RXD[2](1)
B14
IN
Ethernet Receive Data Bus Bit [2]
RXD[1](1)
B13
IN
Ethernet Receive Data Bus Bit [1]
RXD[0](1)
A14
IN
Ethernet Receive Data Bus Bit [0]
RXCRS(1)
A13
IN
Ethernet Receive Carrier Sense
RXCOL(1)
C12
IN
Ethernet Receive Collision
Table 4-16: Pin Description of MII
Note 1: 5V tolerant

IPC@CHIP SC123/SC143
Hardware Manual V1.06 [18.02.2010]
©2000-2008 BECK IPC GmbH Page 20
4.18 PHY Power (Internal PHY)
Ball Pin
Name
Ball
Pin
Type
Description
VDD1A
J16
PWR
Power I/O: +3.3 volt power supply
(requires a separate via to power plane)
VDD2A
J15
PWR
Power I/O: +3.3 volt power supply
(requires a separate via to power plane)
VSS3A
K15
PWR
Power VSS
(requires a separate via to power plane)
VSS4A
H15
PWR
Power VSS
(requires a separate via to power plane)
Table 4-17: Pin Description of PHY Power Pins
4.19 Power
Ball Pin
Name
Ball
Pin
Type
Description
VSS
E15
PWR
Power VSS
VSS
N15
PWR
Power VSS
VSS
C13
PWR
Power VSS
VSS
R13
PWR
Power VSS
VSS
C6
PWR
Power VSS
VSS
R5
PWR
Power VSS
VSS
F3
PWR
Power VSS
VSS
N3
PWR
Power VSS
VSS
A1
PWR
Power VSS
VSS
H10
PWR
Power VSS (Thermal Ball)
VSS
J10
PWR
Power VSS (Thermal Ball)
VSS
K10
PWR
Power VSS (Thermal Ball)
VSS
H9
PWR
Power VSS (Thermal Ball)
VSS
J9
PWR
Power VSS (Thermal Ball)
VSS
K9
PWR
Power VSS (Thermal Ball)
VSS
H8
PWR
Power VSS (Thermal Ball)
VSS
J8
PWR
Power VSS (Thermal Ball)
VSS
K8
PWR
Power VSS (Thermal Ball)
VDD
C15
PWR
Power I/O: +3.3 volt power supply
VDD
R15
PWR
Power I/O: +3.3 volt power supply
VDD
C5
PWR
Power I/O: +3.3 volt power supply
VDD
C3
PWR
Power I/O: +3.3 volt power supply
VDD
E3
PWR
Power I/O: +3.3 volt power supply
VDD
R3
PWR
Power I/O: +3.3 volt power supply
Table 4-18: Pin Description of Power Pins