GigaDevice Semiconductor GD32C10 Series User manual

GigaDevice Semiconductor Inc.
GD32C10x
Arm® Cortex®-M4 32-bit MCU
User Manual
Revision 1.3
( Dec. 2022 )

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Table of Contents
Table of Contents ...........................................................................................................2
List of Figures ..............................................................................................................15
List of Tables ................................................................................................................21
1. System and memory architecture ........................................................................23
1.1. ARM Cortex-M4 processor........................................................................................ 23
1.2. System architecture .................................................................................................. 24
1.3. Memory map .............................................................................................................. 26
1.3.1. Bit-banding............................................................................................................................ 30
1.3.2. On-chip SRAM memory........................................................................................................ 31
1.3.3. On-chip flash memory overview ........................................................................................... 31
1.4. Device electronic signature...................................................................................... 32
1.4.1. Memory density information.................................................................................................. 33
1.4.2. Unique device ID (96 bits) .................................................................................................... 33
1.5. System configuration registers................................................................................ 34
2. Flash memory controller (FMC)............................................................................35
2.1. Overview .................................................................................................................... 35
2.2. Characteristics........................................................................................................... 35
2.3. Function overview..................................................................................................... 35
2.3.1. Flash memory architecture ................................................................................................... 35
2.3.2. Read operations ................................................................................................................... 36
2.3.3. Unlock the FMC_CTL register .............................................................................................. 37
2.3.4. Page erase............................................................................................................................ 38
2.3.5. Mass erase ........................................................................................................................... 39
2.3.6. Main flash programming ....................................................................................................... 40
2.3.7. OTP programming ................................................................................................................ 42
2.3.8. Option bytes Erase ............................................................................................................... 43
2.3.9. Option bytes modify .............................................................................................................. 43
2.3.10. Option bytes description ....................................................................................................... 44
2.3.11. Page erase/program protection ............................................................................................ 45
2.3.12. Security protection ................................................................................................................ 45
2.4. Register definition..................................................................................................... 46
2.4.1. Wait state register (FMC_WS).............................................................................................. 46
2.4.2. Unlock key register (FMC_KEY)........................................................................................... 47
2.4.3. Option byte unlock key register (FMC_OBKEY)................................................................... 47
2.4.4. Status register (FMC_STAT)................................................................................................. 48

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2.4.5. Control register (FMC_CTL) ................................................................................................. 48
2.4.6. Address register (FMC_ADDR) ............................................................................................ 50
2.4.7. Option byte status register (FMC_OBSTAT)......................................................................... 50
2.4.8. Erase/Program protection register (FMC_WP)..................................................................... 51
2.4.9. Product ID register (FMC_PID)............................................................................................. 51
3. Power management unit (PMU) ............................................................................53
3.1. Overview .................................................................................................................... 53
3.2. Characteristics........................................................................................................... 53
3.3. Function overview..................................................................................................... 53
3.3.1. Backup domain ..................................................................................................................... 54
3.3.2. VDD / VDDA power domain ...................................................................................................... 55
3.3.3. 1.2V power domain............................................................................................................... 57
3.3.4. Power saving modes ............................................................................................................ 57
3.4. Register definition..................................................................................................... 60
3.4.1. Control register (PMU_CTL) ................................................................................................. 60
3.4.2. Control and status register (PMU_CS) ................................................................................. 61
4. Backup registers (BKP).........................................................................................63
4.1. Overview .................................................................................................................... 63
4.2. Characteristics........................................................................................................... 63
4.3. Function overview ..................................................................................................... 63
4.3.1. RTC clock calibration ............................................................................................................ 63
4.3.2. Tamper detection .................................................................................................................. 63
4.4. Register definition..................................................................................................... 65
4.4.1. Backup data register x (BKP_DATAx) (x= 0..41) .................................................................. 65
4.4.2. RTC signal output control register (BKP_OCTL).................................................................. 65
4.4.3. Tamper pin control register (BKP_TPCTL) ........................................................................... 66
4.4.4. Tamper control and status register (BKP_TPCS) ................................................................. 67
5. Reset and clock unit (RCU)...................................................................................68
5.1. Reset control unit (RCTL) ......................................................................................... 68
5.1.1. Overview ............................................................................................................................... 68
5.1.2. Function overview ................................................................................................................. 68
5.2. Clock control unit (CCTL) ......................................................................................... 69
5.2.1. Overview ............................................................................................................................... 69
5.2.2. Characteristics ...................................................................................................................... 71
5.2.3. Function overview ................................................................................................................. 71
5.3. Register definition..................................................................................................... 76
5.3.1. Control register (RCU_CTL) ................................................................................................. 76
5.3.2. Clock configuration register 0 (RCU_CFG0) ........................................................................ 78

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5.3.3. Clock interrupt register (RCU_INT) ...................................................................................... 81
5.3.4. APB2 reset register (RCU_APB2RST) ................................................................................. 85
5.3.5. APB1 reset register (RCU_APB1RST) ................................................................................. 87
5.3.6. AHB enable register (RCU_AHBEN) .................................................................................... 90
5.3.7. APB2 enable register (RCU_APB2EN) ................................................................................ 91
5.3.8. APB1 enable register (RCU_APB1EN) ................................................................................ 93
5.3.9. Backup domain control register (RCU_BDCTL) ................................................................... 96
5.3.10. Reset source/clock register (RCU_RSTSCK) ...................................................................... 97
5.3.11. AHB reset register (RCU_AHBRST)..................................................................................... 99
5.3.12. Clock configuration register 1 (RCU_CFG1) ........................................................................ 99
5.3.13. Deep-sleep mode voltage register (RCU_DSV) ................................................................. 102
5.3.14. Additional clock control register (RCU_ADDCTL) .............................................................. 102
5.3.15. Additional clock interrupt register (RCU_ADDINT)............................................................. 103
5.3.16. APB1 additional reset register (RCU_ADDAPB1RST)....................................................... 104
5.3.17. APB1 additional enable register (RCU_ADDAPB1EN) ...................................................... 105
6. Clock trim controller (CTC) .................................................................................106
6.1. Overview .................................................................................................................. 106
6.2. Characteristics......................................................................................................... 106
6.3. Function overview................................................................................................... 106
6.3.1. Reference sync pulse generator......................................................................................... 107
6.3.2. CTC trim counter................................................................................................................. 107
6.3.3. Frequency evaluation and automatic trim process ............................................................. 108
6.3.4. Software program guide ..................................................................................................... 109
6.4. Register definition....................................................................................................111
6.4.1. Control register 0 (CTC_CTL0)............................................................................................111
6.4.2. Control register 1 (CTC_CTL1)............................................................................................112
6.4.3. Status register (CTC_STAT) ................................................................................................113
6.4.4. Interrupt clear register (CTC_INTC) ....................................................................................115
7. Interrupt / event controller (EXTI)....................................................................... 117
7.1. Overview ...................................................................................................................117
7.2. Characteristics..........................................................................................................117
7.3. Function overview....................................................................................................117
7.4. External interrupt and event block diagram .......................................................... 121
7.5. External interrupt and event function overview .................................................... 121
7.6. Register definition................................................................................................... 123
7.6.1. Interrupt enable register (EXTI_INTEN) ............................................................................. 123
7.6.2. Event enable register (EXTI_EVEN) .................................................................................. 123
7.6.3. Rising edge trigger enable register (EXTI_RTEN) ............................................................. 124
7.6.4. Falling edge trigger enable register (EXTI_FTEN) ............................................................. 124

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7.6.5. Software interrupt event register (EXTI_SWIEV) ............................................................... 124
7.6.6. Pending register (EXTI_PD) ............................................................................................... 125
8. General-purpose and alternate-function I/Os (GPIO and AFIO).......................126
8.1. Overview .................................................................................................................. 126
8.2. Characteristics......................................................................................................... 126
8.3. Function overview................................................................................................... 126
8.3.1. GPIO pin configuration ....................................................................................................... 127
8.3.2. External interrupt/event lines .............................................................................................. 128
8.3.3. Alternate functions (AF) ...................................................................................................... 128
8.3.4. Input configuration .............................................................................................................. 128
8.3.5. Output configuration ........................................................................................................... 129
8.3.6. Analog configuration ........................................................................................................... 129
8.3.7. Alternate function (AF) configuration .................................................................................. 130
8.3.8. GPIO locking function ......................................................................................................... 130
8.3.9. GPIO I/O compensation cell ............................................................................................... 131
8.4. Remapping function I/O and debug configuration................................................ 131
8.4.1. Overview ............................................................................................................................. 131
8.4.2. Characteristics .................................................................................................................... 131
8.4.3. JTAG/SWD alternate function remapping........................................................................... 131
8.4.4. ADC AF remapping............................................................................................................. 132
8.4.5. TIMER AF remapping ......................................................................................................... 133
8.4.6. USART AF remapping ........................................................................................................ 134
8.4.7. I2C0 AF remapping ............................................................................................................. 135
8.4.8. SPI0/SPI2/I2S AF remapping ............................................................................................. 135
8.4.9. CAN0/1 AF remapping........................................................................................................ 136
8.4.10. CTC AF remapping ............................................................................................................. 136
8.4.11. CLK pins AF remapping ...................................................................................................... 136
8.5. Register definition................................................................................................... 138
8.5.1. Port control register 0 (GPIOx_CTL0, x=A..E) ................................................................... 138
8.5.2. Port control register 1 (GPIOx_CTL1, x=A..E) ................................................................... 140
8.5.3. Port input status register (GPIOx_ISTAT, x=A..E) .............................................................. 141
8.5.4. Port output control register (GPIOx_OCTL, x=A..E)........................................................... 142
8.5.5. Port bit operate register (GPIOx_BOP, x=A..E) .................................................................. 142
8.5.6. Port bit clear register (GPIOx_BC, x=A..E)......................................................................... 143
8.5.7. Port configuration lock register (GPIOx_LOCK, x=A..E) .................................................... 143
8.5.8. Port bit speed register (GPIOx_SPD, x=A..E) .................................................................... 144
8.5.9. Event control register (AFIO_EC) ....................................................................................... 144
8.5.10. AFIO port configuration register 0 (AFIO_PCF0) ............................................................... 145
8.5.11. EXTI sources selection register 0 (AFIO_EXTISS0) .......................................................... 149
8.5.12. EXTI sources selection register 1 (AFIO_EXTISS1) .......................................................... 150
8.5.13. EXTI sources selection register 2 (AFIO_EXTISS2) .......................................................... 151
8.5.14. EXTI sources selection register 3 (AFIO_EXTISS3) .......................................................... 152

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8.5.15. AFIO port configuration register 1 (AFIO_PCF1) ............................................................... 153
8.5.16. IO compensation control register (AFIO_CPSCTL)............................................................ 154
9. CRC calculation unit (CRC).................................................................................155
9.1. Overview .................................................................................................................. 155
9.2. Characteristics......................................................................................................... 155
9.3. Function overview................................................................................................... 156
9.4. Register definition................................................................................................... 157
9.4.1. Data register (CRC_DATA) ................................................................................................. 157
9.4.2. Free data register (CRC_FDATA) ....................................................................................... 157
9.4.3. Control register (CRC_CTL) ............................................................................................... 158
10. Direct memory access controller (DMA).........................................................159
10.1. Overview............................................................................................................... 159
10.2. Characteristics..................................................................................................... 159
10.3. Block diagram ...................................................................................................... 160
10.4. Function overview................................................................................................ 160
10.4.1. DMA operation .................................................................................................................... 160
10.4.2. Peripheral handshake......................................................................................................... 162
10.4.3. Arbitration............................................................................................................................ 162
10.4.4. Address generation............................................................................................................. 162
10.4.5. Circular mode...................................................................................................................... 163
10.4.6. Memory to memory mode................................................................................................... 163
10.4.7. Channel configuration......................................................................................................... 163
10.4.8. Interrupt............................................................................................................................... 163
10.4.9. DMA request mapping ........................................................................................................ 164
10.5. Register definition................................................................................................ 168
10.5.1. Interrupt flag register (DMA_INTF) ..................................................................................... 168
10.5.2. Interrupt flag clear register (DMA_INTC) ............................................................................ 169
10.5.3. Channel x control register (DMA_CHxCTL) ....................................................................... 169
10.5.4. Channel x counter register (DMA_CHxCNT)...................................................................... 171
10.5.5. Channel x peripheral base address register (DMA_CHxPADDR) ...................................... 172
10.5.6. Channel x memory base address register (DMA_CHxMADDR) ........................................ 172
11. Debug (DBG) .....................................................................................................174
11.1. Overview............................................................................................................... 174
11.2. JTAG/SW function overview................................................................................ 174
11.2.1. Switch JTAG or SW interface ............................................................................................. 174
11.2.2. Pin assignment ................................................................................................................... 174
11.2.3. JTAG daisy chained structure............................................................................................. 175
11.2.4. Debug reset ........................................................................................................................ 175

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11.2.5. JEDEC-106 ID code ........................................................................................................... 175
11.3. Debug hold function overview ............................................................................ 175
11.3.1. Debug support for power saving mode............................................................................... 175
11.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN ............................................ 176
11.4. Register definition................................................................................................ 177
11.4.1. ID code register (DBG_ID).................................................................................................. 177
11.4.2. Control register (DBG_CTL) ............................................................................................... 177
12. Analog-to-digital converter (ADC)...................................................................181
12.1. Overview............................................................................................................... 181
12.2. Characteristics..................................................................................................... 181
12.3. Pins and internal signals..................................................................................... 182
12.4. Function overview................................................................................................ 183
12.4.1. Foreground calibration function .......................................................................................... 183
12.4.2. ADC clock ........................................................................................................................... 184
12.4.3. ADCON enable ................................................................................................................... 184
12.4.4. Routine sequence............................................................................................................... 184
12.4.5. Operation modes ................................................................................................................ 184
12.4.6. Conversion result threshold monitor function ..................................................................... 187
12.4.7. Data storage mode ............................................................................................................. 187
12.4.8. Sample time configuration .................................................................................................. 188
12.4.9. External trigger configuration.............................................................................................. 188
12.4.10. DMA request ................................................................................................................... 189
12.4.11. ADC internal channels.................................................................................................... 189
12.4.12. Programmable resolution (DRES) .................................................................................. 190
12.4.13. On-chip hardware oversampling ..................................................................................... 190
12.5. ADC sync mode.................................................................................................... 192
12.5.1. Free mode........................................................................................................................... 193
12.5.2. Routine parallel mode......................................................................................................... 193
12.5.3. Routine follow-up fast mode ............................................................................................... 194
12.5.4. Routine follow-up slow mode.............................................................................................. 194
12.6. ADC interrupts...................................................................................................... 195
12.7. Register definition................................................................................................ 196
12.7.1. Status register (ADC_STAT) ............................................................................................... 196
12.7.2. Control register 0 (ADC_CTL0) .......................................................................................... 196
12.7.3. Control register 1 (ADC_CTL1) .......................................................................................... 198
12.7.4. Sample time register 0 (ADC_SAMPT0) ............................................................................ 200
12.7.5. Sample time register 1 (ADC_SAMPT1) ............................................................................ 201
12.7.6. Watchdog high threshold register (ADC_WDHT) ............................................................... 202
12.7.7. Watchdog low threshold register (ADC_WDLT) ................................................................. 202
12.7.8. Routine sequence register 0 (ADC_RSQ0)........................................................................ 202

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12.7.9. Routine sequence register 1 (ADC_RSQ1)........................................................................ 203
12.7.10. Routine sequence register 2 (ADC_RSQ2) .................................................................... 204
12.7.11. Routine data register (ADC_RDATA).............................................................................. 204
12.7.12. Oversample control register (ADC_OVSAMPCTL) ........................................................ 205
13. Digital-to-analog converter (DAC) ...................................................................207
13.1. Overview............................................................................................................... 207
13.2. Characteristics..................................................................................................... 207
13.3. Function overview................................................................................................ 208
13.3.1. DAC enable......................................................................................................................... 208
13.3.2. DAC output buffer ............................................................................................................... 208
13.3.3. DAC data configuration....................................................................................................... 209
13.3.4. DAC trigger ......................................................................................................................... 209
13.3.5. DAC workflow ..................................................................................................................... 209
13.3.6. DAC noise wave ................................................................................................................. 209
13.3.7. DAC output calculate .......................................................................................................... 210
13.3.8. DMA function........................................................................................................................211
13.3.9. DAC concurrent conversion.................................................................................................211
13.4. Register definition................................................................................................ 212
13.4.1. Control register (DAC_CTL) ............................................................................................... 212
13.4.2. Software trigger register (DAC_SWT) ................................................................................ 214
13.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH)....................................... 215
13.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH) ......................................... 215
13.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH)........................................... 216
13.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH)....................................... 216
13.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) ......................................... 217
13.4.8. DAC1 8-bit right-aligned data holding register (DAC1_R8DH)........................................... 217
13.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) ............ 217
13.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH) ........... 218
13.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) ............ 219
13.4.12. DAC0 data output register (DAC0_DO) .......................................................................... 219
13.4.13. DAC1 data output register (DAC1_DO) .......................................................................... 219
14. Watchdog timer (WDGT) ..................................................................................221
14.1. Free watchdog timer (FWDGT)............................................................................ 221
14.1.1. Overview ............................................................................................................................. 221
14.1.2. Characteristics .................................................................................................................... 221
14.1.3. Function overview ............................................................................................................... 221
14.1.4. Register definition ............................................................................................................... 224
14.2. Window watchdog timer (WWDGT)..................................................................... 227
14.2.1. Overview ............................................................................................................................. 227
14.2.2. Characteristics .................................................................................................................... 227
14.2.3. Function overview ............................................................................................................... 227

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14.2.4. Register definition ............................................................................................................... 230
15. Real-time Clock (RTC) ......................................................................................232
15.1. Overview............................................................................................................... 232
15.2. Characteristics..................................................................................................... 232
15.3. Function overview................................................................................................ 232
15.3.1. RTC reset............................................................................................................................ 233
15.3.2. RTC reading........................................................................................................................ 233
15.3.3. RTC configuration ............................................................................................................... 233
15.3.4. RTC flag assertion .............................................................................................................. 234
15.4. Register definition................................................................................................ 236
15.4.1. RTC interrupt enable register(RTC_INTEN)....................................................................... 236
15.4.2. RTC control register(RTC_CTL) ......................................................................................... 236
15.4.3. RTC prescaler high register (RTC_PSCH) ......................................................................... 237
15.4.4. RTC prescaler low register(RTC_PSCL) ............................................................................ 237
15.4.5. RTC divider high register (RTC_DIVH)............................................................................... 238
15.4.6. RTC divider low register (RTC_DIVL)................................................................................. 238
15.4.7. RTC counter high register(RTC_CNTH)............................................................................. 238
15.4.8. RTC counter low register (RTC_CNTL).............................................................................. 239
15.4.9. RTC alarm high register(RTC_ALRMH) ............................................................................. 239
15.4.10. RTC alarm low register (RTC_ALRML) .......................................................................... 239
16. TIMER ................................................................................................................240
16.1. Advanced timer (TIMERx, x=0, 7)........................................................................ 241
16.1.1. Overview ............................................................................................................................. 241
16.1.2. Characteristics .................................................................................................................... 241
16.1.3. Block diagram ..................................................................................................................... 242
16.1.4. Function overview ............................................................................................................... 243
16.1.5. TIMERx registers (x=0, 7)................................................................................................... 269
16.2. General level0 timer (TIMERx, x=1, 2, 3, 4)......................................................... 296
16.2.1. Overview ............................................................................................................................. 296
16.2.2. Characteristics .................................................................................................................... 296
16.2.3. Block diagram ..................................................................................................................... 296
16.2.4. Function overview ............................................................................................................... 297
16.2.5. TIMERx registers(x=1, 2, 3, 4)............................................................................................ 313
16.3. General level1 timer (TIMERx, x=8, 11)............................................................... 335
16.3.1. Overview ............................................................................................................................. 335
16.3.2. Characteristics .................................................................................................................... 335
16.3.3. Block diagram ..................................................................................................................... 335
16.3.4. Function overview ............................................................................................................... 336
16.3.5. TIMERx registers (x=8, 11) ................................................................................................. 348
16.4. General level2 timer (TIMERx, x=9, 10, 12, 13) ................................................... 360

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16.4.1. Overview ............................................................................................................................. 360
16.4.2. Characteristics .................................................................................................................... 361
16.4.3. Block diagram ..................................................................................................................... 361
16.4.4. Function overview ............................................................................................................... 361
16.4.5. TIMERx registers (x=9, 10, 12, 13)..................................................................................... 369
16.5. Basic timer (TIMERx, x=5, 6)................................................................................ 378
16.5.1. Overview ............................................................................................................................. 378
16.5.2. Characteristics .................................................................................................................... 378
16.5.3. Block diagram ..................................................................................................................... 378
16.5.4. Function overview ............................................................................................................... 379
16.5.5. TIMERx registers (x=5, 6)................................................................................................... 383
17. Universal synchronous/asynchronous receiver /transmitter (USART)........388
17.1. Overview............................................................................................................... 388
17.2. Characteristics..................................................................................................... 388
17.3. Function overview................................................................................................ 389
17.3.1. USART frame format .......................................................................................................... 390
17.3.2. Baud rate generation .......................................................................................................... 391
17.3.3. USART transmitter.............................................................................................................. 391
17.3.4. USART receiver .................................................................................................................. 392
17.3.5. Use DMA for data buffer access ......................................................................................... 394
17.3.6. Hardware flow control ......................................................................................................... 395
17.3.7. Multi-processor communication .......................................................................................... 396
17.3.8. LIN mode ............................................................................................................................ 397
17.3.9. Synchronous mode............................................................................................................. 398
17.3.10. IrDA SIR ENDEC mode .................................................................................................. 398
17.3.11. Half-duplex communication mode .................................................................................. 400
17.3.12. Smartcard (ISO7816-3) mode......................................................................................... 400
17.3.13. USART interrupts ............................................................................................................ 402
17.4. Register definition................................................................................................ 404
17.4.1. Status register 0 (USART_STAT0) ..................................................................................... 404
17.4.2. Data register (USART_DATA)............................................................................................. 406
17.4.3. Baud rate register (USART_BAUD).................................................................................... 406
17.4.4. Control register 0 (USART_CTL0)...................................................................................... 407
17.4.5. Control register 1 (USART_CTL1)...................................................................................... 409
17.4.6. Control register 2 (USART_CTL2)...................................................................................... 410
17.4.7. Guard time and prescaler register (USART_GP) ............................................................... 412
17.4.8. Control register 3 (USART_CTL3)...................................................................................... 413
17.4.9. Receiver timeout register (USART_RT) ............................................................................. 414
17.4.10. Status register 1 (USART_STAT1) ................................................................................. 415
17.4.11. Coherence control register (USART_CHC) .................................................................... 416
18. Inter-integrated circuit interface (I2C).............................................................417