GigaDevice Semiconductor GD32C10 Series User manual

GigaDevice Semiconductor Inc.
GD32C10x
Arm® Cortex®-M4 32-bit MCU
User Manual
Revision 1.3
( Dec. 2022 )

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Table of Contents
Table of Contents ...........................................................................................................2
List of Figures ..............................................................................................................15
List of Tables ................................................................................................................21
1. System and memory architecture ........................................................................23
1.1. ARM Cortex-M4 processor........................................................................................ 23
1.2. System architecture .................................................................................................. 24
1.3. Memory map .............................................................................................................. 26
1.3.1. Bit-banding............................................................................................................................ 30
1.3.2. On-chip SRAM memory........................................................................................................ 31
1.3.3. On-chip flash memory overview ........................................................................................... 31
1.4. Device electronic signature...................................................................................... 32
1.4.1. Memory density information.................................................................................................. 33
1.4.2. Unique device ID (96 bits) .................................................................................................... 33
1.5. System configuration registers................................................................................ 34
2. Flash memory controller (FMC)............................................................................35
2.1. Overview .................................................................................................................... 35
2.2. Characteristics........................................................................................................... 35
2.3. Function overview..................................................................................................... 35
2.3.1. Flash memory architecture ................................................................................................... 35
2.3.2. Read operations ................................................................................................................... 36
2.3.3. Unlock the FMC_CTL register .............................................................................................. 37
2.3.4. Page erase............................................................................................................................ 38
2.3.5. Mass erase ........................................................................................................................... 39
2.3.6. Main flash programming ....................................................................................................... 40
2.3.7. OTP programming ................................................................................................................ 42
2.3.8. Option bytes Erase ............................................................................................................... 43
2.3.9. Option bytes modify .............................................................................................................. 43
2.3.10. Option bytes description ....................................................................................................... 44
2.3.11. Page erase/program protection ............................................................................................ 45
2.3.12. Security protection ................................................................................................................ 45
2.4. Register definition..................................................................................................... 46
2.4.1. Wait state register (FMC_WS).............................................................................................. 46
2.4.2. Unlock key register (FMC_KEY)........................................................................................... 47
2.4.3. Option byte unlock key register (FMC_OBKEY)................................................................... 47
2.4.4. Status register (FMC_STAT)................................................................................................. 48

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2.4.5. Control register (FMC_CTL) ................................................................................................. 48
2.4.6. Address register (FMC_ADDR) ............................................................................................ 50
2.4.7. Option byte status register (FMC_OBSTAT)......................................................................... 50
2.4.8. Erase/Program protection register (FMC_WP)..................................................................... 51
2.4.9. Product ID register (FMC_PID)............................................................................................. 51
3. Power management unit (PMU) ............................................................................53
3.1. Overview .................................................................................................................... 53
3.2. Characteristics........................................................................................................... 53
3.3. Function overview..................................................................................................... 53
3.3.1. Backup domain ..................................................................................................................... 54
3.3.2. VDD / VDDA power domain ...................................................................................................... 55
3.3.3. 1.2V power domain............................................................................................................... 57
3.3.4. Power saving modes ............................................................................................................ 57
3.4. Register definition..................................................................................................... 60
3.4.1. Control register (PMU_CTL) ................................................................................................. 60
3.4.2. Control and status register (PMU_CS) ................................................................................. 61
4. Backup registers (BKP).........................................................................................63
4.1. Overview .................................................................................................................... 63
4.2. Characteristics........................................................................................................... 63
4.3. Function overview ..................................................................................................... 63
4.3.1. RTC clock calibration ............................................................................................................ 63
4.3.2. Tamper detection .................................................................................................................. 63
4.4. Register definition..................................................................................................... 65
4.4.1. Backup data register x (BKP_DATAx) (x= 0..41) .................................................................. 65
4.4.2. RTC signal output control register (BKP_OCTL).................................................................. 65
4.4.3. Tamper pin control register (BKP_TPCTL) ........................................................................... 66
4.4.4. Tamper control and status register (BKP_TPCS) ................................................................. 67
5. Reset and clock unit (RCU)...................................................................................68
5.1. Reset control unit (RCTL) ......................................................................................... 68
5.1.1. Overview ............................................................................................................................... 68
5.1.2. Function overview ................................................................................................................. 68
5.2. Clock control unit (CCTL) ......................................................................................... 69
5.2.1. Overview ............................................................................................................................... 69
5.2.2. Characteristics ...................................................................................................................... 71
5.2.3. Function overview ................................................................................................................. 71
5.3. Register definition..................................................................................................... 76
5.3.1. Control register (RCU_CTL) ................................................................................................. 76
5.3.2. Clock configuration register 0 (RCU_CFG0) ........................................................................ 78

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5.3.3. Clock interrupt register (RCU_INT) ...................................................................................... 81
5.3.4. APB2 reset register (RCU_APB2RST) ................................................................................. 85
5.3.5. APB1 reset register (RCU_APB1RST) ................................................................................. 87
5.3.6. AHB enable register (RCU_AHBEN) .................................................................................... 90
5.3.7. APB2 enable register (RCU_APB2EN) ................................................................................ 91
5.3.8. APB1 enable register (RCU_APB1EN) ................................................................................ 93
5.3.9. Backup domain control register (RCU_BDCTL) ................................................................... 96
5.3.10. Reset source/clock register (RCU_RSTSCK) ...................................................................... 97
5.3.11. AHB reset register (RCU_AHBRST)..................................................................................... 99
5.3.12. Clock configuration register 1 (RCU_CFG1) ........................................................................ 99
5.3.13. Deep-sleep mode voltage register (RCU_DSV) ................................................................. 102
5.3.14. Additional clock control register (RCU_ADDCTL) .............................................................. 102
5.3.15. Additional clock interrupt register (RCU_ADDINT)............................................................. 103
5.3.16. APB1 additional reset register (RCU_ADDAPB1RST)....................................................... 104
5.3.17. APB1 additional enable register (RCU_ADDAPB1EN) ...................................................... 105
6. Clock trim controller (CTC) .................................................................................106
6.1. Overview .................................................................................................................. 106
6.2. Characteristics......................................................................................................... 106
6.3. Function overview................................................................................................... 106
6.3.1. Reference sync pulse generator......................................................................................... 107
6.3.2. CTC trim counter................................................................................................................. 107
6.3.3. Frequency evaluation and automatic trim process ............................................................. 108
6.3.4. Software program guide ..................................................................................................... 109
6.4. Register definition....................................................................................................111
6.4.1. Control register 0 (CTC_CTL0)............................................................................................111
6.4.2. Control register 1 (CTC_CTL1)............................................................................................112
6.4.3. Status register (CTC_STAT) ................................................................................................113
6.4.4. Interrupt clear register (CTC_INTC) ....................................................................................115
7. Interrupt / event controller (EXTI)....................................................................... 117
7.1. Overview ...................................................................................................................117
7.2. Characteristics..........................................................................................................117
7.3. Function overview....................................................................................................117
7.4. External interrupt and event block diagram .......................................................... 121
7.5. External interrupt and event function overview .................................................... 121
7.6. Register definition................................................................................................... 123
7.6.1. Interrupt enable register (EXTI_INTEN) ............................................................................. 123
7.6.2. Event enable register (EXTI_EVEN) .................................................................................. 123
7.6.3. Rising edge trigger enable register (EXTI_RTEN) ............................................................. 124
7.6.4. Falling edge trigger enable register (EXTI_FTEN) ............................................................. 124

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7.6.5. Software interrupt event register (EXTI_SWIEV) ............................................................... 124
7.6.6. Pending register (EXTI_PD) ............................................................................................... 125
8. General-purpose and alternate-function I/Os (GPIO and AFIO).......................126
8.1. Overview .................................................................................................................. 126
8.2. Characteristics......................................................................................................... 126
8.3. Function overview................................................................................................... 126
8.3.1. GPIO pin configuration ....................................................................................................... 127
8.3.2. External interrupt/event lines .............................................................................................. 128
8.3.3. Alternate functions (AF) ...................................................................................................... 128
8.3.4. Input configuration .............................................................................................................. 128
8.3.5. Output configuration ........................................................................................................... 129
8.3.6. Analog configuration ........................................................................................................... 129
8.3.7. Alternate function (AF) configuration .................................................................................. 130
8.3.8. GPIO locking function ......................................................................................................... 130
8.3.9. GPIO I/O compensation cell ............................................................................................... 131
8.4. Remapping function I/O and debug configuration................................................ 131
8.4.1. Overview ............................................................................................................................. 131
8.4.2. Characteristics .................................................................................................................... 131
8.4.3. JTAG/SWD alternate function remapping........................................................................... 131
8.4.4. ADC AF remapping............................................................................................................. 132
8.4.5. TIMER AF remapping ......................................................................................................... 133
8.4.6. USART AF remapping ........................................................................................................ 134
8.4.7. I2C0 AF remapping ............................................................................................................. 135
8.4.8. SPI0/SPI2/I2S AF remapping ............................................................................................. 135
8.4.9. CAN0/1 AF remapping........................................................................................................ 136
8.4.10. CTC AF remapping ............................................................................................................. 136
8.4.11. CLK pins AF remapping ...................................................................................................... 136
8.5. Register definition................................................................................................... 138
8.5.1. Port control register 0 (GPIOx_CTL0, x=A..E) ................................................................... 138
8.5.2. Port control register 1 (GPIOx_CTL1, x=A..E) ................................................................... 140
8.5.3. Port input status register (GPIOx_ISTAT, x=A..E) .............................................................. 141
8.5.4. Port output control register (GPIOx_OCTL, x=A..E)........................................................... 142
8.5.5. Port bit operate register (GPIOx_BOP, x=A..E) .................................................................. 142
8.5.6. Port bit clear register (GPIOx_BC, x=A..E)......................................................................... 143
8.5.7. Port configuration lock register (GPIOx_LOCK, x=A..E) .................................................... 143
8.5.8. Port bit speed register (GPIOx_SPD, x=A..E) .................................................................... 144
8.5.9. Event control register (AFIO_EC) ....................................................................................... 144
8.5.10. AFIO port configuration register 0 (AFIO_PCF0) ............................................................... 145
8.5.11. EXTI sources selection register 0 (AFIO_EXTISS0) .......................................................... 149
8.5.12. EXTI sources selection register 1 (AFIO_EXTISS1) .......................................................... 150
8.5.13. EXTI sources selection register 2 (AFIO_EXTISS2) .......................................................... 151
8.5.14. EXTI sources selection register 3 (AFIO_EXTISS3) .......................................................... 152

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8.5.15. AFIO port configuration register 1 (AFIO_PCF1) ............................................................... 153
8.5.16. IO compensation control register (AFIO_CPSCTL)............................................................ 154
9. CRC calculation unit (CRC).................................................................................155
9.1. Overview .................................................................................................................. 155
9.2. Characteristics......................................................................................................... 155
9.3. Function overview................................................................................................... 156
9.4. Register definition................................................................................................... 157
9.4.1. Data register (CRC_DATA) ................................................................................................. 157
9.4.2. Free data register (CRC_FDATA) ....................................................................................... 157
9.4.3. Control register (CRC_CTL) ............................................................................................... 158
10. Direct memory access controller (DMA).........................................................159
10.1. Overview............................................................................................................... 159
10.2. Characteristics..................................................................................................... 159
10.3. Block diagram ...................................................................................................... 160
10.4. Function overview................................................................................................ 160
10.4.1. DMA operation .................................................................................................................... 160
10.4.2. Peripheral handshake......................................................................................................... 162
10.4.3. Arbitration............................................................................................................................ 162
10.4.4. Address generation............................................................................................................. 162
10.4.5. Circular mode...................................................................................................................... 163
10.4.6. Memory to memory mode................................................................................................... 163
10.4.7. Channel configuration......................................................................................................... 163
10.4.8. Interrupt............................................................................................................................... 163
10.4.9. DMA request mapping ........................................................................................................ 164
10.5. Register definition................................................................................................ 168
10.5.1. Interrupt flag register (DMA_INTF) ..................................................................................... 168
10.5.2. Interrupt flag clear register (DMA_INTC) ............................................................................ 169
10.5.3. Channel x control register (DMA_CHxCTL) ....................................................................... 169
10.5.4. Channel x counter register (DMA_CHxCNT)...................................................................... 171
10.5.5. Channel x peripheral base address register (DMA_CHxPADDR) ...................................... 172
10.5.6. Channel x memory base address register (DMA_CHxMADDR) ........................................ 172
11. Debug (DBG) .....................................................................................................174
11.1. Overview............................................................................................................... 174
11.2. JTAG/SW function overview................................................................................ 174
11.2.1. Switch JTAG or SW interface ............................................................................................. 174
11.2.2. Pin assignment ................................................................................................................... 174
11.2.3. JTAG daisy chained structure............................................................................................. 175
11.2.4. Debug reset ........................................................................................................................ 175

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11.2.5. JEDEC-106 ID code ........................................................................................................... 175
11.3. Debug hold function overview ............................................................................ 175
11.3.1. Debug support for power saving mode............................................................................... 175
11.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN ............................................ 176
11.4. Register definition................................................................................................ 177
11.4.1. ID code register (DBG_ID).................................................................................................. 177
11.4.2. Control register (DBG_CTL) ............................................................................................... 177
12. Analog-to-digital converter (ADC)...................................................................181
12.1. Overview............................................................................................................... 181
12.2. Characteristics..................................................................................................... 181
12.3. Pins and internal signals..................................................................................... 182
12.4. Function overview................................................................................................ 183
12.4.1. Foreground calibration function .......................................................................................... 183
12.4.2. ADC clock ........................................................................................................................... 184
12.4.3. ADCON enable ................................................................................................................... 184
12.4.4. Routine sequence............................................................................................................... 184
12.4.5. Operation modes ................................................................................................................ 184
12.4.6. Conversion result threshold monitor function ..................................................................... 187
12.4.7. Data storage mode ............................................................................................................. 187
12.4.8. Sample time configuration .................................................................................................. 188
12.4.9. External trigger configuration.............................................................................................. 188
12.4.10. DMA request ................................................................................................................... 189
12.4.11. ADC internal channels.................................................................................................... 189
12.4.12. Programmable resolution (DRES) .................................................................................. 190
12.4.13. On-chip hardware oversampling ..................................................................................... 190
12.5. ADC sync mode.................................................................................................... 192
12.5.1. Free mode........................................................................................................................... 193
12.5.2. Routine parallel mode......................................................................................................... 193
12.5.3. Routine follow-up fast mode ............................................................................................... 194
12.5.4. Routine follow-up slow mode.............................................................................................. 194
12.6. ADC interrupts...................................................................................................... 195
12.7. Register definition................................................................................................ 196
12.7.1. Status register (ADC_STAT) ............................................................................................... 196
12.7.2. Control register 0 (ADC_CTL0) .......................................................................................... 196
12.7.3. Control register 1 (ADC_CTL1) .......................................................................................... 198
12.7.4. Sample time register 0 (ADC_SAMPT0) ............................................................................ 200
12.7.5. Sample time register 1 (ADC_SAMPT1) ............................................................................ 201
12.7.6. Watchdog high threshold register (ADC_WDHT) ............................................................... 202
12.7.7. Watchdog low threshold register (ADC_WDLT) ................................................................. 202
12.7.8. Routine sequence register 0 (ADC_RSQ0)........................................................................ 202

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12.7.9. Routine sequence register 1 (ADC_RSQ1)........................................................................ 203
12.7.10. Routine sequence register 2 (ADC_RSQ2) .................................................................... 204
12.7.11. Routine data register (ADC_RDATA).............................................................................. 204
12.7.12. Oversample control register (ADC_OVSAMPCTL) ........................................................ 205
13. Digital-to-analog converter (DAC) ...................................................................207
13.1. Overview............................................................................................................... 207
13.2. Characteristics..................................................................................................... 207
13.3. Function overview................................................................................................ 208
13.3.1. DAC enable......................................................................................................................... 208
13.3.2. DAC output buffer ............................................................................................................... 208
13.3.3. DAC data configuration....................................................................................................... 209
13.3.4. DAC trigger ......................................................................................................................... 209
13.3.5. DAC workflow ..................................................................................................................... 209
13.3.6. DAC noise wave ................................................................................................................. 209
13.3.7. DAC output calculate .......................................................................................................... 210
13.3.8. DMA function........................................................................................................................211
13.3.9. DAC concurrent conversion.................................................................................................211
13.4. Register definition................................................................................................ 212
13.4.1. Control register (DAC_CTL) ............................................................................................... 212
13.4.2. Software trigger register (DAC_SWT) ................................................................................ 214
13.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH)....................................... 215
13.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH) ......................................... 215
13.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH)........................................... 216
13.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH)....................................... 216
13.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) ......................................... 217
13.4.8. DAC1 8-bit right-aligned data holding register (DAC1_R8DH)........................................... 217
13.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) ............ 217
13.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH) ........... 218
13.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) ............ 219
13.4.12. DAC0 data output register (DAC0_DO) .......................................................................... 219
13.4.13. DAC1 data output register (DAC1_DO) .......................................................................... 219
14. Watchdog timer (WDGT) ..................................................................................221
14.1. Free watchdog timer (FWDGT)............................................................................ 221
14.1.1. Overview ............................................................................................................................. 221
14.1.2. Characteristics .................................................................................................................... 221
14.1.3. Function overview ............................................................................................................... 221
14.1.4. Register definition ............................................................................................................... 224
14.2. Window watchdog timer (WWDGT)..................................................................... 227
14.2.1. Overview ............................................................................................................................. 227
14.2.2. Characteristics .................................................................................................................... 227
14.2.3. Function overview ............................................................................................................... 227

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14.2.4. Register definition ............................................................................................................... 230
15. Real-time Clock (RTC) ......................................................................................232
15.1. Overview............................................................................................................... 232
15.2. Characteristics..................................................................................................... 232
15.3. Function overview................................................................................................ 232
15.3.1. RTC reset............................................................................................................................ 233
15.3.2. RTC reading........................................................................................................................ 233
15.3.3. RTC configuration ............................................................................................................... 233
15.3.4. RTC flag assertion .............................................................................................................. 234
15.4. Register definition................................................................................................ 236
15.4.1. RTC interrupt enable register(RTC_INTEN)....................................................................... 236
15.4.2. RTC control register(RTC_CTL) ......................................................................................... 236
15.4.3. RTC prescaler high register (RTC_PSCH) ......................................................................... 237
15.4.4. RTC prescaler low register(RTC_PSCL) ............................................................................ 237
15.4.5. RTC divider high register (RTC_DIVH)............................................................................... 238
15.4.6. RTC divider low register (RTC_DIVL)................................................................................. 238
15.4.7. RTC counter high register(RTC_CNTH)............................................................................. 238
15.4.8. RTC counter low register (RTC_CNTL).............................................................................. 239
15.4.9. RTC alarm high register(RTC_ALRMH) ............................................................................. 239
15.4.10. RTC alarm low register (RTC_ALRML) .......................................................................... 239
16. TIMER ................................................................................................................240
16.1. Advanced timer (TIMERx, x=0, 7)........................................................................ 241
16.1.1. Overview ............................................................................................................................. 241
16.1.2. Characteristics .................................................................................................................... 241
16.1.3. Block diagram ..................................................................................................................... 242
16.1.4. Function overview ............................................................................................................... 243
16.1.5. TIMERx registers (x=0, 7)................................................................................................... 269
16.2. General level0 timer (TIMERx, x=1, 2, 3, 4)......................................................... 296
16.2.1. Overview ............................................................................................................................. 296
16.2.2. Characteristics .................................................................................................................... 296
16.2.3. Block diagram ..................................................................................................................... 296
16.2.4. Function overview ............................................................................................................... 297
16.2.5. TIMERx registers(x=1, 2, 3, 4)............................................................................................ 313
16.3. General level1 timer (TIMERx, x=8, 11)............................................................... 335
16.3.1. Overview ............................................................................................................................. 335
16.3.2. Characteristics .................................................................................................................... 335
16.3.3. Block diagram ..................................................................................................................... 335
16.3.4. Function overview ............................................................................................................... 336
16.3.5. TIMERx registers (x=8, 11) ................................................................................................. 348
16.4. General level2 timer (TIMERx, x=9, 10, 12, 13) ................................................... 360

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16.4.1. Overview ............................................................................................................................. 360
16.4.2. Characteristics .................................................................................................................... 361
16.4.3. Block diagram ..................................................................................................................... 361
16.4.4. Function overview ............................................................................................................... 361
16.4.5. TIMERx registers (x=9, 10, 12, 13)..................................................................................... 369
16.5. Basic timer (TIMERx, x=5, 6)................................................................................ 378
16.5.1. Overview ............................................................................................................................. 378
16.5.2. Characteristics .................................................................................................................... 378
16.5.3. Block diagram ..................................................................................................................... 378
16.5.4. Function overview ............................................................................................................... 379
16.5.5. TIMERx registers (x=5, 6)................................................................................................... 383
17. Universal synchronous/asynchronous receiver /transmitter (USART)........388
17.1. Overview............................................................................................................... 388
17.2. Characteristics..................................................................................................... 388
17.3. Function overview................................................................................................ 389
17.3.1. USART frame format .......................................................................................................... 390
17.3.2. Baud rate generation .......................................................................................................... 391
17.3.3. USART transmitter.............................................................................................................. 391
17.3.4. USART receiver .................................................................................................................. 392
17.3.5. Use DMA for data buffer access ......................................................................................... 394
17.3.6. Hardware flow control ......................................................................................................... 395
17.3.7. Multi-processor communication .......................................................................................... 396
17.3.8. LIN mode ............................................................................................................................ 397
17.3.9. Synchronous mode............................................................................................................. 398
17.3.10. IrDA SIR ENDEC mode .................................................................................................. 398
17.3.11. Half-duplex communication mode .................................................................................. 400
17.3.12. Smartcard (ISO7816-3) mode......................................................................................... 400
17.3.13. USART interrupts ............................................................................................................ 402
17.4. Register definition................................................................................................ 404
17.4.1. Status register 0 (USART_STAT0) ..................................................................................... 404
17.4.2. Data register (USART_DATA)............................................................................................. 406
17.4.3. Baud rate register (USART_BAUD).................................................................................... 406
17.4.4. Control register 0 (USART_CTL0)...................................................................................... 407
17.4.5. Control register 1 (USART_CTL1)...................................................................................... 409
17.4.6. Control register 2 (USART_CTL2)...................................................................................... 410
17.4.7. Guard time and prescaler register (USART_GP) ............................................................... 412
17.4.8. Control register 3 (USART_CTL3)...................................................................................... 413
17.4.9. Receiver timeout register (USART_RT) ............................................................................. 414
17.4.10. Status register 1 (USART_STAT1) ................................................................................. 415
17.4.11. Coherence control register (USART_CHC) .................................................................... 416
18. Inter-integrated circuit interface (I2C).............................................................417

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18.1. Overview............................................................................................................... 417
18.2. Characteristics..................................................................................................... 417
18.3. Function overview................................................................................................ 417
18.3.1. SDA and SCL lines ............................................................................................................. 418
18.3.2. Data validation .................................................................................................................... 419
18.3.3. START and STOP signal .................................................................................................... 419
18.3.4. Clock synchronization......................................................................................................... 419
18.3.5. Arbitration............................................................................................................................ 420
18.3.6. I2C communication flow...................................................................................................... 420
18.3.7. Programming model ........................................................................................................... 421
18.3.8. SCL line stretching.............................................................................................................. 430
18.3.9. Use DMA for data transfer .................................................................................................. 431
18.3.10. Packet error checking ..................................................................................................... 431
18.3.11. SMBus support ............................................................................................................... 431
18.3.12. SAM_V support ............................................................................................................... 433
18.3.13. Status, errors and interrupts ........................................................................................... 433
18.4. Register definition................................................................................................ 435
18.4.1. Control register 0 (I2C_CTL0) ............................................................................................ 435
18.4.2. Control register 1 (I2C_CTL1) ............................................................................................ 437
18.4.3. Slave address register 0 (I2C_SADDR0) ........................................................................... 438
18.4.4. Slave address register 1 (I2C_SADDR1) ........................................................................... 438
18.4.5. Transfer buffer register (I2C_DATA) ................................................................................... 439
18.4.6. Transfer status register 0 (I2C_STAT0) .............................................................................. 439
18.4.7. Transfer status register 1 (I2C_STAT1) .............................................................................. 442
18.4.8. Clock configure register (I2C_CKCFG) .............................................................................. 443
18.4.9. Rise time register (I2C_RT) ................................................................................................ 444
18.4.10. SAM control and status register (I2C_SAMCS).............................................................. 444
18.4.11. Fast-mode-plus configure register(I2C_FMPCFG)......................................................... 445
19. Serial peripheral interface/Inter-IC sound (SPI/I2S) .......................................447
19.1. Overview............................................................................................................... 447
19.2. Characteristics..................................................................................................... 447
19.2.1. SPI characteristics .............................................................................................................. 447
19.2.2. I2S characteristics .............................................................................................................. 447
19.3. SPI function overview.......................................................................................... 448
19.3.1. SPI block diagram............................................................................................................... 448
19.3.2. SPI signal description ......................................................................................................... 448
19.3.3. SPI clock timing and data format ........................................................................................ 449
19.3.4. NSS function ....................................................................................................................... 450
19.3.5. SPI operating modes .......................................................................................................... 451
19.3.6. DMA function....................................................................................................................... 460
19.3.7. CRC function....................................................................................................................... 460

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19.3.8. SPI interrupts ...................................................................................................................... 461
19.4. I2S function overview .......................................................................................... 462
19.4.1. I2S block diagram ............................................................................................................... 462
19.4.2. I2S signal description.......................................................................................................... 463
19.4.3. I2S audio standards ............................................................................................................ 463
19.4.4. I2S clock ............................................................................................................................. 471
19.4.5. Operation ............................................................................................................................ 472
19.4.6. DMA function....................................................................................................................... 476
19.4.7. I2S interrupts....................................................................................................................... 476
19.5. Register definition................................................................................................ 478
19.5.1. Control register 0 (SPI_CTL0) ............................................................................................ 478
19.5.2. Control register 1 (SPI_CTL1) ............................................................................................ 480
19.5.3. Status register (SPI_STAT)................................................................................................. 481
19.5.4. Data register (SPI_DATA) ................................................................................................... 482
19.5.5. CRC polynomial register (SPI_CRCPOLY) ........................................................................ 483
19.5.6. RX CRC register (SPI_RCRC) ........................................................................................... 483
19.5.7. TX CRC register (SPI_TCRC) ............................................................................................ 484
19.5.8. I2S control register (SPI_I2SCTL) ...................................................................................... 485
19.5.9. I2S clock prescaler register (SPI_I2SPSC) ........................................................................ 486
19.5.10. Quad-SPI mode control register (SPI_QCTL) of SPI0 ................................................... 487
20. External memory controller (EXMC) ...............................................................489
20.1. Overview ............................................................................................................... 489
20.2. Characteristics..................................................................................................... 489
20.3. Function overview................................................................................................ 489
20.3.1. Block diagram ..................................................................................................................... 489
20.3.2. Basic regulation of EXMC access....................................................................................... 490
20.3.3. NOR/PSRAM controller ...................................................................................................... 491
20.4. Register definition................................................................................................ 512
20.4.1. SRAM/NOR Flash control registers (EXMC_SNCTL) ........................................................ 512
20.4.2. SRAM/NOR Flash timing configuration registers (EXMC_SNTCFG)................................. 514
20.4.3. SRAM/NOR Flash write timing configuration registers (EXMC_SNWTCFG)..................... 515
21. Controller area network (CAN) ........................................................................517
21.1. Overview............................................................................................................... 517
21.2. Characteristics..................................................................................................... 517
21.3. Function overview................................................................................................ 518
21.3.1. Working mode..................................................................................................................... 518
21.3.2. Communication modes ....................................................................................................... 519
21.3.3. Data transmission ............................................................................................................... 520
21.3.4. Data reception..................................................................................................................... 522
21.3.5. Filtering function.................................................................................................................. 524

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21.3.6. Time-triggered communication ........................................................................................... 527
21.3.7. Communication parameters................................................................................................ 527
21.3.8. CAN FD operation .............................................................................................................. 529
21.3.9. Transmitter Delay Compensation ....................................................................................... 530
21.3.10. Error flags........................................................................................................................ 531
21.3.11. CAN interrupts ................................................................................................................ 531
21.4. Register definition................................................................................................ 534
21.4.1. Control register (CAN_CTL) ............................................................................................... 534
21.4.2. Status register (CAN_STAT) ............................................................................................... 535
21.4.3. Transmit status register (CAN_TSTAT) .............................................................................. 537
21.4.4. Receive message FIFO0 register (CAN_RFIFO0) ............................................................. 539
21.4.5. Receive message FIFO1 register (CAN_RFIFO1) ............................................................. 540
21.4.6. Interrupt enable register (CAN_INTEN).............................................................................. 541
21.4.7. Error register (CAN_ERR) .................................................................................................. 543
21.4.8. Bit timing register (CAN_BT) .............................................................................................. 543
21.4.9. FD control register (CAN_FDCTL)...................................................................................... 544
21.4.10. FD status register (CAN_FDSTAT) ................................................................................. 545
21.4.11. FD transmitter delay compensation register (CAN_FDTDC).......................................... 546
21.4.12. Date Bit timing register (CAN_DBT) ............................................................................... 547
21.4.13. Transmit mailbox identifier register (CAN_TMIx) (x = 0...2)............................................ 547
21.4.14. Transmit mailbox property register (CAN_TMPx) (x = 0...2) .......................................... 548
21.4.15. Transmit mailbox data0 register (CAN_TMDATA0x) (x = 0...2) ...................................... 549
21.4.16. Transmit mailbox data1 register (CAN_TMDATA1x) (x=0...2) ........................................ 549
21.4.17. Rx FIFO mailbox identifier register (CAN_RFIFOMIx) (x = 0,1) ..................................... 550
21.4.18. Rx FIFO mailbox property register (CAN_RFIFOMPx) (x = 0,1) .................................... 551
21.4.19. Rx FIFO mailbox data0 register (CAN_RFIFOMDATA0x) (x=0,1).................................. 551
21.4.20. Rx FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x = 0,1)................................ 552
21.4.21. Filter control register (CAN_FCTL) ................................................................................. 552
21.4.22. Filter mode configuration register (CAN_FMCFG) ......................................................... 553
21.4.23. Filter scale configuration register (CAN_FSCFG)........................................................... 553
21.4.24. Filter associated FIFO register (CAN_FAFIFO).............................................................. 554
21.4.25. Filter working register (CAN_FW)................................................................................... 554
21.4.26. Filter x data y register (CAN_FxDATAy) (x = 0...27, y = 0,1) .......................................... 555
22. Universal serial bus full-speed interface (USBFS).........................................556
22.1. Overview............................................................................................................... 556
22.2. Characteristics..................................................................................................... 556
22.3. Block diagram ...................................................................................................... 557
22.4. Signal description................................................................................................ 557
22.5. Function overview................................................................................................ 557
22.5.1. USBFS clocks and working modes..................................................................................... 557
22.5.2. USB host function ............................................................................................................... 559

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22.5.3. USB device function ........................................................................................................... 561
22.5.4. OTG function overview ....................................................................................................... 562
22.5.5. Data FIFO ........................................................................................................................... 563
22.5.6. Operation guide .................................................................................................................. 566
22.6. Interrupts.............................................................................................................. 570
22.7. Register definition................................................................................................ 572
22.7.1. Global control and status registers ..................................................................................... 572
22.7.2. Host control and status registers ........................................................................................ 593
22.7.3. Device control and status registers .................................................................................... 605
22.7.4. Power and clock control register (USBFS_PWRCLKCTL)................................................. 629
23. Appendix ...........................................................................................................630
23.1. List of abbreviations used in register................................................................. 630
23.2. List of terms.......................................................................................................... 630
23.3. Available peripherals ........................................................................................... 631
24. Revision history................................................................................................632

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List of Figures
Figure 1-1. The structure of the Cortex®-M4 processor......................................................................... 24
Figure 1-2. GD32C10x series system architecture................................................................................. 26
Figure 2-1. Process of page erase operation.......................................................................................... 39
Figure 2-2. Process of mass erase operation......................................................................................... 40
Figure 2-3. Process of word program operation .................................................................................... 42
Figure 3-1. Power supply overview ......................................................................................................... 54
Figure 3-2. Waveform of the POR / PDR.................................................................................................. 56
Figure 3-3. Waveform of the LVD threshold ........................................................................................... 56
Figure 5-1. The system reset circuit ........................................................................................................ 69
Figure 5-2. Clock tree ................................................................................................................................ 70
Figure 5-3. HXTAL clock source............................................................................................................... 71
Figure 5-4. HXTAL clock source in bypass mode .................................................................................. 72
Figure 6-1. CTC overview........................................................................................................................ 107
Figure 6-2. CTC trim counter.................................................................................................................. 108
Figure 7-1. Block diagram of EXTI......................................................................................................... 121
Figure 8-1. Basic structure of of a general-pupose I/O........................................................................ 127
Figure 8-2. Basic structure of Input configuration............................................................................... 128
Figure 8-3. Basic structure of Output configuration............................................................................ 129
Figure 8-4. Basic structure of Analog configuration ........................................................................... 130
Figure 8-5. Basic structure of Alternate function configuration......................................................... 130
Figure 9-1. Block diagram of CRC calculation unit.............................................................................. 156
Figure 10-1. Block diagram of DMA....................................................................................................... 160
Figure 10-2. Handshake mechanism ..................................................................................................... 162
Figure 10-3. DMA interrupt logic............................................................................................................ 164
Figure 10-4. DMA0 request mapping ..................................................................................................... 165
Figure 10-5. DMA1 request mapping ..................................................................................................... 166
Figure 12-1. ADC module block diagram .............................................................................................. 183
Figure 12-2. Single operation mode....................................................................................................... 184
Figure 12-3. Continuous operation mode ............................................................................................. 185
Figure 12-4. Scan operation mode, continuous disable...................................................................... 186
Figure 12-5. Scan operation mode, continuous enable....................................................................... 186
Figure 12-6. Discontinuous operation mode ........................................................................................ 187
Figure 12-7. 12-bit data storage mode................................................................................................... 188
Figure 12-8. 6-bit data storage mode..................................................................................................... 188
Figure 12-9. 20-bit to 16-bit result truncation ....................................................................................... 191
Figure 12-10. A numerical example with 5-bit shifting and rounding ................................................ 191
Figure 12-11. ADC sync block diagram................................................................................................. 193
Figure 12-12. Routine parallel mode on 10 channels........................................................................... 194
Figure 12-13. Routine follow-up fast mode (the CTN bit of ADCs are set) ........................................ 194
Figure 12-14. Routine follow-up slow mode ......................................................................................... 195

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Figure 13-1. DAC block diagram ............................................................................................................ 208
Figure 13-2. DAC LFSR algorithm.......................................................................................................... 210
Figure 13-3. DAC triangle noise wave ................................................................................................... 210
Figure 14-1. Free watchdog block diagram .......................................................................................... 222
Figure 14-2. Window watchdog timer block diagram .......................................................................... 227
Figure 14-3. Window watchdog timing diagram................................................................................... 228
Figure 15-1. Block diagram of RTC........................................................................................................ 233
Figure 16-1. Advanced timer block diagram......................................................................................... 242
Figure 16-2. Timing chart of internal clock divided by 1 ..................................................................... 243
Figure 16-3. Timing chart of PSC value change from 0 to 2 ............................................................... 244
Figure 16-4. Timing chart of up counting mode, PSC=0/2 .................................................................. 245
Figure 16-5. Timing chart of up counting mode, change TIMERx_CAR on the go........................... 246
Figure 16-6. Timing chart of down counting mode, PSC=0/2 ............................................................. 247
Figure 16-7. Timing chart of down counting mode, change TIMERx_CAR on the go...................... 247
Figure 16-8. Center-aligned counter timechart..................................................................................... 249
Figure 16-9. Repetition timechart for center-aligned counter............................................................. 250
Figure 16-10. Repetition timechart for up-counter............................................................................... 250
Figure 16-11. Repetition timechart for down-counter.......................................................................... 251
Figure 16-12. Channel input capture principle ..................................................................................... 252
Figure 16-13. Output-compare under three modes.............................................................................. 254
Figure 16-14. EAPWM timechart ............................................................................................................ 255
Figure 16-15. CAPWM timechart ............................................................................................................ 255
Figure 16-16. Complementary output with dead-time insertion ......................................................... 258
Figure 16-17. Output behavior in response to a break(The break high active)................................. 259
Figure 16-18. Counter behavior with CI0FE0 polarity non-inverted in mode 2 ................................. 260
Figure 16-19. Counter behavior with CI0FE0 polarity inverted in mode 2 ......................................... 261
Figure 16-20. Hall sensor is used to BLDC motor................................................................................ 262
Figure 16-21. Hall sensor timing between two timers.......................................................................... 262
Figure 16-22. Restart mode .................................................................................................................... 263
Figure 16-23. Pause mode ...................................................................................................................... 264
Figure 16-24. Event mode ....................................................................................................................... 264
Figure 16-25. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 .......................................... 265
Figure 16-26. Timer0 master/slave mode timer example..................................................................... 266
Figure 16-27. Triggering TIMER0 with enable signal of TIMER2......................................................... 267
Figure 16-28. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input............................................ 268
Figure 16-29. General Level 0 timer block diagram ............................................................................. 297
Figure 16-30. Timing chart of internal clock divided by 1................................................................... 298
Figure 16-31. Timing chart of PSC value change from 0 to 2 ............................................................. 299
Figure 16-32. Timing chart of up counting mode, PSC=0/2 ................................................................ 300
Figure 16-33. Timing chart of up counting mode, change TIMERx_CAR ongoing........................... 301
Figure 16-34. Timing chart of down counting mode, PSC=0/2 ........................................................... 302
Figure 16-35. Timing chart of down counting mode, change TIMERx_CAR ongoing...................... 302
Figure 16-36. Timing chart of center-aligned counting mode............................................................. 304
Figure 16-37. Channel input capture principle ..................................................................................... 305

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Figure 16-38. Output-compare under three modes.............................................................................. 307
Figure 16-39. EAPWM timechart ............................................................................................................ 308
Figure 16-40. CAPWM timechart ............................................................................................................ 308
Figure 16-41. Restart mode .................................................................................................................... 310
Figure 16-42. Pause mode ...................................................................................................................... 310
Figure 16-43. Event mode ........................................................................................................................311
Figure 16-44. General level1 timer block diagram................................................................................ 336
Figure 16-45. Timing chart of internal clock divided by 1................................................................... 337
Figure 16-46. Timing chart of PSC value change from 0 to 2 ............................................................. 338
Figure 16-47. Timing chart of up counting mode, PSC=0/2 ................................................................ 339
Figure 16-48. Timing chart of up counting mode, change TIMERx_CAR ongoing........................... 339
Figure 16-49. Channel input capture principle ..................................................................................... 340
Figure 16-50. Output-compare under three modes.............................................................................. 342
Figure 16-51. EAPWM timechart ............................................................................................................ 343
Figure 16-52. CAPWM timechart ............................................................................................................ 343
Figure 16-53. Restart mode .................................................................................................................... 345
Figure 16-54. Pause mode ...................................................................................................................... 345
Figure 16-55. Event mode ....................................................................................................................... 346
Figure 16-56. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 .......................................... 347
Figure 16-57. General level2 timer block diagram................................................................................ 361
Figure 16-58. Timing chart of internal clock divided by 1................................................................... 362
Figure 16-59. Timing chart of PSC value change from 0 to 2 ............................................................. 363
Figure 16-60. Timing chart of up counting mode, PSC=0/2 ................................................................ 364
Figure 16-61. Timing chart of up counting mode, change TIMERx_CAR on the go......................... 364
Figure 16-62. Channel input capture principle ..................................................................................... 365
Figure 16-63. Output-compare under three modes.............................................................................. 367
Figure 16-64. Basic timer block diagram .............................................................................................. 379
Figure 16-65. Timing chart of internal clock divided by 1................................................................... 379
Figure 16-66. Timing chart of PSC value change from 0 to 2 ............................................................. 380
Figure 16-67. Timing chart of up counting mode, PSC=0/2 ................................................................ 381
Figure 16-68. Timing chart of up counting mode, change TIMERx_CAR ongoing........................... 381
Figure 17-1. USART module block diagram.......................................................................................... 390
Figure 17-2. USART character frame (8 bits data and 1 stop bit) ....................................................... 390
Figure 17-3. USART transmit procedure ............................................................................................... 392
Figure 17-4. Receiving a frame bit by oversampling method ............................................................. 393
Figure 17-5. Configuration steps when using DMA for USART transmission .................................. 394
Figure 17-6. Configuration steps when using DMA for USART reception......................................... 395
Figure 17-7. Hardware flow control between two USARTs.................................................................. 395
Figure 17-8. Hardware flow control........................................................................................................ 396
Figure 17-9. Break frame occurs during idle state............................................................................... 397
Figure 17-10. Break frame occurs during a frame................................................................................ 397
Figure 17-11. Example of USART in synchronous mode .................................................................... 398
Figure 17-12. 8-bit format USART synchronous waveform (CLEN=1) ............................................... 398
Figure 17-13. IrDA SIR ENDEC module ................................................................................................. 399

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Figure 17-14. IrDA data modulation ....................................................................................................... 399
Figure 17-15. ISO7816-3 frame format................................................................................................... 400
Figure 17-16. USART interrupt mapping diagram ................................................................................ 403
Figure 18-1. I2C module block diagram ................................................................................................ 418
Figure 18-2. Data validation.................................................................................................................... 419
Figure 18-3. START and STOP signal .................................................................................................... 419
Figure 18-4. Clock synchronization....................................................................................................... 420
Figure 18-5. SDA line arbitration ............................................................................................................ 420
Figure 18-6. I2C communication flow with 7-bit address .................................................................... 421
Figure 18-7. I2C communication flow with 10-bit address (Master Transmit) ................................... 421
Figure 18-8. I2C communication flow with 10-bit address (Master Receive) .................................... 421
Figure 18-9. Programming model for slave transmitting (10-bit address mode).............................. 423
Figure 18-10. Programming model for slave receiving (10-bit address mode) ................................. 424
Figure 18-11. Programming model for master transmitting (10-bit address mode) ......................... 426
Figure 18-12. Programming model for master receiving using Solution A (10-bit address mode) 428
Figure 18-13. Programming model for master receiving mode using solution B (10-bit address
mode) ................................................................................................................................................ 429
Figure 19-1. Block diagram of SPI ......................................................................................................... 448
Figure 19-2. SPI timing diagram in normal mode................................................................................. 449
Figure 19-3. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0) ................................ 450
Figure 19-4. A typical full-duplex connection....................................................................................... 453
Figure 19-5. A typical simplex connection (Master: Receive, Slave: Transmit)................................ 453
Figure 19-6. A typical simplex connection (Master: Transmit only, Slave: Receive) ....................... 453
Figure 19-7. A typical bidirectional connection.................................................................................... 453
Figure 19-8. Timing diagram of TI master mode with discontinuous transfer.................................. 455
Figure 19-9. Timing diagram of TI master mode with continuous transfer....................................... 456
Figure 19-10. Timing diagram of TI slave mode ................................................................................... 456
Figure 19-11. Timing diagram of NSS pulse with continuous transmission..................................... 457
Figure 19-12. Timing diagram of quad write operation in Quad-SPI mode ....................................... 458
Figure 19-13. Timing diagram of quad read operation in Quad-SPI mode........................................ 459
Figure 19-14. Block diagram of I2S........................................................................................................ 462
Figure 19-15. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0)..................... 463
Figure 19-16. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1)..................... 464
Figure 19-17. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0)..................... 464
Figure 19-18. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1)..................... 464
Figure 19-19. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0)..................... 464
Figure 19-20. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1)..................... 464
Figure 19-21. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0)..................... 465
Figure 19-22. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1)..................... 465
Figure 19-23. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0)................. 465
Figure 19-24. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1)................. 465
Figure 19-25. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0)................. 466
Figure 19-26. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1)................. 466
Figure 19-27. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0)................. 466

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Figure 19-28. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ................. 466
Figure 19-29. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0)................. 466
Figure 19-30. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1)................. 466
Figure 19-31. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0).................. 467
Figure 19-32. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1).................. 467
Figure 19-33. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0).................. 467
Figure 19-34. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1).................. 467
Figure 19-35. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=0) ......................................................................................................................... 468
Figure 19-36. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=1) ......................................................................................................................... 468
Figure 19-37. PCM standard short frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=0) ......................................................................................................................... 468
Figure 19-38. PCM standard short frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=1) ......................................................................................................................... 468
Figure 19-39. PCM standard short frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=0) ......................................................................................................................... 468
Figure 19-40. PCM standard short frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=1) ......................................................................................................................... 469
Figure 19-41. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=0) ......................................................................................................................... 469
Figure 19-42. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=1) ......................................................................................................................... 469
Figure 19-43. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=0) ......................................................................................................................... 469
Figure 19-44. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=1) ......................................................................................................................... 469
Figure 19-45. PCM standard long frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=0) ......................................................................................................................... 470
Figure 19-46. PCM standard long frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=1) ......................................................................................................................... 470
Figure 19-47. PCM standard long frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=0) ......................................................................................................................... 470
Figure 19-48. PCM standard long frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=1) ......................................................................................................................... 470
Figure 19-49. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=0) ......................................................................................................................... 470
Figure 19-50. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=1) ......................................................................................................................... 471
Figure 19-51. Block diagram of I2S clock generator............................................................................ 471
Figure 19-52. I2S initialization sequence .............................................................................................. 473
Figure 19-53. I2S master reception disabling sequence ..................................................................... 475
Figure 20-1. The EXMC block diagram.................................................................................................. 490
Figure 20-2. EXMC memory banks......................................................................................................... 491

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Figure 20-3. Mode 1 read access ........................................................................................................... 495
Figure 20-4. Mode 1 write access........................................................................................................... 495
Figure 20-5. Mode A read access........................................................................................................... 496
Figure 20-6. Mode A write access.......................................................................................................... 497
Figure 20-7. Mode 2/B read access........................................................................................................ 498
Figure 20-8. Mode 2 write access........................................................................................................... 499
Figure 20-9. Mode B write access.......................................................................................................... 499
Figure 20-10. Mode C read access......................................................................................................... 501
Figure 20-11. Mode C write access........................................................................................................ 501
Figure 20-12. Mode D read access......................................................................................................... 503
Figure 20-13. Mode D write access........................................................................................................ 503
Figure 20-14. Multiplex mode read access ........................................................................................... 505
Figure 20-15. Multiplex mode write access........................................................................................... 505
Figure 20-16. Read access timing diagram under async-wait signal assertion ............................... 507
Figure 20-17. Write access timing diagram under async-wait signal assertion............................... 507
Figure 20-18. Read timing of synchronous multiplexed burst mode................................................. 509
Figure 20-19. Write timing of synchronous multiplexed burst mode................................................. 510
Figure 21-1. CAN module block diagram .............................................................................................. 518
Figure 21-2. Transmission register ........................................................................................................ 520
Figure 21-3. State of transmit mailbox .................................................................................................. 521
Figure 21-4. Reception register.............................................................................................................. 523
Figure 21-5. 32-bit filter ........................................................................................................................... 524
Figure 21-6. 16-bit filter ........................................................................................................................... 524
Figure 21-7. 32-bit mask mode filter ...................................................................................................... 524
Figure 21-8. 16-bit mask mode filter ...................................................................................................... 525
Figure 21-9. 32-bit list mode filter .......................................................................................................... 525
Figure 21-10. 16-bit list mode filter ........................................................................................................ 525
Figure 21-11. The bit time ....................................................................................................................... 528
Figure 21-12. Transmitter Delay Measurement..................................................................................... 531
Figure 22-1. USBFS block diagram........................................................................................................ 557
Figure 22-2. Connection with host or device mode ............................................................................. 558
Figure 22-3. Connection with OTG mode.............................................................................................. 559
Figure 22-4. State transition diagram of host port............................................................................... 559
Figure 22-5. HOST mode FIFO space in SRAM .................................................................................... 564
Figure 22-6. Host mode FIFO access register mapping...................................................................... 564
Figure 22-7. Device mode FIFO space in SRAM................................................................................... 565
Figure 22-8. Device mode FIFO access register mapping .................................................................. 565