Cypress Semiconductor MoBL CY62157E User manual

8-Mbit (512K x 16) Static RAM
CY62157E MoBL®
Cypress Semiconductor Corporation • 198ChampionCourt • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05695 Rev. *C Revised November 21, 2006
Features
• Very high speed: 45 ns
• Wide voltage range: 4.5V–5.5V
• Ultra-low standby power
—Typical Standby current: 2 µA
—Maximum Standby current: 8 µA (Industrial)
• Ultra-low active power
— Typical active current: 1.8 mA @ f = 1 MHz
• Ultra-low standby power
• Easymemory expansionwithCE1,CE2and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free 44-pin TSOP II and 48-ball VFBGA
package
Functional Description[1]
The CY62157E is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™(MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption when addresses are not toggling.
The device can also be put into standby mode when
deselected (CE1HIGH or CE2 LOW or both BHE and BLE are
HIGH). The input/output pins (IO0through IO15) are placed in
a high-impedance state when: deselected (CE1HIGH or CE2
LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE1LOW, CE2HIGH and WE
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE1 LOW and CE2HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0
through IO7), is written into the location specified on the
address pins (A0through A18). If Byte High Enable (BHE) is
LOW, then data from IO pins (IO8through IO15) is written into
the location specified on the address pins (A0through A18).
Reading from the device is accomplished by taking Chip
Enable (CE1 LOW and CE2HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on IO0to IO7. If Byte
HighEnable (BHE)is LOW,thendatafrommemorywillappear
onIO8to IO15. See the truth table at the back of this data sheet
for a complete description of read and write modes.
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
512K x 16
RAM Array IO0–IO7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11 A12 A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3IO8–IO15
WE
BLE
BHE
A16
A0
A1
A17
A9
BHE
BLE
A10
A18
POWER-DOWN
CIRCUIT CE2
CE1
CE2
CE1
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CY62157E MoBL®
Document #: 38-05695 Rev. *C Page 2 of 12
Pin Configuration[2, 3]
Product Portfolio
Product Range
VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC, (mA) Standby, ISB2
(µA)f = 1MHz f = fmax
Min Typ[4] Max Typ[4] Max Typ[4] Max Typ[4] Max
CY62157E-45 Ind’l 4.5 5.0 5.5 45 1.8 3 18 25 2 8
CY62157E-55[5] Auto 4.5 5.0 5.5 55 1.8 418 35 230
Notes:
2. NC pins are not connected on the die.
3. The 44-pin TSOP II package has only one chip enable (CE) pin.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA= 25°C.
5. Automotive product information is Preliminary.
WE
A11
A10
A6
A0
A3CE1
IO10
IO8
IO9
A4
A5
IO11
IO13
IO12
IO14
IO15
VSS
A9
A8
OE
Vss
A7
IO0
BHE
CE2
A17
A2
A1
BLE
VCC
IO2
IO1
IO3
IO4
IO5IO6
IO7
A15 A14
A13
A12
NC
A18 NC
3
26
5
4
1
D
E
B
A
C
F
G
H
VFBGA
A16
NC
Vcc
Top View
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15 29 30
A
5
18
17
20
19 27
28
25
26
22
21 23
24
TSOP II
Top View
A
6
A
7
A
3
A
2
A
1
A
0
A
17
A
4
A
9
A
10
A
11
A
12
A
15
A
16
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
10
A
18
A
14
A
8
A
13
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CY62157E MoBL®
Document #: 38-05695 Rev. *C Page 3 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Supply Voltage to Ground
Potential .......................................................... –0.5V to 6.0V
DC Voltage Applied to Outputs
in High Z State[6, 7]........................................... –0.5V to 6.0V
DC Input Voltage[6, 7]........................................–0.5V to 6.0V
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ..........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ...................................................> 200 mA
Operating Range
Device Range Ambient Temperature VCC[8]
CY62157E Industrial –40°C to +85°C 4.5V to 5.5V
Automotive –40°C to +125°C
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
45 ns (Industrial) 55 ns (Automotive)
UnitMin Typ[4] Max Min Typ[4] Max
VOH Output HIGH
Voltage IOH = –1 mA VCC = 4.5V 2.4 2.4 V
VOL Output LOW
Voltage IOL = 2.1 mA VCC = 4.5V 0.4 0.4 V
VIH Input HIGH
Voltage VCC = 4.5V to 5.5V 2.2 VCC + 0.5 2.2 VCC + 0.5 V
VIL Input LOW
Voltage VCC = 4.5V to 5.5V –0.5 0.8 –0.5 0.8 V
IIX Input Leakage
Current GND < VI< VCC –1 +1 –1 +1 µA
IOZ Output Leakage
Current GND< VO<VCC,Output Disabled –1 +1 –1 +1 µA
ICC VCC Operating
Supply
Current
f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA
CMOS levels
18 25 18 35 mA
f = 1 MHz 1.8 3 1.8 4
ISB1 Automatic CE
Power-Down
Current —
CMOS Inputs
CE1> VCC − 0.2V, CE2 <0.2V,
VIN >VCC – 0.2V, VIN <0.2V,
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60V
28 230 µA
ISB2 Automatic CE
Power-Down
Current —
CMOS Inputs
CE1> VCC – 0.2V or CE2< 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
28 230 µA
Capacitance[9]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz, VCC = VCC(typ) 10 pF
COUT Output Capacitance 10 pF
Notes:
6. VIL(min) = –2.0V for pulse durations less than 20 ns for I < 30 mA.
7. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
8. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
9. Tested initially and after any design or process changes that may affect these parameters.
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CY62157E MoBL®
Document #: 38-05695 Rev. *C Page 4 of 12
Thermal Resistance[9]
Parameter Description Test Conditions TSOP II VFBGA Unit
ΘJA Thermal Resistance
(Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 77 72 °C/W
ΘJC Thermal Resistance
(Junction to Case) 13 8.86 °C/W
AC Test Loads and Waveforms
Parameters Values Unit
R1 1800 Ω
R2 990 Ω
RTH 639 Ω
VTH 1.77 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ[4] Max Unit
VDR VCC for Data Retention 2 V
ICCDR Data Retention Current VCC=2V, CE1>VCC – 0.2V,
CE2< 0.2V, VIN > VCC – 0.2V or VIN < 0.2V Industrial 8 µA
Automotive 30
tCDR[9] Chip Deselect to Data
Retention Time 0ns
tR[10] Operation Recovery Time tRC ns
Data Retention Waveform[11]
Notes:
10.Full device operation requires linear VCC ramp from VDR to VCC(min) >100 µs or stable at VCC(min) >100 µs.
11. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
3V
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
VCC(min)
tCDR
VDR >2 V
DATA RETENTION MODE
tR
VCC
CE1or
BHE.BLE
CE2
VCC(min)
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CY62157E MoBL®
Document #: 38-05695 Rev. *C Page 5 of 12
Switching Characteristics Over the Operating Range [12]
Parameter Description
45 ns 55 ns
UnitMin Max Min Max
Read Cycle
tRC Read Cycle Time 45 55 ns
tAA Address to Data Valid 45 55 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE1LOW and CE2 HIGH to Data Valid 45 55 ns
tDOE OE LOW to Data Valid 22 25 ns
tLZOE OE LOW to LOW Z[13] 5 5 ns
tHZOE OE HIGH to High Z[13, 14] 18 20 ns
tLZCE CE1LOW and CE2 HIGH to Low Z[13] 10 10 ns
tHZCE CE1HIGH and CE2 LOW to High Z[13, 14] 18 20 ns
tPU CE1LOW and CE2 HIGH to Power-Up 0 0ns
tPD CE1HIGH and CE2 LOW to Power-Down 45 55 ns
tDBE BLE/BHE LOW to Data Valid 45 55 ns
tLZBE BLE/BHE LOW to Low Z[13] 10 10 ns
tHZBE BLE/BHE HIGH to HIGH Z[13, 14] 18 20 ns
Write Cycle[15]
tWC Write Cycle Time 45 55 ns
tSCE CE1LOW and CE2 HIGH to Write End 35 40 ns
tAW Address Set-Up to Write End 35 40 ns
tHA Address Hold from Write End 0 0ns
tSA Address Set-Up to Write Start 00ns
tPWE WE Pulse Width 35 40 ns
tBW BLE/BHE LOW to Write End 35 40 ns
tSD Data Set-Up to Write End 25 25 ns
tHD Data Hold from Write End 00ns
tHZWE WE LOW to High-Z[13, 14] 18 20 ns
tLZWE WE HIGH to Low-Z[13] 10 10 ns
Notes:
12.Test conditions for all parameters other than Tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
13.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
14.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
15.The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the Write.
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CY62157E MoBL®
Document #: 38-05695 Rev. *C Page 6 of 12
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[16, 17]
Read Cycle 2 (OE Controlled)[17, 18]
Notes:
16.The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
17.WE is HIGH for read cycle.
18.Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2transition HIGH.
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tPD
tHZBE
tLZBE
tHZCE
tDBE
HIGH
ICC
ISB
IMPEDANC
E
OE
CE1
ADDRESS
VCC
SUPPLY
CURRENT
BHE/BLE
DATA OUT
CE2
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CY62157E MoBL®
Document #: 38-05695 Rev. *C Page 7 of 12
Write Cycle 1 (WE Controlled)[15, 19, 20, 21]
Write Cycle 2 (CE1or CE2 Controlled)[15, 19, 20, 21]
Notes:
19.Data IO is high impedance if OE = VIH.
20.If CE1goes HIGH and CE2goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
21.During this period, the IOs are in output state and input signals should not be applied.
Switching Waveforms (continued)
tHD
tSD
tPWE tSA
tHA tAW
tSCE
tWC
tHZOE
VALID DATA
tBW
See Note 21
ADDRESS
WE
DATA IO
OE
BHE/BLE
CE1
CE2
tHD
tSD
tPWE
tHA tAW
tSCE
tWC
tHZOE
VALID DATA
See Note 21
tBW
tSA
CE
1
ADDRESS
WE
DATA IO
OE
BHE/BLE
CE
2
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CY62157E MoBL®
Document #: 38-05695 Rev. *C Page 8 of 12
Write Cycle 3 (WE Controlled, OE LOW)[20, 21]
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[20, 21]
Switching Waveforms (continued)
VALID DATA
tHD
tSD
tLZWE
tPWE tSA
tHA tAW
tSCE
tWC
tHZWE
tBW
See Note 21
CE1
ADDRESS
CE2
WE
DATA IO
BHE/BLE
tHD tSD
tSA
tHA tAW
tWC
VALID DATA
tBW
tSCE
tPWE
See Note 21
DATA IO
ADDRESS
CE1
WE
BHE/BLE
CE2
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CY62157E MoBL®
Document #: 38-05695 Rev. *C Page 9 of 12
Truth Table
CE1CE2WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X X High Z Deselect/Power-Down Standby (ISB)
X L X X X X High Z Deselect/Power-Down Standby (ISB)
X X X X H H High Z Deselect/Power-Down Standby (ISB)
L H H L L L Data Out (IO0–IO15)Read Active (ICC)
L H H L H L Data Out (IO0–IO7);
High Z (IO8–IO15)Read Active (ICC)
L H H L L H High Z (IO0–IO7);
Data Out (IO8–IO15)Read Active (ICC)
L H H H L H High Z Output Disabled Active (ICC)
L H H H H L High Z Output Disabled Active (ICC)
L H H H L L High Z Output Disabled Active (ICC)
L H L X L L Data In (IO0–IO15)Write Active (ICC)
L H L X H L Data In (IO0–IO7);
High Z (IO8–IO15)Write Active (ICC)
L H L X L H High Z (IO0–IO7);
Data In (IO8–IO15)Write Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package Diagram Package Type Operating Range
45 CY62157ELL-45ZSXI 51-85087 44-pin Thin Small Outline Package Type II (Pb-free) Industrial
55 CY62157ELL-55ZSXE 51-85087 44-pin Thin Small Outline Package Type II (Pb-free) Automotive
CY62157ELL-55BVXE 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
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CY62157E MoBL®
Document #: 38-05695 Rev. *C Page 10 of 12
Package Diagrams
44-pin TSOP II (51-85087)
51-85087-*A
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