Digital Equipment LAB-8/E User manual

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manual:
LAB-8/E
MAINTENANCE
MANUAL
laboratory
data
products

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Ist
Edition,
March 1972
2nd
Printing
(Rev)
August
1973
Copyright
©
1972,
1973
by Digital Equipment
Corporation
The
material in
this
manual is for informa-
tional
purposes
and
is
subject
to
change
without notice.
The
following
are trademarks
of
Digital Equipment
Corporation,
Maynard,
Massachusetts:
DEC
PDP
FLIP CHIP
FOCAL
DIGITAL
COMPUTER
LAB
UNIBUS

CONTENTS
CHAPTER 1
INTRODUCTION
1.1
Purpose
of Manual
1.21
System
Features
1.2.1
Analog-to-Digital
Converter
(AD8—EA)
1.2.2
Analog Preamplifier
and
Multiplexer
(AM8—EA)
1.2.3
Point-Plot
Display
Control
(VC8—E)
1.2.4
Buffered
Digital
l/O
(D R8-EA)
1.2.5
Real-Time
Programmable
Clock
(DK8-EP)
1.2.6
Analog Input
Panels
(AM8-ED
and
AM8-EC)
1.2.7
Real-Time
Programmable
Clock
Input
Panel
(DK8-EF)
1.2.8
Digital
l/O
Panel
(D
R8-EB)
1.3
Physical
Description
1.4
Documentation
CHAPTER 2
INSTALLATION
2.1
Site
Considerations
2.1.1
Power Source
2.2
l/O
Panels and
Cabling Requirements
2.2.1
A/D
Converter
Connections
2.2.2 Buffered
Digital
l/O
Connections
2.2.3 Real-Time
Programmable
Clock
Input
Connections
2.2.4
Point-Plot
Display
(VC8-E)
Control
Connections
2.3 Fire
And
Safety
Precautions
2.4
Installation Procedures
2.4.1
Unpacking
and
inspection
2.4.2 Installation Procedure
2.5
Acceptance
Test
2.5.1 Central Processor
Acceptance
Test
2.5.2
Analog-to-Digital
Converter
(ADB-EA)
and
Analog Multiplexer
(AM8—EA)
Acceptance
Test
2.5.2.1
Acceptance
Test
2.5.3 Point-Plot
Display
Control
(VC8-E)
Acceptance
Test
2.5.3.1
Control
Logic
Acceptance
Test
2.5.3.2
VC8-E
Ramp
Slewing
Test
2.5.3.3 VC8-E
Display
Test
2.5.4 Real-Time Clock
(DK8—EP
and
DK8-ES)
Acceptance
Test
2.5.4.1
Acceptance
Tests
2.5.4.2
DK8-ES
Acceptance
Test
2.5.5
Buffered
Digital
I/O
(D R8-EA)
Acceptance
Tests
2.5.5.1 Visual
Inspection
and Test
Setup
2.5.5.2 DR8-EA
Acceptance
Test Without
DR8—EB
Panel
P?
5247
few
602
”0d?
77'“;
Page
M
1-1
1-3
1-3
1-3
1-3
1-3
1-4
1-4
1-4
1-7
1-7
2—1
2-2
2-2
2-2
2—4
2-5
245
2-6
2-6
2-6
2-12
2-18
2-19
2-19
2-20
2-24
2-24
2-25
2-25
2-28
2-28
2-29
2-30
2-31
2-31

CONTENTS
(Cont)
CHAPTER 3
OPERATING PROCEDURES
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.6.1
3.1.6.2
3.1.6.3
3.1.6.4
3.1.7
3.1.7.1
3.1.8
3.1.9
3.1.9.1
3.1.9.2
3.1.10
3.2
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3
3.2.2.4
3.2.2.5
3.2.2.6
Computer
Operation
Controls
and Indicators
Keyboard Operation
Printer
Operation
Paper-Tape
Reader
Operation
Operating
Procedures
Manual Data
Storage
and Modification
Power
for
Manual
Operation
Memory
Addressing
for
Manual
Operation
Manual Data
Input
to Addressed
Memory
Location
Checking
the
Contents
of
Any
Address
In
Core
Memory
Loading
Data
Under
Program
Control
Initializing
the
System
Program Loading Operation
Loaders
Read-In-Mode
(RIM)
Loader
Binary
(BIN)
Loader
Off-Line
Teletype Operation
Display
System
Operating
Procedures
VR14
Display
Operation
Guidelines for VC8-E
Interfacing
for
Oscilloscopes
and XY Plotters
lntensification Pulse
X and
Y
Outputs
Drive
Capabilities
External
Controls
Ground
Loops
VC8-E
Restrictions
CHAPTER 4
PRINCIPLES
OF OPERATION
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
Section 1
System
Operation
Introduction
Analog
Data
Input
to the
A/D
Converter
A/D
Converter
(ADB-EA)
Buffered
Digital
I/O
(D
R8-EA)
Real-Time
Programmable
Clock
(DK8-EP)
Point-Plot
Display
Control
(VC8—E)
33 ASR
Teletype
HQ
Power
Supply
Page
3-1
3-1
3-5
3-6
3-6
3-6
3-6
3-6
3-6
3-6
3-7
3-7
3-7
3-8
3-9
3-9
3-1 1
3-1
2
3-1
3
3-1
3
3-1
5
3-1
5
3-1
5
3-1
5
3-1
5
3-1
6
3-1 6
4-3
4-4
4-4
4-4
4-6
4-6
4-9
4-9

4.2
4.2.1
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10
4.2.11
4.2.12
4.3
4.3.1
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.4
4.4.1
4.4.2
4.4.2.1
4.4.2.2
4.4.2.2.1
4.4.2.2.2
4.4.2.2.3
4.4.2.3
4.4.2.4
4.4.2.5
4.4.2.6
4.4.2.7
CONTENTS
(Cont)
Section 2
Analog-To-Digital
Converter
(AD8-EA)
introduction
A/D
Converter
Block
Diagram
A/D
Converter Detailed
Logic
Device
and
Operation
Select
Logic
External
A/D
START
and Time
Pulse
Logic
interrupt, Skip,
and Control
Logic
Status
Register
BUSY
Flip-Flop
MUX
Register
Logic
Enable
Register
Analog
Buffer and
Sample
and Hold Circuits
A/D
Converter Internal
Clock
Analog
Switches
Comparator
A/D
Buffer and
Shift
Register
Positive and
Negative
References
Section 3
Analog
Preamplifier
and
Multiplexer
Introduction
Analog
Preamplifier
and
Multiplexer Expander
Block
Diagram
Analog Preamplifier
and
Multiplexer
Expander
Detailed
Logic
Differential
Amplifiers
Channel
Decoder and
Analog
Switches
Reference
Voltages
Optional Multiplexer
Configurations
Section
4
Point-Plot
Display
Control
(VC8-E)
Introduction
Functional Block
Diagram
Description
Point-Plot
Display
Control
Detailed
Logic
Device
and
Operaiton
Select
Logic
Enable/Status
Register
DONE
Logic
interrupt
Enable
Logic
Channel Select
Logic
Intensity
Pulse Generation
Data Gates
Holding Registers
Analog
Switches and
Summing
Amplifier
Positive Reference
Source
Page
4-1 1
4-14
4-17
4—1
7
4-17
4-17
4-21
4-21
4-21
4-23
4—23
4—26
4—26
4-31
4-31
4-33
4-35
4—35
4—36
4-36
4-37
4—39
4-39
4-43
4-46
4-49
4-49
4-49
4-49
4-51
4-51
4-51
4-51
4-51
4-53
4-54

4.5
4.5.1
4.5.2
4.5.2.1
4.5.2.2
4.5.2.3
4.5.2.4
4.5.2.5
4.6
4.6.1
4.6.2
4.6.2.1
4.6.2.2
4.6.2.3
4.6.2.4
4.6.2.5
4.6.2.6
4.6.2.7
4.6.2.8
4.6.2.9
4.7
4.7.1
4.7.1.1
4.7.1.2
CONTENTS
(Cont)
Section
5
Buffered
Digital
l/O
(DR8-EA)
Introduction
Buffered
Digital
I/O
Functional Block
Diagram
Buffered
Digital
I/O
Detailed
Logic
Device Select
and
Operation
Decoder
Interrupt
and
Skip
Logic
Input Register
and
Control
Logic
Output Register
and Control
Logic
AC Bus
Register
Section 6
Real-Time
Programmable
Clock
(DK8-EP)
Introduction
Block
Diagram
Discussion
Detailed
Logic
IOT Decoder
Logic
Clock Enable
Register Logic
Clock
Rate
Select
Logic
Load Buffer
Register Logic
Clock
Buffer/Clock
Counter
Logic
Overflow
Flip-Flop Logic
Interrupt/Skip
Logic
Input/Overflow
Status
Logic
Schmitt
Trigger Logic
Section
7
High Quality
Power
Supply
Introduction
High Quality
Power
Supply Operation
Regulator
Circuitry
Current—Limiting
Circuitry
CHAPTER
5
MAINTENANCE
5:1
5.1.1
5.1.1.1
5.1.1.2
5.1.1.3
Section
1
Preparation
for Maintenance and Maintenance
Requirements
Equipment
Programs
Display
Line on VR14 or User
Oscilloscope
Display
Converted Value
in AC
(AD8—EA
only
or
channel
0
of
AM8-EA)
Display
Converted
Value in MO with
AM8-EA
vi
Page
4-57
4-57
4-59
4—59
4-59
4-59
4-61
4-64
4-6 5
4-66
4-7
1
4-7
1
4-7 1
4-7
1
4-74
4-7
5
4-80
4-80
4-82
4-84
4-87
4-87
4-87
4-89
5-3
5-4
5—4
5-4
5-5

5.1.1.4
5.1.1.5
5.1.2
5.1.3
5.1.3.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.2.9.1
5.2.9.2
5.2.9.2.1
5.2.9.2.2
5.29.2.3
5.29.2.4
5.2.9.2.5
52926
52.9.27
5.2.10
5.2.10.1
5.2.10.2
5.2.10.3
5.2.10.4
5.2.10.5
5.2.10.6
5.2.10.7
5.2.10.8
5.3
5.3.1
5.3.2
CONTENTS
(Cont)
Display
Converted Value of
A/D
on
VR14
Start
A/D
Converter with Real—Time Clock
Preventive Maintenance
Inspections
Scheduled
Maintenance
Weekly
Preventive
Maintenance Schedule
Section
2
Corrective Maintenance
Maintenance
Procedures
Preliminary
Investigation
System Troubleshooting
Logic
Troubleshooting
Circuit
Troubleshooting
Repairs
and
Replacements
Validation Tests
Log
Entry
CPU
Troubleshooting
Memory Troubleshooting
Memory
Resistance Checks
Memory
Circuit Variables
Field Select
Jumpers
Strobe
Adjustment
Slice
Level
XY Current Control
(G227)
Temperature
Tracking
Inhibit Current
Strobe
Setting
Procedure
H724 Power
Supply
Troubleshooting
Procedures
Overcurrent
Protection
Hold-Up
Time
Thermal Protection
Contact
Protection
input Switching
POWER ON/OFF
Switch
Adjustment
Parallel
Operation
Large Configuration
Section
3
Teletype
Maintenance
Introduction
Special
Tools
Programs
vii
Page
5-5
5-6
5-6
5-7
5-8
5-9
5-9
5-9
5-1 1
5-1
1
512
5-15
5-1 5
5-16
5-1 7
5-19
5—20
5-21
5-21
5-21
5-21
5-21
5-21
5-21
5-23
5-24
5-24
5-24
5-24
5-24
5-24
5-24
5-24
5-25
5-25
5-25

5.4
5.4.1
5.4.1.1
5.4.1.2
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.5
5.5.1
5.5.2
5.6
5.7
CHAPTER
6
6.1
6.2
6.3
APPENDIX A
A.1
A2
A3
A.4
A5
A6
APPENDIX
B
CONTENTS
(Cont)
Section
4
System
Calibration
Calibration of the
LAB-8/E
Options
A/D
Converter
(ADS-EA)
Calibration Procedure
Minor
Calibration
Major
Calibration
Common
Mode
Rejection
(CM R)
Calibration
Calibration of the
Point-Plot
Display
Control
(VC8-E)
Using
VR14 or
Tektronix
602
Display
VC8—E Calibration
Procedure
Without
a
VR14 or VR03
Analog Preamplifier
and
Multiplexer
(AM8—EA)
Calibration Procedure
VR14 Calibration
Calibration
of the Tektronix
602
Using
the
VCB-E
Section
5
Preventive Maintenance
Procedures
Preventive
Maintenance
Weekly
Tasks
Preventive
Maintenance
Tasks
Section
6
Corrective
Maintenance
Corrective Maintenance
Procedures
Section
7
Special
Troubleshooting
Procedures
Test Clock
(M499)
LAB-8/E
SYSTEM SPARE PARTS
Introduction
LAB-8/E
Central
Processor
(PDP-8/E
and 33 ASR
Teletype Spare
Parts)
Basic
LAB~8/E
System
Spare
Parts
IC CIRCUIT
DESCRIPTION
SN 74193 IC
DEC
17090 IC
DEC 7475
IC
DEC
749010
DEC 7470
IC
DEC 74197 IC
LAB-8/E
MODULE JUMPER REQUIREMENTS
viii
Page
5-27
5-27
5-27
5-28
5-29
5—29
5-31
5-32
533
5-34
5-35
5-35
5-35
5-37
5-39
6-1
6-1
6-1
A-1
A-1
A-4
A-4
A-4

Figure
No.
1-1
1-2
2-1
2-2
2-3
2-4
2—5
2-6
2-7
2-8
2-9
3-1
3—2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
4-1
4—2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-1 1
4-12
4-13
4-14
4-15
4-16
4-1
7
4-1 8
4-19
4-20
4-21
4-22
4-23
ILLUSTRATIONS
Title
LAB-8/E
Basic
System
LAB-8/E
Rack-Mounted Version
Single-Ended
Measurement
Connection
Differential
Input
Measurement Connection
AM8—ED
Analog
Input
Panel
AM8-EC
Analog
Input
Panel,
Front and Rear View
Front View of DB-255 Connector
and
Telephone
Plug
Edge
Connector Installation
(top
view)
Analog
Inputs
for
Accuracy
Check
Negative
Input
Checkout
Oscilloscope
Display
for
Ramp
Test
Programmer’s
Console
Teletype
Model 33
ASR
Console
Teletype Keyboard
Loading
Data
Under
Program
Control
Loading Programs
with Mass
Storage
Devices
Loading
the
RIM Loader
Checking
the
RIM Loader
Loading
the BIN Loader
Loading
a
Binary
Tape Using
BIN
VR14
Display
Oscilloscope
LAB-8/E
Block
Diagram
A/D
Converter
Flow Chart
Buffered
Digital
I/O
Flow
Chart
Real-Time
Programmable
Clock
Flow
Chart
Point-Plot
Display
Control
Flow
Chart
Analog-to-Digital
Converter
Block
Diagram
Enable/Status
Register
Contents
A/D
Converter
Functional
Block
Diagram
A/D
Buffer and
Switch
Logic
Device and
Operation
Select
Logic
Interrupt,
Skip,
and
Control
Logic
Interrupt Timing
Diagram
MUX
Register Logic
Enable
Register Logic
Analog
Buffer and
Sample
and Hold Circuits
Signal
at
AA1
with
a
Slow
Ramp
Input
to the
A/D
Converter
Analog-to-Digital
Converter
Internal
Clock
Analog-to-Digital
Converter Internal
Timing
Diagram
A/D
Converter
Shift
Register
and Data
Buffer
Analog
Switches
Comparator
Circuits
A/D
Buffer
Signal
Summing
Junction
and
Comparator Output Signals
Page
1-2
1-8
2-2
2-2
2-3
2-3
2-3
2-1 5
2-20
2-22
2-25
3-1
3-2
3-5
3-8
3-9
3-10
3-10
3-1
1
3-12
3-13
4-3
4-5
4-6
4-7
4-8
4—1 1
4-12
4-14
4-1 7
4-18
4-19
4-20
4-22
4-24
4-25
4-26
4-27
4-28
4-29
4—30
4-31
4-32
4-33

Figure
No.
4—24
4-25
4-26
4—27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-35
4-36
4-37
4-38
4-39
4-40
4-41
4-42
4-43
4-44
4-45
4-46
4-47
448
4-49
4-50
4-51
4-52
4-53
4-54
4-55
4-56
4-57
4-58
4-59
4—60
4—61
4-62
4-63
4-64
4—65
ILLUSTRATIONS
(Cont)
Title
Signals
at AA1 and
Collector
of
020 on the A841
Module
Positive
and
Negative
References
Analog
Preamplifier
and
Multiplexer
Block
Diagram
Analog
Preamplifier
and
Multiplexer
Expander
Functional
Block
Diagram
Differential
Amplifier
Channel
Decoder
and
Analog
Switches
AM8-EA Reference
Voltages
Point-Plot
Display
of Coordinate
Data
Point-Plot
Display
Control
Block
Diagram
AC
Input
Data
Format
Analog
Switches and
Summing Amplifier
One
Analog
Switch
and
Summing
Amplifier
Device
and
Operation
Select
Logic
Enable/Status
Register
Enable/Status
Register
Word
Contents
DONE and
Interrupt
Logic
intensity
Pulse
Logic
Data
Gates
X-Axis
Holding Register
Analog
Switches and
Summing
Amplifier
+5V
Reference
Buffered
Digital
l/O
Block
Diagram
Device
Select and
Operation
Decoder
Logic
Interrupt
and
Skip
Logic
lnput
Buffer
Register
and
Logic
Output Register
and
Logic
AC Bus
Register
DK8-EP
Functional Block
Diagram
lOT
Decoder
Logic
Clock Enable
Register
Logic
Clock Rate Select
Logic
Load Buffer
Register Logic
Load Buffer
Register
Timing
NOT
LAST TRANSFER
Logic
Clock
Buffer/Clock
Counter
Logic
Clock
Buffer/Clock
Counter Control
Signals
OVERF LOW
Flip—Flop
Logic
Interrupt/Skip Logic
Input/Overflow
Status
Logic
Schmitt
Trigger
Logic
DK8-EF Front
Panel Schematic
High
Quality
Power
Supply
Schematic
Page
4-33
4-34
4-35
4-36
4-37
4-38
4-39
4-43
4-44
4-44
4-45
4-45
4-48
4-50
4-51
4-52
4-53
4-54
4-54
4-55
4-55
4-57
4-60
4-61
4-62
4-63
4-63
4-67
4—69
4-72
4-73
4-74
4—76
4-77
4-78
4-79
4-81
4-82
4-83
4-84
4-85
4-88

Figure
No.
4-66
4-67
4-68
4-69
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
A-1
A-2
A-3
A-4
A-5
A-6
A-7
Table
No.
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-1
1
2-12
2-13
2-14
2-15
2—1 6
2-17
ILLUSTRATIONS
(Cont)
Title
'
Current
Limiting Circuitry
Regulator
Circuitry
Power
Mate
(20885-8)
HO
Power
Supply
Deltron
(C13495)
HQ
Power
Supply
System
Troubleshooting
Flow Chart
IC Location
IC Pin Location
Memory
Troubleshooting
Flowchart
Memory
Waveforms
Setting
of
Strobe
AD8-EA Common
Mode
Rejection
Calibration
Connection
Teletype
Signal
Waveform
and
Bit
Relationship
for the Character
U
74193
IC
Logic Diagram
74193 IC
Pin
Location
(Top
View)
DEC
1709C
IC
Illustrations
DEC 7475 IC
Illustrations
DEC 7490 IC
Illustrations
DEC
7470
IC
Illustrations
DEC
74197
IC
Illustrations
TABLES
Title
LAB-8/E
System
Specifications
LAB-8/E
Handbooks,
User’s
Manuals,
Maintenance
Manuals,
and
Engineering Drawings
Summary
of
Installation
Functions
AM8-ED and AM8-EC
Analog
Panel Pin
Connections
Analog
Connection
Using
7008533 Cable
BC08J-X Connection and
Bit
Assignments
Connections
for
DR8—EB Panel
Assembly
Real-Time
Programmable
Clock Connections
VCB-E Cable
Connections
AD8-EA
Accessory
and
Component
List
AD8-ES
Accessory
and
Component
List
AM8-EA
Accessory
and
Component
List
AM8—EC
Accessory
and
Component
List
AM8—ED
Accessory
and
Component
List
DK8—EF
Accessory
and
Component
List
DK8-EP
Accessory
and
Component
List
DK8-ES
Accessory
and
Component
List
DR8-EA
Accessory
and
Component
List
DR8-EB
Accessory
and
Component
List
xi
Page
4-88
4-89
4-90
4-91
5-1 0
5-1 3
5-1 3
5-1
8
5-20
5-22
5-29
5-38
A-2
A-3
A-3
A-6
A—7
A-8
A-9
Page
1-4
1-9
2-1
2-3
2—4
2-4
2-5
2-7
2-8
2-8
2-9
2-9
2-9
2-9
2-10
2-10
2-10

Table
No.
2-1 8
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
3-1
3-2
3-3
3-4
3-5
3-6
4-1
4-2
4-3
4-4
4-5
4-6
4-7
48
4-9
4-1 0
4-1 1
4-1
2
4-1 3
4-14
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-1 0
5-1 1
TABLES
(Cont)
Title
DR8—EC
Accessory
and
Component
List
yC8-E
Accessory
and
Component
List
VM03
Accessory
and
Component
List
Recommended
LAB-8/E
Module
Installation
Positions
High
Quality
Power
Supply
Parameters
Switch
Requirements
for
VCB-E
Modules
VM03 Tektronix
602
Modification
Kit
Parts List
LAB-8/
E
Acceptance
Test
Diagnostics
A/
D
Converter
and
Analog Preamplifier
and
Multiplexer
Acceptance
Test
Switching
Points
and Theoretical
Voltage Readings
Theoretical
Voltage
and
Reading
in the AC
Programmer’s
Console Control and Indicator
Functions
Special Keyboard
Functions
RIM
Loader
Programs
VR14
Input
Voltages
VR14 Controls
Unit
Top
Panel Control
Settings
Enable/Status
Register
C-Line
Logic
Levels
MUX
Register
Contents and Look-Ahead Bits
Applied
Voltages
and Octal
Equivalents
Resistors
for
Changing
Input
Configuration
AM8—EA
Configuration
Change
Parts List
Point~PIot
Display
Control
Enable/Status
Register
IOT
Device Code
DK8-EP IOT Instructions
Clock Enable
Register
Enable
Signals
Frequencies
Selected
by
Rate
Enable Bits 3—5
Control
Signals
for Clock
External and Internal
Transfers
High
Quality
Power
Supply
Parameters and
Specifications
Side Connector for
H0 Power
Input
and
Output
Maintenance
Equipment
Processor
Preventive
Maintenance
Schedule
(3
months or
500
hours)
Processor
Troubleshooting
Memory
Data
Errors
——
Possible Causes
Memory
Module
Test
Point
Voltage
Levels
Memory
Circuit Variables
H724 Power
Supply
Parameters
Component Troubleshooting
Aid
for
H724 Power
Supply
POWER
ON/OFF
Switch
Adjustment
Teletype
Maintenance
Tools
EDC
Connection
to A841 Module
xii
Page
2-1 1
2-1 1
2-1 2
2-1 2
2-14
2-16
2-1
7
2-19
2-20
2-21
2-22
3-2
3-5
3-10
3-13
3-14
3-14
4-1 3
4-20
4-23
4-32
4-40
4-40
4-46
4-59
4-68
4—70
4-70
4—78
4-87
4-87
5-3
5—7
5-16
5—1 9
5-19
5-20
5-23
5-23
5-24
5-25
5-28

Table No.
5-12
5-13
5-14
5-15
5-16
5-17
6—1
6-2
6-3
6-4
6-5
TABLES
(Cont)
Title
EDC
Voltage
and
AC
Readings
Major
Calibration
Voltages
and AC
Readings
AM8-EA Calibration
Connections
Gain and Bias Potentiometers
Connections
of
Teletype
Cable
Teletype
Cabling,
Fusing,
and
Test Points
Analog-To-Digital
Converter
(ADS-EA)
Recommended
Spare
Parts
Point-Plot
Display
Control
(VC8—E)
Spare
Parts
Analog Preamplifier
and
Multiplexer Expander
(AM8—EA)
Recommended
Spare
Parts
Buffered
Digital
I/O
(D R8—EA)
Recommended
Spare
Parts
Real—Time
Programmable
Clock
(DK8-EP)
Recommended
Spare
Parts
xiii
Page
5—28
5-29
5-33
5-34
5-37
5-37
6-1
6-2
6-2
6-2
6-3

CHAPTER
1
INTRODUCTION
1.1
PURPOSE
OF MANUAL
This manual
provides
the user with
the
installation
procedures,
theory
of
operation,
and maintenance
procedures
necessary
to
install
and
operate
the
LAB-8/
E
System
manufactured
by
Digital
Equipment
Corporation.
The
theory
of
operation
and maintenance
procedures
for the
LAB-8/
E
processor
are
contained
in
the
PDP-8/E
Maintenance
Manual,
Volume /.
When
operating
and
performing
maintenance
on the
LAB-8/
E,
the user should
be
familiar with
Chapter
4 of
the
PDP-8/E
manual. This manual deals with
the
options
that
have
been added
to
the
PDP-8/E
to
form the
LAB-8/E
System.
Paragraph
1.4
contains
a
list
of
companion
documents to
this
manual
and
other
documentation
for
the
LAB-8/E.
1.2
SYSTEM FEATURES
The
LAB-8/
E
System
performs
arithmetic
calculations,
controls machintD
operations,
makes
on-line
measurements
of both
analog
and
digital
information,
displays
data on an
oscilloscope,
and
stores
large quantities
of data
for
future use
and/or
modification.
The user
may
use
control
tapes
provided
by
Digital,
or
write
his own
programs
to
shape
the
LAB-8/
E to
his
own needs and to
perform
sophisticated handling
of
analog
or
digital
data.
The
LAB-8/E
is a
truly sophisticated
system
allowing flexibility
for the user in data
acquisition
and
processing.
The
LAB-8/E
design
enables the
user to
purchase
the
basic LAB-8/E
and to add
on
options
as
requirements
in-
crease. The basic
system
comprises
the
following:
a. A
PDP-8/
E
general purpose
12-bit
digital
computer
with a
basic 4096-w0rd
memory
and a
1.2-us
cycle
time.
b. A
33 ASR
Teletype®,
10-bit
l/O
device with a
paper-tape
reader and
punch.
c. A
laboratory
mounting
panel
with
precision
power
supply
for
use with
LAB-8/E
peripherals.
d.
A
10-bit
Analog-to-Digital
Converter with
sample
and hold
circuitry
and
optional
preamplifier
and
multiplexer expander.
e. A
10-bit
Point-Plot
Display
Control for the
graphical display
of
data
on an
oscilloscope.
f. A
Real-Time Clock with
five
programmable
ranges
from
1
us
per
count
to
10 ms
per
count,
plus
three
Schmitt
triggers.
Expansion
is
easily
accommodated
through
a
two—way bus,
called
OMNIBUS®,
which all LAB-8/E
modules
plug
into
directly
or
indirectly. Figure
1-1
shows the
basic
PDP-8/E and
the
options added,
shown inside the
dotted
lines,
to
form the
basic
LAB-8/
E.
One OMNIBUS contains 20
non-dedicated slots
that can contain
up
to
®Teletype
is a
registered
trademark
of
Teletype Corporation.
OMNIBUS is a
trademark of
Digital
Equipment Corporation.
1-1

Z‘I
I—
ANALOG
CARRY
INPUT
PANEL
I
AM8-EC
I
ENABLE
OR
AMa—
ED
I
ANAILOO
I
DRB-EB
OKs—E1.-
I
I?
RFI
REOVIPRTgR
LOAD
SEgISTERS
MULTIPLEX
INPUT/
INPUT/
SHIELD
C L
LOAD
EXPANDER
OUTPUT
OUTPUT
(M849)
LOAD
AM8-EA
(A232)
PANEL
PANEL
DATA
|
1
T 1 1
1
TI
CONTROLQ
I
AglAIéIOPA‘lr-O
A/D
BBIEIETIIAED
REALTIME
CONTROLS
SCHMITT
I
TIMING
LOAD
Mo
LMD
CONTROL
CLOCK
TRIGGER
aus
CONVERTER
DATA
-
ADS-EA
I/O
DRe-E
DK8-EP
‘
DKB-EP
GENERATOR
MEMORY
REIéIchERs
I
“73‘“
(A841)
(A231)
(M863)
(M860) (M518)
I
(M833)
(MM8—3) (M8310)
(M8300)
I
TIMING
I
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ANALOG
POWER
DISPLAY
HO
HO POWER
I
POWER
BUS TELETYPE
PROGRAMMERS
CONVERTER
CONTROL
CONTROL
POWER
——>
T0 LAB 8/E
SUPPLY
LOADs CONTROL
CONSOLE
_
_
KCB-E
I
vce
E
(M885)
DATA
VC8
E
(M869)
MODULES
I
(H724) (M832)
(M865)
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EE-OIBB
Figure
1-1
LAB-8/E
Basic
System

20
PDP-8/E
or
LAB-8/E
options.
The user can
add one
or
more additional
OMNlBUS
modules to
accommodate
more
options,
if
required.
Three
categories
of
options
are
provided
with the
LAB-8/
E:
internal
options,
OMNIBUS
options,
and external
options.
Internal
options
are
units,
such as
Extended
Memory,
and
Extended Arithmetic
Element,
that extend
the
capability
of the
processor
but
do
not control
peripherals.
OMNIBUS
options
include internal and external
options
that
plug
directly
into the OMNIBUS. External
options
are
units
that
indirectly plug
into the OMNlBUS
through
an
l/O Bus
Adapter
interface.
The
specifications
for the
LAB-8/E
Central Processor
and
options
are shown in
Table 1-1.
The
options
are
de-
scribed
in the
following paragraphs.
1.2.1
Analog-to-Digital
Converter
(ADS-EA)
The
Analog-to-Digital
(A/D)
Converter consists
of
the A841 and
A231 modules.
The A841 module contains
analog circuitry,
including
the
A/D
weighing
switches,
comparator,
and
sample
and hold. The A231 module
contains all the control
logic
for
the
A841
module. The ADS-EA
receives
a $5 Vdc
signal
and
produces
a 9-bit
+
sign
digital
word
representing
the
input.
The two
modules are
joined by
an
H851
Edge
Connector.
1.2.2
Analog
Preamplifier
and
Multiplexer
(AM8-EA)
The
AM8-EA
is
a
single
A232
quad
module
containing eight
analog
preamplifiers
and
eight
multiplexer
channels
that select the
output
of
one
preamplifier
to
be
applied
to the
A/D
converter.
An
additional module
expands
the
multiplexer
to
16
channels.
Input
to the AM8~EA
is
:1
V
differential and the
output
is
:5V
single-ended
to
the A841 module
of
the AD8-EA.
1.2.3 Point-Plot
Display
Control
(VC8—E)
The
VC8-E
consists of
the
M885 and
M869 modules. The
M885
module receives 9 bits
+
sign
of
digital
data and
converts it
to $5
Vdc
voltage
to
be
applied
to
the
oscilloscope display.
The M869
module
contains all the control
logic
to
control the
Digital-to-Analog
(D/A)
converter.
1.2.4 Buffered
Digital
l/O
(DR8-EA)
The DR8-EA
consists
of one M863 module. It
can
provide
12
digital
inputs
and
12
digital outputs
for the LAB—
8/
E
and can be used
to sense external events. The
inputs
and
outputs
are TTL
compatible; ground
(0V)
represents
logical
true and
high
(+3V)
represents logical
false.
1.2.5 Real-Time
Programmable
Clock
(DK8-EP)
The DK8-EP consists
of
the M860
and
M518 modules. The M518 module contains the
input logic
and Schmitt
triggers.
The M860
module contains the control
logic,
registers,
and IOT
decoding logic.
The DK8-EP
provides
a
programmable
time
base
that allows the user
to
control
and/or
record internal and external events.
It
can be
used
to
measure time
between
events,
record
number
of
events
in
a
given
time,
or initiate
repetitive operations
at
specified
intervals
of
time.
NOTE
The
following panels
are
single-width
or
double-width
modules which are mounted
in
the H945
option
cab-
inet,
Nuclear Installation Module
(NIM)
Binary
Load-
er
(BIN),
for
connecting
inputs
and/or
outputs
to the
LAB-8/
E
System.
1-3

1.2.6
Analog
Input
Panels
(AM8—ED
and
AM8-EC)
The AMS-ED and AM8—EC
panels
are used
to
supply inputs
to the
analog multiplexer
and are
mounted in
the
H945 cabinet. The
AM8~ED
has
two DB-258
25-pin
connectors
with
matching plugs.
The AM8—EC has four
inputs
from
potentiometer
channels
0
through
3.
As on the
AM8-ED,
channels
48
through
178
are
supplied
on
the
DB-25S.
1.2.7
Real-Time
Programmable
Clock
Input
Panel
(DK8-EF)
The DK8—EF
panel
has
inputs
for the Schmitt
triggers.
It also
provides
connections
for EXT
CLOCK
or EXT
STA RT
signals.
1.2.8
Digital
l/O
Panel
(DR8-EB)
The
DR8-EB
provides
a
front
panel
assembly
with two M904
modules,
with
connections
for
input
and
output
to
the DR8-EA Buffered
Digital
I/O.
Table
1-1
LAB-8/
E
System
Specifications
Equipment
Specifications
Central
Processor
Processor
Speed
Two
memory
cycles:
a.
Fast
cycle
accomplishes
a
FETCH,
Internal
IOT,
or
DEFER
(non-Auto
Index)
in
1.2
Ms.
b. Slow
cycle
accomplishes
(after
FETCH)
an instruc—
tion
execution,
or
DEFER
(Auto
Index)
in
1.4
ps.
Instruction Execution
Time
(MRI
only)
The instruction
execution
time,
beginning
with the instruc-
tion
completely
executed,
requires
one
fast and
one slow
memory
cycle,
or
2.6
us.
Word
Length
12
bits
Addressing
Direct
memory
addressing
is controlled on
front
panel
or
through
the Data Break
system. Programmed
addressing
is
accomplished
as a function
of
software. 200 octal
memory
locations
may
be
directly
accessed
(except
when on
page
0)
by
the
program
during
any
one
memory cycle.
Program
Loading
Programs
may
be
loaded
by
Read-ln-Mode
(RIM)
or
Binary
Loader
(BIN).
RIM is read into
memory using toggle
switches
on front
panel.
BIN
is
a
program
used
to
load
other
programs.
Input/Output Capability
Three
types
of
input/output
transfers
(IOTs)
are
provided:
a.
Programmed
input/output
or
transfers
b.
Programmed
Interrupts
0. Data
Break
Data Break is a method used
to
read out
of,
or write
into,
a
block
of
memory
during
normal
processing.
(continued
on next
page)
1-4

Table
1-1
(Cont)
LAB-8/
E
System
Specifications
Equipment
Specifications
Central
Processor
(Cont)
Memory
Capacity
Power
Requirements
Power
Requirements
(Teletype)
Environment
Cable
Requirements
Instructions
4096 12-bit
word
memory
locations
which can be
expanded
to 32K of
memory
95—130
Vac,
47—63
Hz,
approximately
6A
single-phase,
or
185—250
Vac,
47—63
Hz,
approximately
3A
single-phase
with 450W
power dissipation
115
i
10%
Vac,
60
Hz
i
0.45
Hz,
or
230 i10%
Vac,
50
Hz
i
0.50
Hz,
2A line
current
drain,
150W
power
dissipation
The
LAB-8/E
is
designed
to
operate
at 0°C to
55°C
with
a rel-
ative
humidity
of
10%
to
95%
(without
condensation).
The
LAB-8/E I/O
cable is a combination
shielded
and
coaxial
cable. The maximum
length
of
Data Break
l/O
Bus cable is
30
ft,
using
a coaxial cable. Maximum
length
of
the
pro-
grammed
l/O
Bus is 50
ft,
using
a
coaxial cable.
Eight
basic instructions constitute the instruction set:
AN D
0000
Logical
AND
TAD 1000 2’s
complement
add
lSZ 2000 Increment
and
skip
if 0
DCA
3000
Deposit
and clear AC
JMS 4000
Jump
to subroutine
JMP
5000
Jump
to another
memory
location
IOT 6000
In/out
transfer
OPR
7000
Operate
A/D
Converter
(ADS-EA)
Input
Voltage
lnput Impedance
Output
Format
Common Mode
Rejection
Resolution
Accuracy
Conversion
Rate
Power
Requirements
Temperature
StabilityH
i5.0 Vdc
Differential.
Plus
input
greater
than 10
M52;
negative input
with
jumper,
greater
than 10
k9
(negative input
intended for
use as an external
ground
sense;
i.e., impedance
from
negative
lead to
computer ground
< 20 Q for
given
common mode
rejection
(CMR)
specification).
Parallel
data,
10
bits,
right justified,
and
sign
extended 2’s
complement
At least 35 dB at
60
Hz. Common mode
voltage
less than
5V to
ground
0.1%
(1
bit
in
1024)
0.2%
of
full
scale*
50
kHz
maximum
i5
Vdc
i10%1A,+15
Vdc
i
0.1% 150
mA,
-15 Vdc
i
0.1%
150 mA
0.01%
full
scale/°C
(continued
on next
page)
1-5

Table
1-1
(Cont)
LAB-8/
E
System
Specifications
Equipment
Specifications
Analog
Multiplexer
(AM8-EA)
Input
Voltage
Input Impedance
Common Mode
Rejection
Overload Protection
Overload
Recovery
Time
Frequency Response
Leakage
Current
*
Temperature Stability*
Output
Differential
i
1V;
16
channels,
maximum
Non-inverting input
is 70
k9 in
parallel
with 300
pF.
In—-
verting
input
is 35 k9 in
parallel
with 300
pF.
Greater than 25
dB,
35 dB
typical
:67V
from fault line
8
us
Flat
from 0
to 30
kHz,
-3 dB at 60
kHz
Negligible
at
70k
impedance
0.01%
full
scale/°C
:5V
full
scale,
single-ended,
0.2%
accuracy*
Point-Plot
Display
Control
(VCB-E)
Input
Format
Output Voltage
Resolution
Slewing
Speed
Driving Capability
Power
Requirements
2
Axis
Intensity
Pulse
10 bits
of
data
in
2’s
complement
format
+5.01
to
~
5.01
i
0.1
Vdc offset
(adjustable)
10 mV
i
2.5 mV
1.25
V/ps
Capable
of
driving
loads
greater
than
1 k9
minimum,
in
parallel
with 5000
pF;
l.e.,
100 ft of
50
pF/ft
cable
+5
Vdc= 10%
1A,
+15
Vdc:L 0.1% 150
mA,
-15
Vdc
i'
0.1%
150 mA
1
us,
+
4V to
-2V
or
+
4V to -10V
positive-
or
negative-going
Buffered
Digital
l/O
(DR8-EA)
Programmable Input
and
Output
Input
Output
Input
Levels
Output
Levels
Power
Requirements
12
parallel
bits
or 12
independent
bits selected
by
jumpers.
12
parallel
buffered bits
or
12
independent
bits
TTL
compatible
levels.
Input
lines are
clamped
at
+5V
for
positive input protection. Input
source must
sink
3 mA
in
the 0
(true)
state.
TTL
compatible
levels.
Outputs
can
sink 20 mA in the 0
(true)
state.
+5V,
2.25A
(worst
case)
Programmable
Real-Time
Clock
(DK8-EP)
Control
Schmitt
Triggers
20
MHz
crystal
controlled
Three threshold detectors that
accept pulse
or
varying analog
inputs
(i5V variations)
(continued
on
next
page)
1-6