Epson SED1751 User manual

SED1751

SED1751
MLS Driver Chip Set EPSON i
Technical Manual
Contents
OVERVIEW...................................................................................................................................5-1
TERMINAL FUNCTIONS ..............................................................................................................5-3
ABSOLUTE MAXIMUM RATINGS................................................................................................5-9

SED1751
MLS Driver Chip Set EPSON 5–1
Technical Manual
OVERVIEW
Description
The SED1751 is an 120 output, 3-level low-resistance common (row) driver suitable for high-quality,
high-response-speed MLS (Multi Line Selection) driving.
The SED1751 receives signals from LCD controllers such as the SED1335, and when used is used in
conjunction with the SED1580, can be used to structure a 4-line MLS drive.
The SED1751 uses a slim-chip form that is useful for making LCD panels slimmer. It also supports reduced
logic system voltage operation, making it suitable for a broad range of applications.
The SED1751 has a pad layout supporting easy mounting, and supports bi-directional selection of driver
output order, and has the highest use efficiency for 1/240 and 1/480 duty panels.
Features
• LCD driver outputs......................................120
• Low output ON resistance
• High duty drive supported ...........................1/480 (Reference value)
• Broad range of LC drive voltages ...............+ 14 to + 42 V (VCC = 2.7 to 5.5 V)
• Output shift direction pin select is possible
• Can be switched between 100 and 120 outputs
• Non-biased display OFF function
• Logic system power source .........................2.7 V to 5.5 V
• LC power source offset bias can be adjusted relative to the VDDH and GND levels
• Slim chip shape
•D
0B .............................................................. Au Bump die
•T0A ...............................................................TCP
Pad Layout
Y
X
131
1
132
155
60
35
59
36
Chip size 12.19 mm ×2.38 mm
Pad pitch 80 µm (Min.)
Chip thickness 525 µm ±25 µm
1) Au Bump Specifications (SED1751DOB) Reference Values Only
Au vertical bump
Parallel to Scribe ×Perpendicular to Scribe ±Tolerance
Bump Size A 60 µm ×75 µm ±4 µm (Pad No. 1 to 35, 60 to 131)
Bump Size B 80 µm ×50 µm ±4 µm (Pad No. 36 to 59, 132 to 155)
Bump height 17 to 28 µm (The details specified in the acceptance specifications.)

SED1751
5–2 EPSON MLS Driver Chip Set
Technical Manual
Pad Coordinates
1VDDHL –5812 –1012
2+V1L –5717
3VCL –5622
4–V1L –5527
5 GNDL –5432
6 SHL –5094
7 SEL –4869
8VCC –4531
9 LSEL –4192
10 DOFF –3828
11 FR –3081
12 CSEL –2336
13 LP –1998
14 DM –1162
15 CIO2 –755
16 DM –347
17 DM 0
18 DM 347
19 CIO1 755
20 DM 1162
21 YD 1998
22 DM 2336
23 DM 2674
24 DM 3081
25 DM 3489
26 DM 3828
27 F1 4192
28 DM 4531
29 F2 4869
30 TEST1 5094
31 GNDR 5432
32 –V1R 5527
33 VCR 5622
34 +V1R 5717
35 VDDHR 5812
Pin Name X Y Pin Name X Y
36 COM1 5945 –902
37 COM2 –822
38 COM3 –742
39 COM4 –662
↓↓ ↓ ↓
57 COM22 5945 778
58 COM23 5945 858
59 COM24 5945 938
60 COM25 5709 1034
61 COM26 5549 1034
62 COM27 5389 1034
↓↓ ↓ ↓
93 COM58 429 1034
94 COM59 269
95 COM60 109
96 COM61 –109
97 COM62 –269
98 COM63 –429
↓↓ ↓ ↓
129 COM94 –5389 1034
130 COM95 –5549 1034
131 COM96 –5709 1034
132 COM97 –5945 938
133 COM98 –5945 858
134 COM99 –5945 778
↓↓ ↓ ↓
152 COM117 –5945 –662
153 COM118 –742
154 COM119 –822
155 COM120 –902
Units: µm
COMn XY coordinates:
COM1 to COM24: (5945, –902 + [80 ×(n–1)])
COM25 to COM60: (5709– [160 ×(n–25)],1034)
COM61 to COM96: (–109– [160 ×(n–61)],1034)
COM97 to COM120:(–5945, 938 – [80 ×(n–97)])

SED1751
MLS Driver Chip Set EPSON 5–3
Technical Manual
TERMINAL FUNCTIONS
Input
TEST1
Terminal Name I/O Function Number of
Terminals
COM1 to OCommon (row) output to drive LC. 120
COM120 Output transition occurs on falling edge of LP.
Carry signal I/O.
CIO1 I/O This is set to input or output depending on the level of 2
CIO2 the SHL input. Output transition occurs on falling edge
of LP.
YD I Frame start/pulse input, with terminator. (*1) 1
F1, F2 I Drive pattern select signal input, with terminator. (*1) 2
LP I Shift clock input for display data. 1
(Triggers on falling edge.) With terminator. (*1)
Shift direction select and CIO terminal I/O control input.
SHL I 1
The numbers in parentheses are for 100 output mode.
Select input for the number of COM output terminals:
SEL I 120 outputs ←→ 100 outputs 1
L: COM1 to COM120
H: COM9 to COM108
LSEL I 1/2 H operation select signal input. 1
L: Normal operation. H: 1/2 operation.
Chip select signal input for when a cascade connection
CSEL I is used. 1
L: Leading chip
H: Other chips
FR I LC drive output AC signal input. With terminator (*1) 1
LC display blanking control input. With a low level input,
DOFF Iall common outputs are temporarily set to the VClevel. 1
The contents of the latches are maintained. With
terminator (*1)
TEST1 I Test1 signal input. Normally tied at L. 1
VCC, GNDL,
Power
Power source for logic: 3
GNDR GND: 0 V , VCC: +2.7 to 5.5 V
VCL, VCR,LC Drive Power:
+V1L, +V1R,
Power GND: 0 V, 8
-V1L, -V1R,VDDH: + 14.0 to 42.0 V, VDDH ≥+V1≥VC≥–V1≥GND
VDDHL, VDDHR
DM Dummy pad 11
Total 155
Note: *1
SHL Output Shift Direction CIO
CIO1 CIO2
L 1(9) →120(108) Input Output
H 120(108) →1(9) Output Input

SED1751
5–4 EPSON MLS Driver Chip Set
Technical Manual
VDDHL
GNDL
+V1L
VCL
–V1L
DOFF
GNDR
+V1R
VCR
–V1R
CIO2
LCD Driver: 120-bits
Level Shifter: 3x120-bits
Decoder
Bi-directional Shift Register: 30-bits
Data Register:
120-bits
VCC
TEST1
LP
YD
CIO1
COM 1 COM 120
SHL SEL LSEL CSEL
FR
F1
F2
Block Diagram

SED1751
MLS Driver Chip Set EPSON 5–5
Technical Manual
Explanation of Each Block
Shift Register
This is a bi-directional shift register used for transmitting common data. The display data shifts on the
falling edge of LP.
Level Shifter
The level shifter is a voltage level converter circuit which converts the signal voltage level from a logic
system level to the LC driver system voltage level.
LCD Driver
The LCD driver outputs the LC drive voltage.
The relationship between the display blanking signal DOFF, the field recognition signals F1 & F2, the AC
signal FR, and the common output voltage is as follows:
DOFF HL
FR L H —
F1,F2 1,1 0,1 1,0 0,0 1,1 0,1 1,0 0,0 —
Line 1 +V1+V1–V1+V1–V1–V1+V1–V1VC
Line 2 –V1+V1+V1+V1+V1–V1–V1–V1VC
Line 3 +V1–V1+V1+V1–V1+V1–V1–V1VC
Line 4 +V1+V1+V1–V1–V1–V1–V1+V1VC
Voltage level relationships: + V1> VC> –V1(VCis the center voltage level)

SED1751
5–6 EPSON MLS Driver Chip Set
Technical Manual
Timing Diagram (1)
1/240 duty, normal operation.
SHL = L, SEL = L, LSEL = L, CSEL = L (This diagram provided only as a reference.)
+V1
VC
–V1
F2
F1
FR
LP
Driver 1
COM1
+V1
VC
–V1
COM2
+V1
VC
–V1
COM3
+V1
VC
–V1
COM4
+V1
VC
–V1
COM5
+V1
VC
–V1
COM6
+V1
VC
–V1
COM7
+V1
VC
–V1
COM8
+V1
VC
–V1
Driver 2
COM120
Field 1 Field 2 Field 3
1 Frame (240 lines)
Field 4
1 2 3 60 61 62 63 120 121 122 123 180 181 182 183 240 1 2 3
1
1 2 3 4 5 30 31 32 33 60 61 62 63 90 91 92 93 120 121 122 123
2 3 4 5
240 lines
120 121 122 123 240 1 2 3 4
YD
LP
FR
LP
CIO 1
CIO 2

SED1751
MLS Driver Chip Set EPSON 5–7
Technical Manual
Timing Diagram (2)
1/240 duty, 1/2 H operation.
SHL = L, SEL = L, LSEL = H, CSEL = L (This diagram provided only as a reference.)
+V1
VC
–V1
F2
F1
FR
LP
Driver 1
COM1
+V1
VC
–V1
COM2
+V1
VC
–V1
COM3
+V1
VC
–V1
COM4
+V1
VC
–V1
COM5
+V1
VC
–V1
COM6
+V1
VC
–V1
COM7
+V1
VC
–V1
COM8
+V1
VC
–V1
Driver 2
COM120
Field 1 Field 2 Field 3
1 Frame (240 lines)
Field 4
2/240 2/1 2/60 2/61 2/120 2/121 2/180 2/181 2/240 2/1
1/1 1/1 1/61 1/62 1/121 1/122 1/181 1/182 1/1 1/1
1/1
1/1
2/1
1/2
2/2
1/3 1/30
2/30
1/31
2/31
1/60
2/60
1/61
2/61
1/90
2/90
1/91
2/91
1/120
2/120
1/121
2/121
2/1 1/2 2/2 1/3
240 lines
1/120 2/120 1/121 2/121 2/240 1/1 2/1 1/2 2/2
YD
LP
FR
LP
CIO
CIO
1
2

SED1751
5–8 EPSON MLS Driver Chip Set
Technical Manual
ABSOLUTE MAXIMUM RATINGS
Item Signal Rated Value Units
Power voltage (1) VCC –0.3 to +7.0 V
Power voltage (2) VDDH –0.3 to + 45.0 V
Power voltage (3) ±V1, VCGND – 0.3 to VDDH + 0.3 V
Input voltage VIGND – 0.3 to VCC + 0.3 V
Output voltage VOGND – 0.3 to VCC + 0.3 V
CIO output current IO1 20 mA
Operating temperature Topr –30 to +85 °C
Storage temperature 1 Tstg1 –65 to +150 °C
Storage temperature 2 Tstg2 –55 to +100 °C
NOTE 1: The voltages are all relative to GND = 0 V.
NOTE 2: Storage temperature 1 is for the chip alone, and storage temperature 2 is for the TCP
product.
NOTE 3: Ensure that the relationship between +V1, VC, and –V1is always as follows:
VDDH ≥+V1≥VC≥–V1≥GND.
NOTE 4: The LSI may be permanently damaged if the logic system power is floating or VCC is less
than or equal to 2.6 V when power is applied to the LC drive system. Special caution must
be paid to the power sequences during power up and power down.
V CC
GND (–V1)
V
DDH /2 (VC)
V
DDH (+V1)
Logic System LCD System

SED1751
MLS Driver Chip Set EPSON 5–9
Technical Manual
Electrical Characteristics
DC Characteristics
Unless otherwise noted, GND = 0 V, VCC = + 5.0 V ±10%, Ta = –30 to 85°C
Item Signal Parameter Applicable Min Typ Max Unit
Terminals
Power Supply VCC VCC 2.7 5.0 5.5 V
Voltage (1)
Range Operating VDDH Function VDDH 8.0 42.0 V
Voltages
Power Supply +V1Recommended Value +V1VDDH V
Voltage (2)
Power Supply VCRecommended Value VCVDDH/2 V
Voltage (3)
Power Supply –V1Recommended Value –V1GND V
Voltage (4)
High-level Input VIH 0.8VCC V
Voltage VCC = 2.7 to 5.5V
Low-level Input VIL 0.2VCC V
Voltage
High-level Output VOH IOH = VCC–0.4 V
Voltage VCC = 2.7 to 5.5V –0.3mA CIO1,CIO2
Low-level Output VOL IOL = 0.4 V
Voltage 0.3mA
Input Leakage Current ILI GND ≤VIN ≤VCC 2.0 µA
Input/Output Leakage ILI/O GND ≤VIN ≤VCC CIO1,CIO2 5.0 µA
Current
Static Current IGND VDDH = 14.0~42.0V GND 25 µA
VIH = VCC, VIL = GND
∆VON = 0.5 V VDDH = 0.55 0.7
Output Resistance RCOM Recommended +30.0V COM1 to kΩ
parameter VDDH = COM120 0.5 0.7
+40.0V
VCC = +5.0 V, VIH = VCC
VIL = GND, fLP = 16.8 kHz 10 25
Average Operating fFR = 70 Hz,
Consumption Current ICC Input data: 1/240 No load VCC µA
(1) VCC = 3.0 V
All other parameters 7 17
the same as VCC = 5.0 V.
VDDH = +V1= +30.0 V,
Average Operating VC= VDDH/2, –V1= 0.0 V,
Consumption Current IDDH VCC = 5.0 V VDDH 613µA
(2) All other parameters
the same as the ICC item.
Input Terminal CIFreq. = 1 MHz 10 pF
Capacity Chip alone
Input/Output Terminal CI/O Ta = 25°CCIO1,CIO2 18 pF
Capacity
CIO1,CIO2,FR,
YD,LP,SHL,SEL,
LSEL,CSEL,
DOFF,F1,F2,
TEST1
LP,YD,SHL,SEL,
LSEL,CSEL,F1,
F2,DOFF,TEST1,
FR
LP,YD,SHL,SEL,
LSEL,CSEL,F1,F2,
DOFF,TEST1,FR

SED1751
5–10 EPSON MLS Driver Chip Set
Technical Manual
Range of Operating Voltages: VCC – VDDH
It is necessary to set the voltage for VDDH within the VCC – VDDH operating voltage range shown in the
diagram below.
Range of
Operating
Voltage
50
42
40
30
20
10
28
8
02.0 3.02.7 4.0
VCC (V)
VDDH (V)
5.0 6.05.5

SED1751
MLS Driver Chip Set EPSON 5–11
Technical Manual
AC Characteristics
Input Timing Characteristics
The FR latched at the nth LP is reflected in the output at the n+1th LP.
t
DS
t
DH
t
SET
t
WCLH
t
WCLD
t
CCL
t
FFDS
t
FFDH
t
r
t
f
t
FRDS
t
FRDH
FR
F1, F2
LP
YD
CIO1, 2
(IN)
(VCC = +5.0 V ±10%, Ta = –30 to +85°C)
Item Signal Parameter Min Max Units
LP Frequency tCCL 500 ns
LP “H” Pulse Width tWCLH 55 ns
LP “L” Pulse Width tWCLL 330 ns
FR Setup Time tFRDS 100 ns
FR Hold Time tFRDH 40
F1, F2 Setup Time tFFDS 100
F1, F2 Hold Time tFFDH 40
Input Signal Rise Time tr50ns
Input Signal Fall Time tf50ns
CIO Setup Time tDS 100 ns
CIO Hold Time tDH 40 ns
YD →LP Allowable Time tSET 80 ns
(VCC = +2.7 V to 4.5 V, Ta = –30 to +85°C)
Item Signal Parameter Min Max Units
LP Frequency tCCL 800 ns
LP “H” Pulse Width tWCLH 100 ns
LP “L” Pulse Width tWCLL 660 ns
FR Setup Time tFRDS 200 ns
FR Hold Time tFRDH 80
F1, F2 Setup Time tFFDS 200
F1, F2 Hold Time tFFDH 80
Input Signal Rise Time tr 100 ns
Input Signal Fall Time tf 100 ns
CIO Setup Time tDS 200 ns
CIO Hold Time tDH 80 ns
YD →LP Allowable Time tSET 150 ns

SED1751
5–12 EPSON MLS Driver Chip Set
Technical Manual
Output Timing Characteristics
tpdCDOF
tpdCCL
tpdDOC
LP
DOFF
COM
Output
CIO1, 2
(OUT)
(VCC = 5.0 V ±10%, VDDH = +14.0 to +42.0 V, Ta = –30 to +85°C)
Item Signal Parameter Min Max Units
Delay time from LP to CIO output tpdDOC CL= 15 pF 300 ns
Delay time from LP to COM output tpdCCL VDDH =350ns
Delay time from DOFF to COM output tpdCDOF 14.0 V to 40.0 V 700 ns
(VCC = +2.7 V to 4.5 V, VDDH = +14.0 to +28.0 V, Ta = –30 to +85°C)
Item Signal Parameter Min Max Units
Delay time from LP to CIO output tpdDOC CL= 15 pF 600 ns
Delay time from LP to COM output tpdCCL VDDH =500ns
Delay time from DOFF to COM output tpdCDOF 14.0 V to 40.0 V 1400 ns

SED1751
MLS Driver Chip Set EPSON 5–13
Technical Manual
The Power Supply
Method of Forming Each Voltage Level
VCC
GND
Logic System
LCD Controller
Capacitor
Coupling
Logic System LCD System
SED1580D
0B
Logic System LCD System
SED1751D
0B
VDDx
VSSx
VDDy
VSSy
V3
VC VC
V1
–V1
V2
–V2
–V3
When the SED1580 and the SED1751 are used to form an extremely low power module system, the power
relationships as shown in the figure above between the SED1580 and SED1751 logic systems, and the LCD
system power supply, and the LCD controller power supply are optimal.
In this case, care is required when it comes to signal propagation in the logic system.
LCD Controller →SED1580 Direct
LCD Controller →SED1751 Capacitor coupling is required
SED1580 →SED1751 Capacitor coupling is required
SED1751 →SED1580 Capacitor coupling is required
Cautions at Power Up and Power Down
Because the voltage level in the LCD system is high voltage, if the logic system power supply of this LSI
is floating or if VCC is 2.6 V or less when the LCD system high voltage (30 V or above) is applied, or if
the LCD drive signal is output before the voltage level that is applied to the LCD system has stabilized,
then there is the risk that there will be an over current condition in this LSI, resulting in permanent damage
to this LSI.
It is recommended that the display OFF function (DOFF) is used until the LCD system voltage stabilizes
to insure that the LCD drive output power level is at the VC level.
Be sure to follow the sequences below when turning the power supplies ON and OFF:
When turning the power supply ON:
Logic system ON →LCD drive system ON, or simultaneously ON.
When turning the power supply OFF:
LCD drive system OFF →Logic system OFF, or simultaneously OFF.
As a countermeasure to guard against over current conditions, it is effective to insert a high-speed fuse or
a guard resistance in series with the LC power supply. The guard resistance value must be optimized
depending on the capacity of the LC cell.

SED1751
5–14 EPSON MLS Driver Chip Set
Technical Manual
Example of Connection
Large Screen LCD Structure Diagram
EIO1
BSEL
LSEL
F1O~F2O
F2S
F1S
SEL
CA
YD
FR
LP
XSCL
DOFF
D0~7
EIO2
160
SED1580
EIO1
BSEL
LSEL
F1O~F2O
F2S
F1S
SEL
CA
YD
FR
LP
XSCL
DOFF
D0~7
EIO2
160
SED1580
EIO1
BSEL
LSEL
F1O~F2O
F2S
F1S
SEL
CA
YD
FR
LP
XSCL
DOFF
D0~7
EIO2
160
SED1580
160
CIO1 YD LP FR DOFF SHL SEL LSEL CSEL F1~F2 CIO2
DU0~7
FS2 FS1
SHLU
YD
FR
LP
XSCL
DOFF
LSEL
SEL
SHL
YSCL
SHLL
DL0~7
120
SED1751
CIO1 YD LP FR DOFF SHL SEL LSEL CSEL F1~F2 CIO2
120
SED1751
CIO1 YD LP FR DOFF SHL SEL LSEL CSEL F1~F2 CIO2
120
SED1751
CIO1 YD LP FR DOFF SHL SEL LSEL CSEL F1~F2 CIO2
120
SED1751
EIO2
D0~7
DOFF
XSCL
LP
FR
YD
CA
SHL
F1S
F2S
F1O~F2O
LSEL
BSEL
EIO1
160
SED1580
EIO2
D0~7
DOFF
XSCL
LP
FR
YD
CA
SHL
F1S
F2S
F1O~F2O
LSEL
BSEL
EIO1
160
SED1580
EIO2
D0~7
DOFF
XSCL
LP
FR
YD
CA
SHL
F1S
F2S
F1O~F2O
LSEL
BSEL
EIO1
160
SED1580
EIO2
D0~7
DOFF
XSCL
LP
FR
YD
CA
SHL
F1S
F2S
F1O~F2O
LSEL
BSEL
EIO1
160
SED1580
640 ×480 DOT
1/240 DUTY
Controller
EIO1
BSEL
LSEL
F1O~F2O
F2S
F1S
SEL
CA
YD
FR
LP
XSCL
DOFF
D0~7
EIO2
SED1580

SED1751
MLS Driver Chip Set EPSON 5–15
Technical Manual
Example of External Connections
(Rear surface should be P1 coated.) (Rear surface should be P1 coated.)
(Rear surface should be P1 coated.)
Detail drawing for the test pad section Output terminal pattern shape
Specifications :
Base : Eupirex-S? , 75?u?m Copper foil : 31P (14.25mm) Sn plated Product pitch : 31P (14.25mm) Solder resist position tolerance : ±0.3
(Molding range) (Molding range)
(Rear surface should
be P1 coated.)
(Molding range) (Molding range)