ETAS ES1651.1 User manual

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ES1651.1 Carrier Board
User’s Guide
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2
Copyright
The data in this document may not be altered or amended without special
notification from ETAS GmbH. ETAS GmbH undertakes no further obligation
in relation to this document. The software described in it can only be used if
the customer is in possession of a general license agreement or single license.
Using and copying is only allowed in concurrence with the specifications stip-
ulated in the contract.
Under no circumstances may any part of this document be copied, repro-
duced, transmitted, stored in a retrieval system or translated into another lan-
guage without the express written permission of ETAS GmbH.
© Copyright 2004 - 2007 ETAS GmbH, Stuttgart
The names and designations used in this document are trademarks or brands
belonging to the respective owners.
F 00K 103 396 - 12.2007 TTN F 00K 103 396
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Contents 3
Contents
1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Applications and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Carrier Board for Piggybacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Synchronization Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Crankshaft Angle Clock Bus (CAC Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Generating an Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5 Inspection and Versioning Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3CAN Interfaces (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Pin Assignment and Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 Configuration of the Debug Port Connections of the Processor (JP0) . . . . 20
4.2 JTAG Chain Configuration (JP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 Boot Configuration (SW0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 Reset Switch (SW3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5 Addressing the ES1651.1 at the VMEbus (SW1 and SW2) . . . . . . . . . . . . 23
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Contents4
5Installing I/O Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1 Assembling the Front Panel to the PB4350XXX Module . . . . . . . . . . . . . . 26
5.2 Mounting the CAN Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3 Mounting the I/O Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6Pin Assignments and Display Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1 CAN Ports CAN0 and CAN1 (CO0, CO1) . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2 Synchronization Bus and CAC Bus Connection ”SYNC & CAC” (CO2) . . . 35
6.3 Connectors for CAN Transceiver Modules . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.1 8-Pin Female Header (CO3, CO5) . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.2 16-Pin Female Header (CO4, CO6) . . . . . . . . . . . . . . . . . . . . . . 37
6.4 Box Headers for I/O Modules (CO7 - CO10) . . . . . . . . . . . . . . . . . . . . . . . 37
6.5 ETAS-Internal Service Connection (CO11) . . . . . . . . . . . . . . . . . . . . . . . . 38
6.6 Interface for Logic Analyser (CO12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.7 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7Technical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8ETAS Contact Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Introduction 5
1 Introduction
This User’s Guide contains the description of the ES1651.1 Carrier Board.
It consists of the following chapters:
• "Applications and Features" on page 6
The introduction contains an overview of the characteristics of the
ES1651.1 Carrier Board and also includes a block diagram.
• "Hardware Features" on page 10
This is where the properties of the ES1651.1 Carrier Board are
described in detail. These are:
– "Carrier Board for Piggybacks" on page 10
– "Synchronization Bus" on page 10
– "Crankshaft Angle Clock Bus (CAC Bus)" on page 11
– "Generating an Interrupt" on page 15
– "Inspection and Versioning Data" on page 16
• "CAN Interfaces (Optional)" on page 17
This section contains information on the CAN interfaces.
• "Configuration" on page 20
This section contains a description of the configuration possibilities of
the ES1651.1 Carrier Board and their presettings.
• "Addressing the ES1651.1 at the VMEbus (SW1 and SW2)"
on page 23
This section describes addressing the ES1651.1 at the VMEbus.
• "Installing I/O Modules" on page 26
This section describes how to assemble I/O modules on the ES1651.1
Carrier Board and any necessary preparatory steps:
– "Assembling the Front Panel to the PB4350XXX Module"
on page 26
– "Mounting the CAN Transceivers" on page 29
– "Mounting the I/O Modules" on page 30
• "Pin Assignments and Display Elements" on page 34
This section contains a description of all connectors on the front panel
and on the board as well as the meaning of the LED displays.
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Introduction6
• "Technical Data" on page 40
contains the technical data of the ES1651.1 Carrier Board.
1.1 Applications and Features
The ES1651.1 Carrier Board acts as a carrier board for up to four I/O modules
in VMEbus systems. All modules of types ”PB4350XXX” and ”PB1651XXX”
can be used in any combination. An SPI control unit realized in the FPGA of the
board converts the parallel data flow of the processor into a serial bit flow for
the SPI interfaces of the I/O modules.
The ES1651.1 Carrier Board has a crankshaft angle clock bus for testing engine
ECUs in LABCAR projects; this can be used to synchronize I/O modules with a
central crankshaft angle clock for speed-synchronous signal acquisition and
signal generation. The crankshaft angle clock bus is routed to the 9-pin Sub-D
connector on the front panel of the board so that the crankshaft angle clock
can be both supplied externally as well as routed to the outside.
Synchronization Bus
The ES1651.1 has a synchronization bus to synchronize the I/O modules of an
ES1651.1 Carrier Board with each other. It consists of four lines which can be
configured independently of each other. The bus is also routed to the 9-pin
Sub-D connector on the front panel of the board so that the signals can be
Note
Some components of the ES1651.1 Carrier Board may be damaged or
destroyed by electrostatic discharges. Please keep the board in its storage
package until it is installed.
The ES1651.1 Carrier Board should only be taken from its package, config-
ured and installed at a working place that is protected against static dis-
charge.
Note
The components, connectors and conductors of the ES1651.1 Carrier Board
may carry dangerous voltages.
These voltages may even exist when the board is not installed in the VMEbus
system or the VMEbus system is powered off.
Make sure that the board is protected against contact during operation.
Disconnect all connections to the ES1651.1 Carrier Board before removing
the board from the VMEbus system.
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Introduction 7
supplied externally or routed to the outside to synchronize I/O modules on
other carrier boards. The synchronization lines can also be stimulated from
within the simulation model.
CAN Interfaces
There are two identical CAN channels on the ES1651.1 Carrier Board for con-
necting the board to the CAN bus. The transceiver functionality is realized on
piggybacks so that, if necessary, different transceivers can be used than those
intended, i.e. than the PCA82C251 transceiver by Philips for high-speed CAN
applications 1and the MAX3055 transceiver by Maxim for low-speed CAN
applications2.
The ETAS PB1651CAN1 transceiver module is a combined high-speed/low-
speed CAN transceiver module3with galvanic isolation of the CAN channels.
Relays are used to toggle between high-speed and low-speed functionality.
The CAN controller functionality is realized in the MPC555 processor of the
board which has two CAN channels on board.
VMEbus Interface
The ES1651.1 Carrier Board has a VMEbus slave interface and reacts to ”A24
non privileged data access” accesses (VMEbus address modifier 39 hex).
The position of the 64-kByte VMEbus address space of the board can be set
either dynamically or statically. Data is exchanged with VMEbus master boards
via a 32-kByte DPRAM. The board can trigger interrupts at the VMEbus.
Inspection and Versioning Data
Inspection and versioning data of the board are stored in a serial non-volatile
data memory. PB1651CAN1 transceiver modules also have serial data memo-
ries for version and inspection data.
Processor
In addition to the CAN channels listed, the MPC555 processor of the board
also has a 448-kByte ROM memory which is large enough for program code
and data; this is why the optional external ROM memory is not assembled.
1. High-speed CAN systems (data rates between 125 kBaud and 1 MBaud) are
used e.g. for engine and transmission controls, ESP, ASR, ACC and ABS.
2. Low-speed CAN systems (data rates up to 125 kBaud) are used in the field
of convenience electronics.
3. The terms fault-tolerant CAN and low-speed CAN are synonymous.
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Introduction8
Fig. 1-1 shows the front panel of the ES1651.1 Carrier Board.
Fig. 1-1 Front Panel of the ES1651.1 Carrier Board
ES1651.1
ETAS
CAN0CAN1
RDER SY
C1C0 CB
SYNC & CAC
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Introduction 9
1.2 Block Diagram
Fig. 1-2 shows a block diagram with all important functional units of the
ES1651.1 Carrier Board.
Fig. 1-2 Block Diagram of the ES1651.1 Carrier Board
FPGA
CAN
Transceiver 0
SYNC & CAC CAN0CAN1
Processor
I/O Module 3
Serial
ROM
CAN
Transceiver 1
SPI Control Unit
I/O Module 2
I/O Module 1
I/O Module 0
External
RAM
(512
kByte)
External
ROM
(opt.)
32
VMEbus Interface
16
32
DPRAM (32 kByte)
16
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Hardware Features10
2 Hardware Features
This section contains a description of the different hardware features of the
ES1651.1 Carrier Board.
These are:
• "Carrier Board for Piggybacks" on page 10
• "Synchronization Bus" on page 10
• "Crankshaft Angle Clock Bus (CAC Bus)" on page 11
• "Generating an Interrupt" on page 15
• "Inspection and Versioning Data" on page 16
2.1 Carrier Board for Piggybacks
The ES1651.1 Carrier Board is used as a carrier board for I/O modules in VME-
bus systems. I/O modules are available for various tasks, such as the generation
and measuring of ECU signals in real time.
All modules of types ”PB4350XXX” and ”PB1651XXX” can be used. This
means that the LABCAR test system can be equipped both with the standard
I/O modules for the ES1651.1 Carrier Board (VME system) and with the highly
precise I/O modules for the ES4350 Carrier Board. Up to four I/O modules of
both types mentioned above can be used per ES1651.1 Carrier Board.
The I/O modules are connected using ribbon cable. There are four connectors
on the ES1651.1 Carrier Board for this purpose. For more details on how to
assemble I/O modules, please refer to section 5 on page 26.
2.2 Synchronization Bus
The ES1651.1 Carrier Board has a synchronization bus for synchronizing
• the I/O modules mounted on the carrier board with each other,
• I/O modules with the carrier board,
• I/O modules with other I/O modules which are installed on other
ES1651.1 Carrier Boards or ES4350 Carrier Boards in the same or other
VMEbus systems,
• with other external hardware which can generate or interpret the rele-
vant synchronization signals.
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Hardware Features 11
The synchronization bus has four identical synchronization channels. A block
diagram of a single channel is shown in Fig. 2-1.
Fig. 2-1 Block Diagram of a Synchronization Channel
The front panel connector can be configured as
• an input which provides the synchronization signals for the carrier
board hardware and the I/O modules,
• an output which provides the synchronization signals for external hard-
ware
or can be disconnected from the synchronization bus.
Internally the synchronization bus works with 3.3 V digital signals. To reduce
interference sensibility, the signals are transferred to and from external hard-
ware with 5 V digital signals. The direction of an individual synchronization
channel can be selected independently of the other synchronization channels.
The input and output stages are protected against overvoltage from -14 V to
+19 V (with reference to VMEbus ground).
For more details of the input and output stages, please refer to the section
"Technical Data" on page 40.
2.3 Crankshaft Angle Clock Bus (CAC Bus)
The ES1651.1 Carrier Board has a crankshaft angle clock bus (CAC bus) for
LABCAR projects which include the stimulation and testing of engine ECUs bus
(CAC bus).
3.3 V Digital Signals 5 V Digital Signals
I/O Module 1
I/O Module 2
I/O Module 3
I/O Module 4
Front Panel
Connector
IP
OP
IP: Input Protection Circuit
OP: Output Protection Circuit
ES1651
FPGA
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Hardware Features12
Like the synchronization bus, the CAC bus is also connected to the I/O mod-
ules and the FPGA of the carrier board. It is connected to I/O modules which
are assembled on other ES1651.1 Carrier Boards or ES4350 Carrier Boards, or
to other external hardware which can provide or process crankshaft angle
clock signals via the 9-pin Sub-D connector on the front panel.
The CAC bus can be driven by the CAC generators on ES1332.1 and ES4320
boards (an I/O module for CAC generation is currently under development).
The crankshaft angle clock cannot be generated in the FPGA of the ES1651.1.
The CAC bus of the ES1651.1 consists of the following three signals (refer to
Fig. 2-4 on page 14):
• CAC-SYNC signal: Synchronization signal for 0 °CA
• CAC-CLK signal: The actual crankshaft angle clock signal
• CAC-DOR signal: Signal for displaying the direction of rotation
The following two figures show block diagrams of the channel for the synchro-
nization signal (Fig. 2-2) and the CAC signal (Fig. 2-3) respectively. The chan-
nel for the direction signal is identical to the channel for hardware
synchronization (see Fig. 2-1 on page 11).
Fig. 2-2 Block Diagram of the CAC Bus Synchronization Channel
3.3 V Digital Signals 5 V/10 V Digital Signals
I/O Module 1
I/O Module 2
I/O Module 3
I/O Module 4
Front Panel
Connector
IP
OP
ES1651
FPGA
+
+
7.2 V
2.2 V
IP: Input Protection Circuit
OP: Output Protection Circuit
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Hardware Features 13
Fig. 2-3 Block Diagram of the CAC Bus Crankshaft Angle Clock Channel
The CAC bus front panel connector can be configured as
• an input which provides the CAC signals for the carrier board hardware
and the I/O modules,
• an output which provides the CAC signals for external hardware
or can be disconnected from the crankshaft angle clock.
The input and output stages are protected against overvoltage from -14 V to
+19 V (with reference to VMEbus ground).
Internally the synchronization bus works with 3.3 V digital signals – the levels
of the output signals of the CAC bus on the front panel are shown in Fig. 2-4
on page 14.
The CAC bus inputs can process two types of CAC signal:
• The combined CAC synchronization and clock signal as generated by
ES1332 boards (see Fig. 2-5 on page 15).
This signal must be connected to the pin of the CAC synchronization
signal as well as to the pin of the CAC clock signal of the Sub-D front
panel connector for this purpose. In this case, the ”Input ES1332 CAC”
option must be set in the option box ”CAC Port Mode” in the
”ES1651-CTRL” RTIO element of the ES1651-RTIO integration. This
results in the switch at the output of the 7.2 V comparator (Fig. 2-2
on page 12) and the switch at the output of the 2.2 V comparator
(Fig. 2-3 on page 13) being closed.
3.3 V Digital Signals 5 V/10 V Digital Signals
I/O Module 1
I/O Module 2
I/O Module 3
I/O Module 4
Front Panel
Connector
IP
OP
IP: Input Protection Circuit
OP: Output Protection Circuit
ES1651
FPGA
+
2.2 V
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Hardware Features14
• Input signals of the type shown in Fig. 2-4.
The signals are connected to the relevant pins of the Sub-D front panel
connector. In this case, the ”Input” option must be set in the option
box ”CAC Port Mode” in the ”ES1651-CTRL” RTIO element of the
ES1651-RTIO integration. This results in the switch at the output of the
2.2 V comparator (Fig. 2-2 on page 12) and the switch at the output of
the 2.2 V comparator (Fig. 2-3 on page 13) being closed.
The direction of the CAC bus signals (input or output) can only be selected for
the bus as a whole.
Fig. 2-4 CAC Bus Output Signals
Note
The pin assignment of the 9-pin Sub-D connector is contained in the section
"Synchronization Bus and CAC Bus Connection ”SYNC & CAC” (CO2)"
on page 35.
Crankshaft
Angle
0° 720° 1440°
5 V
0 V
5 V
0 V
5 V
0 V
Crankshaft Angle Clock Bus Synchronization Signal
Crankshaft Angle Clock Bus Angle Clock Signal
Crankshaft Angle Clock Bus Direction of Rotation Indicator Signal
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Hardware Features 15
Fig. 2-5 Combined CAC Synchronization and Clock Signal (ES1332)
For more details of the input and output stages, please refer to the section
"Technical Data" on page 40.
2.4 Generating an Interrupt
The ES1651.1 Carrier Board has eight interrupt lines which, connected via a
logical ”OR” operation, generate a common interrupt request on the VMEbus.
Each of these eight interrupt lines can be activated or deactivated using the
software. If a line is activated, an interrupt request is generated by a falling
signal edge on the interrupt line. The VMEbus interrupt handler then deter-
mines which of the interrupt lines was the source of the request.
The interrupt lines PB0_IRQ to PB3_IRQ of the I/O modules are connected to
interrupt lines 0 to 3 of the VMEbus interface. The ES1651.1 Carrier Board also
makes it possible to connect one of the synchronization bus lines to interrupt
line 4 – this is selected using the software.
Interrupt lines 5 to 7 are not assigned to date.
Crankshaft
Angle
0° 720°
ES1332 combined crankshaft angle synchronization and clock signal
1440°
10 V
5 V
0 V
0.5°
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Hardware Features16
Fig. 2-6 The Interrupt Concept of the ES1651.1
2.5 Inspection and Versioning Data
Inspection and versioning data of the board are stored in a serial non-volatile
data memory which is addressed via the processor’s SPI (Serial Peripheral Inter-
face). The data can be read out via the operating software LABCAR-OPERA-
TOR.
OR VME_IRQ
&
Enable0
&
&
&
&
&
&
&
ES1651 VMEbus Interface
SYNC_IRQ
SYNC0
SYNC1
SYNC2
SYNC3
PB3_IRQ
PB2_IRQ
PB1_IRQ
PB0_IRQ
Enable1
Enable2
Enable3
Enable4
Enable5
Enable6
Enable7
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CAN Interfaces (Optional) 17
3 CAN Interfaces (Optional)
There are two identical CAN channels on the ES1651.1 Carrier Board for con-
necting the board to the CAN bus. The transceiver functionality is realized on
piggybacks so that, if necessary, different transceivers can be used than those
intended, i.e. than the PCA82C251 transceiver by Philips for high-speed CAN
applications and the MAX3055 transceiver by Maxim for low-speed CAN appli-
cations.
The ETAS PB1651CAN1 transceiver module is a combined high-speed/low-
speed CAN transceiver module with galvanic isolation of the CAN channels.
Relays are used to toggle between high-speed and low-speed functionality. A
120 Ohm bus termination of the high-speed CAN interface can also be acti-
vated and deactivated using a relay switch.
The relay switches can be controlled using the LABCAR-OPERATOR operating
software. The CAN controller functionality is realized in the MPC555 processor
of the board which has two CAN channels on board.
The PB1651CAN1 transceiver modules have a serial non-volatile data memory
for inspection and versioning data which is addressed via the processor’s SPI
interface. The data can be read out via the operating software LABCAR-
OPERATOR.
The block diagram of a PB1651CAN1 transceiver module is shown in Fig. 3-1.
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CAN Interfaces (Optional)18
Fig. 3-1 Block Diagram of a PB1651CAN1 Transceiver Module
3.1 Features
The PB1651CAN1 transceiver modules have the following features:
• Galvanic isolation from the VMEbus
• ±36 V on CAN_H and CAN_L
• Toggling between high-speed and low-speed CAN interface via relays
• The high-speed CAN transceiver is fully compatible with the
ISO 11898-24 V standard
•120Ωterminating resistor of the high-speed CAN interface can be
switched using relays
HS
Transceiver
FT
Transceiver
Galvanic
Isolation
CAN_H
CAN_L
+UBatt
-UBatt
Wake
HS / FT CAN Transceiver Piggyback Module
TXD
RXD
HSON
TERM
Standby
Enable
Error
+5V
GND
MOSI
TXD
RXD
TXD
RXD
Standby
Enable
Error
SPI Bus
EEPROM
+3.3V
MISO
SCLK
CSEL
TPB_AV
120 Ω
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CAN Interfaces (Optional) 19
• Full support of the operating modes ”Standby” and ”Sleep” of the
fault-tolerant CAN transceiver as well as error monitoring
• Switch technology for reducing electromagnetic emission and improv-
ing the electromagnetic compatibility of the CAN channel
• SPI bus EEPROM for versioning, inspection and maintenance data
• Automatic detection of the transceiver module with the LABCAR-
OPERATOR operating software
• The bus lines CAN_H and CAN_L are each terminated on the low-
speed CAN transceiver with 2.2 kΩ.
3.2 Pin Assignment and Signals
The CAN transceiver module and the ES1651.1 Carrier Board are connected
using an 8-pin and a 16-pin connector. For more details on the pin assign-
ment, please refer to the section "Connectors for CAN Transceiver Modules"
on page 36.
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