Freescale Semiconductor T4240 User manual

Freescale Semiconductor
T4240 QDS Quick Start Guide
© 2013 Freescale Semiconductor, Inc. All rights reserved.
The QorIQ T4240 development system (T4240
QDS-16GPA) is a flexible system that supports the
24-virtual core T4240 processor. The T4240 QDS main
board is mounted in a 4U rack-mounted chassis and the main
PCB is a custom form factor.
An additional layer of flexibility for system clocking, power
distribution, and I/O multiplexing is built into the T4240
QDS. Eight expansion slots are provided for adding standard
PCIe cards or Freescale specialized SerDes riser cards (XFI
or XAUI networking). The T4240 QDS comes with a
Linux® board support package (BSP) that provides a
comprehensive starting point for Linux development efforts.
The T4240 QDS is available in two form factors:
• T4240 QDS board installed in a chassis
• T4240 QDS board as a stand-alone system
When you finish reading this document, you should be
familiar with:
• T4240 QDS hardware kit contents
• Board configuration settings
• How to get started and boot the board
Document Number:T4240QDSQSG
Rev.0, 06/2013
Contents
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Hardware Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . 2
3. T4240 QDS Board Diagram . . . . . . . . . . . . . . . . . . . . 3
4. Connections and Switch Settings . . . . . . . . . . . . . . . . 4
5. Powering up and Booting System . . . . . . . . . . . . . . . 12
6. Pre-loaded RCW and Boot Flash Information . . . . . 33
7. Connecting a 750W Power Supply . . . . . . . . . . . . . . 34
8. Configuring T4240 QDS in Chassis . . . . . . . . . . . . . 38
T4240 QDS Quick Start Guide

T4240 QDS Quick Start Guide, Rev.0
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Introduction
1 Introduction
This T4240 QDS Quick Start Guide explains T4240 QDS board settings and physical connections needed
to boot the board.
The document provides steps for configuring switches, connectors, jumpers, push buttons, and LEDs and
connecting peripheral devices.
The T4240 QDS works with an integrated development environment (IDE), such as Freescale
CodeWarrior. However, instructions for working with the IDE are beyond the scope of this document.
1.1 Acronyms and Abbreviations
Table 1 lists commonly used acronyms and abbreviations.
1.2 Related Documentation
The following table lists the documents that you can refer to for more information about T4240 QDS board
operations.
2 Hardware Kit Contents
This section lists the T4240 QDS Standalone System and T4240 QDS System-in-Chassis contents.
2.1 T4240 QDS Standalone System Contents
• 700-27313: T4240 QDS Board assembly
• 400-75912: Power supply, ATX, 600W, input 90V-264V with power factor correction, low min.
load req
Table 1. Acronyms and Abbreviations
IDE Integrated Development Environment PLL Phase Lock Loop
QDS QorIQ Development System SERDES Serializer/Deserializer
RCW Reset Configuration Word USB Universal Serial Bus
PHY Physical Layer Interface Device
Table 1-2. Related Documentation
Document Description
CodeWarrior Kit Configuration Guide Explains how to setup hardware and software, and use each software component
in the development kit.
T4240 QorIQ
Advanced Multiprocessor Reference
Manual
T4240RM
T4240 QorIQ
Advanced Multicore Processor
Datasheet
T4240
T4240 QDS Reference Manual T4240QDSRM

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T4240 QDS Board Diagram
• 600-76962: Power cable adapter, 4-pin to 6-pin for PCI Express Card power
• 600-76963: Power cable adapter, 6-pin to 8-pin +12V supply adapter cable
• 600-75565: RS-232 Pro Series shielded serial cable, w/ DB-9 connectors
• 600-75499: Ethernet Cable, straight through wiring, 6 ft.
2.2 T4240 QDS System-in-Chassis Contents
• 800-75661: Chassis, 4U, Custom, T4240 QDS
• 700-27313: T4240 QDS Board assembly
• 400-75973: Power Supply, 1U, EPS12V, 460W
• 600-76962: Power cable adapter, 4-pin to 6-pin for PCI Express Card power
• 600-75565: RS-232 Pro Series shielded serial cable, w/ DB-9 connectors
• 600-75499: Ethernet Cable, straight through wiring, 6 ft.
3 T4240 QDS Board Diagram
Figure 1 and Figure 2 shows the T4240 QDS board.
Figure 1. T4240 QDS Board - Components

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Connections and Switch Settings
Figure 2. T4240 QDS Board
4 Connections and Switch Settings
This section explains T4240 QDS connections and switch settings.
4.1 Connection Settings
In order to operate T4240 QDS and boot U-boat, you need to connect different cables to the board. Some
of the cable connections are required, however, some of the connections are optional.
1. Fan cable – Required: Ensure the 3-wire cable from the main fan is connected to the 3-pin Prod
Fan header at J15.
This fan cable should already be installed in the received shipment, however ensure that this
connection is always made before powering on the system.

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Connections and Switch Settings
Figure 3. Main Fan Cable Connection
2. DDR Dims – Required: Ensure that at least three DDR Dims are installed, one for each of the
three DDR controllers, as shown in Figure 4. Otherwise, U-boat will not boot. Dims should be in
the following slots:
— J23 - D2_DIMM #1
— J22 - D1_DIMM #1
— J200 - D3_DIMM #1

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Connections and Switch Settings
Figure 4. Default DDR DIMM Assembly
3. Power Supply – Required: For power supply setup and connections:
a) Gather the following items from the packaging:
– Power Supply, ATX, 600W w/ AC power cord, as shown in Figure 5.
NOTE
If you are using an older 750W Power supply - typically black in color - then
refer to Section 7, “Connecting a 750W Power Supply” for information
about how to make connections.
Figure 5. Power Supply
– 6-pin to 8-pin12V supply power cable adapter, as shown in Figure 6.

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Connections and Switch Settings
Figure 6. 12V Power Cable Adapter
b) Attach AC cable to power supply. Note the location of the main power supply ON/OFF switch
near the AC plug.
c) The output cabling from the power supply consists of many cables, but only three of them are
attached to the T4240 QDS board. Separate the three output power cables from the rest of the
cabling bundle, as shown in Figure 7.
Figure 7. Output Power Cables to be Separated from Cabling Bundle
d) Attach the 12V power adapter cable to the 6-pin P11 connector of the power supply, as shown
in Figure 8.

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Connections and Switch Settings
Figure 8. 12V Power Adapter Cable Attached to the 6-pin P11 Connector
Be careful to attach the 6-pin end of the adapter cable to the 6-pin portion of the P11 power
supply connector. Also, ensure that the latching mechanism of the P11 connector aligns with
the latching tab of the 6-pin adapter cable connector, as shown in Figure 9.
Figure 9. Latch of VGA1 Connector Aligned With Latching Tab of Adapter Connector
e) To attach the power supply cables to the T4240 QDS system:
— Attach the two-part P2 power supply connector to the EPS_BULK_12V header (J27) of the
T4240 QDS board. Be careful that connector latches align with the latching tab of the mating
connector of the board.
— Attach the 2x4 end of the 12V adapter cable to the EPS_12V header (J225) of the T4240 QDS
board. Be careful that connector latch aligns with the latching tab of the mating connector of
the board.
— The main supply connector P1 has two parts; a 2x2 section and a 2x10 section. Attach the 2x2
section of the main power supply connector to the right-most side of the ATX24 connector
(J30), and then attach the 2x10 section of the main power supply connector to the left-most side

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Connections and Switch Settings
of the ATX24 connector (J30). Be careful that connector latch aligns with the latching tab of
the mating connector of the board. Figure 10 and Figure 11 show these power connections
before and after proper insertion in the board.
Figure 10. Power Supply Connections (Before Insertion)
Figure 11. Completed Power Supply Connections (After Insertion)

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Connections and Switch Settings
4. Serial Cable – Required: Attach serial cable to UART1_BOTTOM Port of T4240_QDS as
shown in Figure 13. Attach other end of cable to serial port of PC. This connection provides
visibility of boot activity to the COM port window of the PC. Configure the serial port of the host
PC with the settings shown in Figure 12.
Figure 12. Serial Port Configuration Settings
5. Ethernet Cable – Optional: Figure 13 shows Ethernet cable connection to the ENET TOP
connector. This ENET port is defined as FM1@DTSEC5. This connection is not required to boot
the system. However, it is useful in loading the boot images from an external boot image source.
Figure 13. Ethernet and Serial Connections.
6. JTAG / COP TAP – Optional: For additional development purposes, a TAP pod (such as
CodeWarrior USB TAP) can be attached to the COP/JTAG_TAP header at the location J216 on
the board. CCS software application is installed on the PC to support this system control interface.
The red cable edge should be oriented toward the left side of the connector where pin 1 is located,
as shown in Figure 14.
7. PROMJET Adapter – Optional: A PROMJET (USB) adapter can also be attached at the
PROMJET header (U112) for the purposes of downloading boot images. Note orientation of the
PROMJET pod so that pin 1 is aligned properly as shown in Figure 14.

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Connections and Switch Settings
Figure 14. JTAG / COP TAP and PROMJET Adapter Attached to Board
4.2 Switch Settings
Ensure that the switch settings for SW1 through SW9 are configured as shown in Figure 15. For more
details on decoding the switch settings, refer to the T4240 QDS Reference Manual.
Figure 15. SW1-SW9 Switch Settings
4.2.1 Default Switch Settings
The default switch settings for T4240 QDS are:
SW1= 0x24 SW2= 0xfe SW3= 0x00 SW4= 0x50 SW9= 0x1f SW5= 0xe2 SW6= 0x0f SW7=
0xfa SW8= 0xcd

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Powering up and Booting System
• It is important to have SW1= 0x24. This setting lets RCW to be fetched from the on-board I2C
EEPROM. Note that for rev 1 T4240 devices, the RCW can not be sourced from NOR flash, so the
I2C EEPROM is used as the default RCW location. As a backup, the RCW is also stored in the
on-board eMMC device. The eMMC RCW image is accessed if SW1= 0x20 and SW2= 0b0xxx xxxx.
• For PROMJET operation, SW6 position 1-4 should be 1000.
•SW9= 0x1f connects SD4 serdes lanes 4-7 to the SATA connectors. For SRIO serdes connections
in slots 6 and 8, SW9= 0x5f. This connects SD4 lanes 4-7 to slot 8.
5 Powering up and Booting System
To power-up and boot the T4240 QDS board:
1. Apply Hot Power to the system board by toggling the switch on the back of the 600W power
supply. Only the following LEDs should illuminate (HOT_3V and HOT_5V).
Figure 16. LEDs Illuminated on Applying Hot Power
2. Power-on the T4240 QDS board by pressing the red POWER pushbutton switch (SW11), as
shown in Figure 17.

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Powering up and Booting System
Figure 17. Red POWER Pushbutton Switch
3. After a few seconds, the board will power on with the LEDs illuminated as shown in the following
figures, and the system will begin displaying the uboot output on the COM port screen.
Figure 18. Power LEDs After Power-on: All ON Except POVDD

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Powering up and Booting System
Figure 19. PASS LED ON After Power-on: All Others are OFF
Figure 20. M7 LED ON After Power-on: All Others are OFF
4. The following uboot text should be displayed on the COM port screen:
U-Boot 2012.10 (Dec 08 2012 - 22:38:39)

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Powering up and Booting System
CPU0: T4240E, Version: 1.0, (0x82480010)
Core: E6500, Version: 1.0, (0x80400010)
Clock Configuration:
CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz,
CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz,
CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667 MHz,
CCB:666.667 MHz,
DDR:800 MHz (1600 MT/s data rate) (Asynchronous), IFC:166.667 MHz
FMAN1: 444.444 MHz
FMAN2: 333.333 MHz
QMAN: 333.333 MHz
PME: 333.333 MHz
L1: D-cache 32 kB enabled
I-cache 32 kB enabled
Board: T4240QDS, Sys ID: 0x1e, Sys Ver: 0x22, vBank: 0
FPGA: v3 (T4240QDS_2012_1113_1114), build 438 on Tue Nov 13 17:14:23 2012
Reset Configuration Word (RCW):
00000000: 14180019 0c101914 00000000 00000000
00000010: 04383063 30548c00 1c020000 1d000000
00000020: 00000000 ee0000ee 00000000 000307fc
00000030: 00000000 00000000 00000000 00000020
SERDES Reference Clocks: SERDES1=125MHz SERDES2=125MHz SERDES3=100MHz SERDES4=100MHz
I2C: ready
SPI: ready
DRAM: Initializing....using SPD
Detected UDIMM 9JSF25672AZ-2G1KZ
Detected UDIMM 9JSF25672AZ-2G1KZ
Detected UDIMM 9JSF25672AZ-2G1KZ
4 GiB left unmapped
DDR: 6 GiB (DDR3, 64-bit, CL=11, ECC on)
DDR Controller Interleaving Mode: 3-way 4KB
Flash: 128 MiB
L2: 2048 KB enabled
enable l2 for cluster 1 fec60000
enable l2 for cluster 2 feca0000

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Powering up and Booting System
Corenet Platform Cache: 1536 KB enabled
Using SERDES1 Protocol: 1 (0x1)
Using SERDES2 Protocol: 28 (0x1c)
Using SERDES3 Protocol: 6 (0x6)
Using SERDES4 Protocol: 12 (0xc)
SRIO1: enabled
SRIO2: disabled
NAND: 512 MiB
MMC: FSL_SDHC: 0
EEPROM: NXID v1
PCIe1: Root Complex, x4, regs @ 0xfe240000
PCIe1: Bus 00 - 01
PCIe2: disabled
PCIe3: Root Complex, x4, regs @ 0xfe260000
PCIe3: Bus 02 - 03
PCIe4: disabled
In: serial
Out: serial
Err: serial
Net: Fman1: Uploading microcode version 106.4.6
Fman2: Uploading microcode version 106.4.6
PHY reset timed out
PHY reset timed out
PHY reset timed out
PHY reset timed out
PHY reset timed out
PHY reset timed out
PHY reset timed out
FM1@DTSEC5 [PRIME], FM2@DTSEC1, FM2@DTSEC2, FM2@DTSEC3, FM2@DTSEC4, FM2@DTSEC5, FM2@DTSEC6,
FM2@DTSEC9, FM2@DTSEC10
Hit any key to stop autoboot: 0
WARNING: adjusting available memory to 30000000
## Booting kernel from Legacy Image at e8020000 ...
Image Name: Linux-3.0.51-rt75
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 4287063 Bytes = 4.1 MiB

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Powering up and Booting System
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at e9300000 ...
Image Name: fsl-image-flash-t4240qds-2012120
Image Type: PowerPC Linux RAMDisk Image (gzip compressed)
Data Size: 5984667 Bytes = 5.7 MiB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
## Flattened Device Tree blob at e8800000
Booting using the fdt blob at 0xe8800000
Uncompressing Kernel Image ... OK
Loading Ramdisk to 2fa4a000, end 2ffff19b ... OK
Loading Device Tree to 03fdc000, end 03fff43f ... OK
Using T4240 QDS machine description
MMU: Supported page sizes
4 KB as direct
1024 KB as direct
2048 KB as direct
4096 KB as direct
16384 KB as direct
65536 KB as direct
262144 KB as direct
1048576 KB as direct
MMU: Book3E HW tablewalk not supported
Found initrd at 0xc00000002fa4a000:0xc00000002ffff19b
No /soc@ffe000000/qman@318000 property 'fsl,qman-fqd', using memblock_alloc(0000000000400000)
No /soc@ffe000000/qman@318000 property 'fsl,qman-pfdr', using memblock_alloc(0000000001000000)
Qman ver:0a01,03,00
No /soc@ffe000000/bman@31a000 property 'fsl,bman-fbpr', using memblock_alloc(0000000001000000)
Bman ver:0a02,02,01
pme: No /soc@ffe000000/pme@316000 property 'fsl,pme-pdsr', using
memblock_alloc(0x0000000001000000)
pme: No /soc@ffe000000/pme@316000 property 'fsl,pme-sre', using
memblock_alloc(0x0000000000a00000)

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Powering up and Booting System
No USDPAA memory, no 'usdpaa_mem' bootarg
bootconsole [udbg0] enabled
CPU maps initialized for 2 threads per core
Starting Linux PPC64 #1 SMP Sat Dec 8 19:52:16 CST 2012
-----------------------------------------------------
ppc64_pft_size = 0x0
physicalMemorySize = 0x180000000
ppc64_caches.dcache_line_size = 0x40
ppc64_caches.icache_line_size = 0x40
-----------------------------------------------------
Linux version 3.0.51-rt75 (jenkins@testlink) (gcc version 4.6.2 (GCC) ) #1 SMP Sat Dec 8
19:52:16 CST 2012
CF000012
Setup Arch
[boot]0012 Setup Arch
Found FSL PCI host bridge at 0x0000000ffe240000. Firmware bus number: 0->1
PCI host bridge /pcie@ffe240000 ranges:
MEM 0x0000000c00000000..0x0000000c1fffffff -> 0x00000000e0000000
IO 0x0000000ff8000000..0x0000000ff800ffff -> 0x0000000000000000
/pcie@ffe240000: PCICSRBAR @ 0xdf000000
/pcie@ffe240000: Setup 64-bit PCI DMA window
/pcie@ffe240000: DMA window size is 0xdf000000
Found FSL PCI host bridge at 0x0000000ffe260000. Firmware bus number: 0->1
PCI host bridge /pcie@ffe260000 ranges:
MEM 0x0000000c40000000..0x0000000c5fffffff -> 0x00000000e0000000
IO 0x0000000ff8020000..0x0000000ff802ffff -> 0x0000000000000000
/pcie@ffe260000: PCICSRBAR @ 0xdf000000
/pcie@ffe260000: Setup 64-bit PCI DMA window
/pcie@ffe260000: DMA window size is 0xdf000000
T4240 QDS board from Freescale Semiconductor
Zone PFN ranges:
DMA 0x00000000 -> 0x00080000
Normal 0x00080000 -> 0x00180000
Movable zone start PFN for each node
early_node_map[1] active PFN ranges

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Powering up and Booting System
0: 0x00000000 -> 0x00180000
MMU: Allocated 2112 bytes of context maps for 255 contexts
CF000015
Setup Done
[boot]0015 Setup Done
PERCPU: Embedded 13 pages/cpu @c000000009500000 s23936 r0 d29312 u65536
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 1551360
Kernel command line: root=/dev/ram rw console=ttyS0,115200
PID hash table entries: 4096 (order: 3, 32768 bytes)
Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
Placing 64MB software IO TLB between c00000000a27d000 - c00000000e27d000
software IO TLB at phys 0xa27d000 - 0xe27d000
Memory: 6042208k/6291456k available (9564k kernel code, 249248k reserved, 1112k data, 854k bss,
324k init)
Hierarchical RCU implementation.
RCU debugfs-based tracing is enabled.
CONFIG_RCU_FANOUT set to non-default value of 32
NR_IRQS:512 nr_irqs:512 16
mpic: Setting up MPIC " OpenPIC " version 1.2 at ffe040000, max 24 CPUs
mpic: ISU size: 512, shift: 9, mask: 1ff
mpic: Initializing for 512 sources
clocksource: timebase mult[6000002] shift[22] registered
Console: colour dummy device 80x25
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 256
mpic: requesting IPIs...
Brought up 24 CPUs
devtmpfs: initialized
xor: measuring software checksum speed
8regs : 3382.000 MB/sec
8regs_prefetch: 2988.000 MB/sec
32regs : 3274.000 MB/sec
32regs_prefetch: 3000.000 MB/sec
xor: using function: 8regs (3382.000 MB/sec)

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Powering up and Booting System
NET: Registered protocol family 16
EDAC PCI0: Giving out device to module 'MPC85xx_edac' controller 'mpc85xx_pci_err': DEV
'ffe240000.pcie' (INTERRUPT)
MPC85xx_edac acquired irq 494 for PCI Err
MPC85xx_edac PCI err registered
EDAC PCI1: Giving out device to module 'MPC85xx_edac' controller 'mpc85xx_pci_err': DEV
'ffe260000.pcie' (INTERRUPT)
MPC85xx_edac acquired irq 492 for PCI Err
MPC85xx_edac PCI err registered
PCI: Probing PCI hardware
pci 0000:00:00.0: ignoring class b20 (doesn't match header type 01)
pci 0000:00:00.0: PCI bridge to [bus 01-ff]
pci 0001:00:00.0: ignoring class b20 (doesn't match header type 01)
pci 0001:00:00.0: PCI bridge to [bus 01-ff]
pci 0000:00:00.0: PCI bridge to [bus 01-01]
pci 0000:00:00.0: bridge window [io 0x10000-0x1ffff]
pci 0000:00:00.0: bridge window [mem 0xc00000000-0xc1fffffff]
pci 0000:00:00.0: bridge window [mem pref disabled]
pci 0001:00:00.0: PCI bridge to [bus 01-01]
pci 0001:00:00.0: bridge window [io 0x21000-0x30fff]
pci 0001:00:00.0: bridge window [mem 0xc40000000-0xc5fffffff]
pci 0001:00:00.0: bridge window [mem pref disabled]
bio: create slab <bio-0> at 0
raid6: int64x1 480 MB/s
raid6: int64x2 808 MB/s
raid6: int64x4 1212 MB/s
raid6: int64x8 1223 MB/s
raid6: altivecx1 1437 MB/s
raid6: altivecx2 1816 MB/s
raid6: altivecx4 2823 MB/s
raid6: altivecx8 3000 MB/s
raid6: using algorithm altivecx8 (3000 MB/s)
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub