Holtek HTG2190 User manual

HTG2190
8-Bit 1024 Pixel Dot Matrix LCD MCU Series
Rev. 1.20 1 July 5, 2002
Features
·Operating voltage: 2.4V~3.6V
·64K´16 bits program ROM
·2.3K´8 bits data RAM
·15~39 bidirectional I/O lines
·16 common´40~64 segment LCD driver
·Two 16-bit programmable timer/event counters with
overflow interrupts
·One 8-bit programmable timer with 8-stage prescaler
for PFD
·One 8-bit programmable timer with 8-stage prescaler
for time base
·One 8-bit PWM audio output to directly drive speaker
or buzzer
·One 12-bit current type D/A output with 4-bit volume
control
·R to F function for temperature measurement
·Synchronous serial interface
·On-chip RC oscillator for system clock
·32768Hz crystal oscillator for time base and LCD
driver
·Watchdog Timer
·HALT function and wake-up feature reduce power
consumption
·Eight-level subroutine nesting
·Bit manipulation instructions
·63 powerful instructions
·Built-in supply voltage detection circuit
·One interrupt input
·128-pin QFP package
General Description
The HTG2190 is an 8-bit high performance RISC-like
microcontroller capable of driving 1024 pixel (max.)
LCD display. Its single cycle instruction and two-stage
pipeline architecture make it suitable for high speed ap-
plications. The device is suited for use in multiple LCD
low power applications among which are calculators,
clock timer, game, scales, leisure products, other hand
held LCD products and battery operated systems in par-
ticular.

Block Diagram
HTG2190
Rev. 1.20 2 July 5, 2002
P r o g r a m
C o u n t e r
P r o g r a m
R O M
I n s t r u c t i o n
R e g i s t e r
I n s t r u c t i o n
D ecoder
T i m i n g
G e n e r a t i o n
O S C O O S C I
R E S
V D D
V S S
I n t e r r u p t
C i r c u i t
I N T C
M P 0
M P 1 MUX
M U X
D T
M e m o r y
L U
S h i f t e r
S T T U S
C C
T M R 1
T M R 1 C
MUX
S Y S C L K / 4
P B 6 / T M R 1
W D T S
W D T P r e s c a l e r
¸
256 W D T R C
O S C
1 6 b i t
T M R 0
T M R 0 C
MUX
S Y S C L K / 4
P B 7 / T M R 0
1 6 b i t
P D C
P D
P O R T D
P D 0 ~ P D 7 / S E G 4 8 ~ S E G 5 5
P E C
P E
P O R T E
P E 0 ~ P E 7 / S E G 4 0 ~ S E G 4 7
S T C K 2
S T C K 3
S T C K 4
S T C K 5
S T C K 6
S T C K 7
P C C
P C
P O R T C
P C 0 ~ P C 7 / S E G 5 6 ~ S E G 6 3
P B C
P B
P O R T B
P B 0 , P B 2 ~ P B 7
X I N / P C 7 / S E G 6 3
X O U T / P C 6 / S E G 6 2
L C D
M e m o r y
L C D D r i v e r
C O M 0 ~ C O M 1 5 S E G 0 ~ 3 9
P E 0 ~ P E 7 / S E G 4 0 ~ S E G 4 7
P D 0 ~ P D 7 / S E G 4 8 ~ S E G 5 5
P C 0 ~ P C 5 / S E G 5 6 ~ S E G 6 1
X O U T / P C 6 / S E G 6 2
X I N / P C 7 / S E G 6 3
8 - s t a g e
P r e s c a l e r
P F D
T M R 2
I N T / S I N
P C
P
P O R T
P 0 ~ P 7
S e r i a l
I n t e r f a c e
8 - s t a g e
P r e s c a l e r
P W M
D /
S C L K / P B 5
I N T / S I N
S O U T / P B 4
P W M D C 1
P W M D C 2
T M R 3 C
T M R 3
3 2 7 6 8 H z C r y s t a l
MUX
S Y S C L K
8 - s t a g e
P r e s c a l e r
8 - s t a g e
P r e s c a l e r
T M R 2 C
MUX
MUX
S Y S C L K
P B 0 / P W M 1
P W M 2 / U D
S T C K 0
S T C K 1
P W M D C 1
P W M D C 2
1 2 b i t s
D /
4 b i t s
V o l u m e
c o n t r o l
R T F
S u p p l y V o l t a g e
D e t e c t i o n
S Y S C L K
S Y S C L K

Pin Assignment
HTG2190
Rev. 1.20 3 July 5, 2002
126127
H T G 2 1 9 0
1 2 8 Q F P - A
4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 04 0 5 1 5 2 5 3
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
1 2 8
S E G 3 5
S E G 3 4
S E G 3 3
S E G 3 2
S E G 3 1
S E G 3 0
S E G 2 9
S E G 2 8
S E G 2 7
S E G 2 6
S E G 2 5
S E G 2 4
S E G 2 3
S E G 2 2
S E G 2 1
S E G 2 0
S E G 1 9
S E G 1 8
S E G 1 7
S E G 1 6
S E G 1 5
S E G 1 4
S E G 1 3
S E G 1 2
S E G 1 1
S E G 1 0
S E G 9
S E G 8
S E G 7
S E G 6
S E G 5
S E G 4 3 9 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4
N C
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
P B 2
P B 3
P B 4 / S O U T
P B 5 / S C L K
P B 6 / T M R 1 / R T F
P B 7 / T M R 0
P B 0 / P W M 1
A U D / P W M 2
R E S
I N T / S I N
V D D
O S C 1
N C
N C
N C
N C
O S C 0
N C
V S S
N C
C A P 1
N C
N C
N C
125 122123 1 2 4 1 2 1 1201191181171161151141131121111101 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3
9 6
9 5
9 4
9 3
9 2
9 1
9 0
8 9
8 8
8 7
8 6
8 5
8 4
8 3
8 2
8 1
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
6 6
6 5
102101100 99 9 8 9 7
3 3 3 4 3 5 3 6 3 7 3 8
N C C A P 2 C A P 3 N C N C N C N C C A P 4 V O U T 4 4 V O U T 3 3 V O U T 2 2 V O U T 1 1 C O M 0 C O M 1 C O M 2 C O M 3 C O M 4 C O M 5 C O M 6 C O M 7 C O M 8 C O M 9 C O M 1 0 C O M 1 1 C O M 1 2 C O M 1 3 C O M 1 4 C O M 1 5 S E G 0
S E G 1
S E G 2
S E G 3
N C
P A 0
I N / P C 7 S E G 6 3
O U T / P C 6 S E G 6 2
P C 5 / S E G 6 1
P C 4 / S E G 6 0
P C 3 / S E G 5 9
P C 2 / S E G 5 8
P C 1 / S E G 5 7
P C 0 / S E G 5 6
P D 7 / S E G 5 5
P D 6 / S E G 5 4
P D 5 / S E G 5 3
P D 4 / S E G 5 2
P D 3 / S E G 5 1
P D 2 / S E G 5 0
P D 1 / S E G 4 9
P D 0 / S E G 4 8
P E 7 / S E G 4 7 P E 6 / S E G 4 6 P E 5 / S E G 4 5 P E 4 / S E G 4 4 P E 3 / S E G 4 3 P E 2 / S E G 4 2 P E 1 / S E G 4 1 P E 0 / S E G 4 0
S E G 3 9 S E G 3 8 S E G 3 7 S E G 3 6
N C N C

Pad Assignment
Chip size: 3420 ´3855 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pad Coordinates Unit: mm
Pad No. X Y Pad No. X Y
1-1561.08 1781.81 58 1214.37 -1797.56
2-1577.85 1535.18 59 1156.72 -1465.33
3-1577.85 1428.50 60 1331.47 -1797.56
4-1577.85 1322.07 61 1442.47 -1797.56
5-1577.85 1215.39 62 1559.56 -1797.56
6-1577.85 1108.96 63 1264.67 -1465.33
7-1577.85 1002.28 64 1492.25 -1516.38
8-1577.85 895.86 65 1492.25 -1404.62
HTG2190
Rev. 1.20 4 July 5, 2002
5 8
2
5 9
3
6 0
4
6 1
5
6 2
6
6 3
7
6 4
8
6 5
9
6 6
1 0
6 7
1 1
6 8
1 2
6 9
1 3
7 0
1 4
7 1
1 5
7 2
1 6
7 3
1 7
7 4
1 8 7 5
1 9
7 6
2 0
7 7
2 1
7 8
2 2
7 9
2 3
8 0
2 4
8 1
2 5
8 2
2 6
8 3
2 7
8 4
2 8
8 5
2 9
8 6
3 0
8 7
3 1
8 8
3 2
8 9
3 3
9 0
3 4
9 1
3 5
9 2
3 6
9 3
3 7
9 4
3 8
9 5
3 9
9 6
4 0
9 7
4 1
9 8
4 2
9 9
4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7
( 0 , 0 )
4 3
1 0 01 0 1
1 0 21 0 31 0 41 0 51 0 61 0 71 0 81 0 91 1 01 1 1
1 1 2
1 1 31 1 4
1
S E G 3 5
S E G 3 4
S E G 3 3
S E G 3 2
S E G 3 1
S E G 3 0
S E G 2 9
S E G 2 8
S E G 2 7
S E G 2 6
S E G 2 5
S E G 2 4
S E G 2 3
S E G 2 2
S E G 2 1
S E G 2 0
S E G 1 9
S E G 1 8
S E G 1 7
S E G 1 6
S E G 1 5
S E G 1 4
S E G 1 3
S E G 1 2
S E G 1 1
S E G 1 0
S E G 9
S E G 8
S E G 7
S E G 6
S E G 5
C A P 4 V O U T 4 4 V O U T 3 3 V O U T 2 2 V O U T 1 1 C O M 0 C O M 1 C O M 2 C O M 3 C O M 4 C O M 5 C O M 6 C O M 7 C O M 8 C O M 9 C O M 1 0 C O M 1 1 C O M 1 2 C O M 1 3 C O M 1 4 C O M 1 5 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 C A P 1 C A P 2 C A P 3
T R I M 1
T R I M 3
T R I M 4
T R I M 2
O S C O
V S S
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
P B 2
P B 3
P B 4 / S O U T
P B 5 / S C L K
P B 6 / T M R 1 / R T F
P B 7 / T M R 0
P B 0 / P W M 1
P W M 2 / A U D
R E S
I N T / S I N
V D D
O S C I
S E G 3 6
I N / P C 7 / S E G 6 3
O U T / P C 6 / S E G 6 2
P C 5 / S E G 6 1
P C 4 / S E G 6 0
P C 3 / S E G 5 9
P C 2 / S E G 5 8
P C 1 / S E G 5 7
P C 0 / S E G 5 6
P D 7 / S E G 5 5
P D 6 / S E G 5 4
P D 5 / S E G 5 3
P D 4 / S E G 5 2
P D 3 / S E G 5 1
P D 2 / S E G 5 0
P D 1 / S E G 4 9
P D 0 / S E G 4 8
P E 7 / S E G 4 7
P E 6 / S E G 4 6
P E 5 / S E G 4 5
P E 4 / S E G 4 4
P E 3 / S E G 4 3
P E 2 / S E G 4 2
P E 1 / S E G 4 1
P E 0 / S E G 4 0
S E G 3 9 S E G 3 8 S E G 3 7

Pad No. X Y Pad No. X Y
9-1577.85 789.18 66 1264.67 -1351.53
10 -1577.85 682.75 67 1240.28 -1235.20
11 -1577.85 576.33 68 1492.25 -1119.38
12 -1577.85 469.65 69 1515.36 -991.36
13 -1577.85 363.22 70 1517.14 -867.16
14 -1577.85 256.54 71 1517.14 -745.49
15 -1577.85 150.11 72 1517.14 -596.65
16 -1577.85 43.43 73 1517.14 -422.91
17 -1577.85 -62.99 74 1517.14 -271.27
18 -1577.85 -169.67 75 1517.14 -154.18
19 -1577.85 -276.10 76 1517.14 -40.13
20 -1577.85 -382.78 77 1517.14 76.45
21 -1577.85 -489.20 78 1517.14 190.50
22 -1577.85 -595.88 79 1517.14 307.34
23 -1577.85 -702.31 80 1517.14 421.39
24 -1577.85 -809.99 81 1517.14 538.23
25 -1577.85 -915.42 82 1517.14 652.27
26 -1577.85 -1022.10 83 1517.14 768.86
27 -1577.85 -1128.52 84 1517.14 882.90
28 -1577.85 -1235.20 85 1517.14 999.74
29 -1577.85 -1341.63 86 1517.14 1113.79
30 -1577.85 -1448.31 87 1517.14 1230.63
31 -1577.85 -1554.73 88 1544.83 1734.82
32 -1577.85 -1797.56 89 1427.99 1734.82
33 -1471.17 -1797.56 90 1313.94 1734.82
34 -1364.74 -1797.56 91 1196.85 1734.82
35 -1258.06 -1797.56 92 1083.06 1734.82
36 -1151.64 -1797.56 93 965.96 1734.82
37 -1044.96 -1797.56 94 851.92 1734.82
38 -938.53 -1797.56 95 735.08 1734.82
39 -831.85 -1797.56 96 621.03 1734.82
40 -725.42 -1797.56 97 503.94 1734.82
41 -618.74 -1797.56 98 389.89 1734.82
42 -512.32 -1797.56 99 273.05 1734.82
43 -405.64 -1797.56 100 159.00 1734.82
44 -299.21 -1797.56 101 41.91 1734.82
45 -192.53 -1797.56 102 -72.14 1734.82
46 -86.11 -1797.56 103 -188.98 1734.82
47 20.57 -1797.56 104 -303.02 1734.82
48 127.00 -1797.56 105 -420.12 1734.82
49 233.45 -1797.56 106 -534.16 1734.82
50 340.11 -1797.56 107 -651.00 1734.82
51 446.53 -1797.56 108 -765.05 1734.82
52 553.21 -1797.56 109 -882.14 1734.82
53 659.64 -1797.56 110 -995.93 1734.82
54 766.83 -1797.56 111 -1113.03 1734.82
55 873.25 -1797.56 112 -1241.55 1781.81
56 979.68 -1797.56 113 -1347.98 1781.81
57 1100.07 -1797.56 114 -1454.66 1781.81
HTG2190
Rev. 1.20 5 July 5, 2002

Pad Descriptions
Pad No. Pad Name I/O Mask Option Description
37~1
114~112 SEG0~SEG39 O ¾LCD segment signal output
53~38 COM0~COM15 O ¾LCD common signal output
54~57 VOUT11, VOUT22
VOUT33, VOUT44 O¾LCD driving power generated
62, 61,
60, 58
CAP1, CAP2,
CAP3, CAP4 ¾¾
LCD system voltage booster condenser connecting termi-
nal.
59, 63
66, 67 TRIM1~TRIM4 ¾¾
Test pin only
64 VSS ¾¾ Negative power supply, ground
68
65
OSCI
OSCO
I
OCrystal or RC
OSCI and OSCO are connected to an RC network or a crys-
tal (by mask option) for the internal system clock. In the
case of RC operation,OSCI is connected to the RC network
of the internal system clock.
69 VDD ¾¾ Positive power supply
70 INT/SIN I INT or Serial
Data Input
Selectable as external interrupt Schmitt trigger input or serial
data input by mask option. External interrupt Schmitt trigger
input with pull-high resistor. Edge triggered activated on INT
or Serial data input a high to low transition. Serial data input
with pull-high resistor. INT shares pad with SIN.
71 RES I¾Schmitt trigger reset input. Active low without pull-high re-
sistor.
72 PWM2/AUD O
PWM2 CMOS
Output or
AUD Output
Selectable as negative PWM CMOS output or audio output
by mask option. PWM2 share pad with AUD.
73 PB0/PWM1
I/O
or
O
I/O or
PWM1 CMOS
Output
Selectable as bidirectional input/output or positive PWM
CMOS output by mask option. On bidirectional input/output
mode, software instructions determine whether each pad is
a CMOS output or Schmitt trigger input with pull-high resis-
tor. PB0 shares pad with PWM1.
74 PB7/TMR0
I/O
or
I
I/O or
TMR0 Input
Selectable as bidirectional input/output or TMR0 input by
mask option. On bidirectional input/output mode, software
instructions determine whether it is a CMOS output or
Schmitt trigger input with pull-high resistor. On TMR0 input
mode, it uses Timer/Event Counter 0. Software can be
optioned with or without pull-high resistor. PB7 shares pad
with TMR0.
75 PB6/TMR1/RTF
I/O
or
I
I/O or
TMR1 Input
or
RTF Input
Selectable as bidirectional input/output or TMR1 input or
RTF input by mask option. On bidirectional input/output
mode, software instructions determine whether it is a
CMOS output or Schmitt trigger input with pull-high resistor.
On TMR1 and RTF input mode, it uses Timer/Event Coun-
ter 1. Software can be optioned with or without pull-high re-
sister and be option the RTF function disable or enable.
PB6 and TMR1 share pad with RTF.
HTG2190
Rev. 1.20 6 July 5, 2002

Pad No. Pad Name I/O Mask Option Description
76 PB5/SCLK I/O I/O or
SCLK Signal
Selectable as bidirectional input/output or serial interface
clock signal by mask option. On bidirectional input/output
mode, software instructions determine whether it is a CMOS
output or Schmitt trigger input .
Serial I/O interface clock signal.
At Master mode: SCLK should be set as serial clock output
pin and after 8 clock output from SCLK terminal, clock out-
put is automatically suspended and SCLK terminal is fixed
at a high level.
At Slave mode: SCLK should be set as serial clock input pin
and after 8 clock input from SCLK terminal, subsequent
clock input are masked. PB5 shares pad with SLCK
77 PB4/SOUT
I/O
or
O
I/O or
SOUT Output
Selectable as bidirectional input/output or serial data output
master by mask option. On bidirectional input/output
mode, software instructions determine whether it is a
CMOS output or Schmitt trigger input . On serial output mode,
SOUT pin is a CMOS output. PB4 shares pad with SOUT.
78
79
PB3
PB2 I/O ¾
Software instructions determine whether it is a CMOS out-
put or Schmitt trigger input with pull-high resistor. When the
PB6/TMR1/RTF pad is selected to be in RTF mode, the
PB3, PB2 pull-high resistor is not present.
87~80 PA0~PA7 I/O
Wake-up
or
None Wake-up
Bidirectional 8-bit input/output port. Each bit can be config-
ured as a wake-up input by mask option. Software instruc-
tions determine whether it is a CMOS output or Schmitt
trigger input with pull-high resistor.
88
89
XIN/PC7/SEG63
XOUT/PC6/SEG62
I
or
I/O
or
O
Crystal or I/O
or Segment
Output
Selectable as 32768Hz crystal or bidirectional input/output
or segment signal output by mask option. 32768Hz crystal
for timer3 and LCD clock source. XOUT and PC6 share
with SEG62 Pad,XIN and PC7 share with SEG63 pad.
95~90
103~96
111~104
PC0~5/SEG56~61
PD0~7/SEG48~55
PE0~7/SEG40~47
I/O
or
O
I/O or
Segment Output
Three bidirectional 8-bit input/output ports. Software in-
structions determine the CMOS output or Schmitt trigger in-
put with pull-high resistor. PC, PD, PE can be individually
optioned for segment output by mask option. PC0~PC7
share pads with SEG56~SEG63, PD0~PD7 share pads
with SEG48~SEG55, and PE0~PE7 share pads with
SEG40~SEG47.
Absolute Maximum Ratings
Supply Voltage .........................................-0.3V to 3.6V Storage Temperature ............................-50°Cto125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...............................0°Cto70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings²may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
HTG2190
Rev. 1.20 7 July 5, 2002

D.C. Characteristics Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage ¾¾ 2.4 ¾3.6 V
IDD Operating Current (RC OSC) 3V No load, fSYS=4MHz ¾1 1.5 mA
ISTB1 Standby Current (RTC ON, LCD ON) 3V No load, HALT ¾930
mA
ISTB2 Standby Current (RTC ON, LCD OFF) 3V No load, HALT ¾3.5 15 mA
VIL1 Input Low Voltage for I/O Ports 3V ¾0¾0.9 V
VIH1 Input High Voltage for I/O Ports 3V ¾2.1 ¾3V
VIL2 Input Low Voltage (TMR0, TMR1, INT)3V ¾0¾0.7 V
VIH2 Input High Voltage (TMR0, TMR1, INT)3V ¾2.3 ¾3V
VIL3 Input Low Voltage (RES)3V
¾¾
1.5 ¾V
VIH3 Input High Voltage (RES)3V
¾¾
2.4 ¾V
IOL1 I/O Ports Sink Current 3V VOL=0.3V 1.5 4 ¾mA
IOH1 I/O Ports Source Current 3V VOH=2.7V -1-2¾mA
VLCD LCD Voltage 3V ¾3.96 4.4 4.84 V
IOL2 PWM1/PWM2 Sink Current 3V VOL=0.3V 12 16 ¾mA
IOH2 PWM1/PWM2 Source Current 3V VOH=2.7V -8-10 ¾mA
IOL3 Audio Sink Current 3V VOL=0.3V 1.5 2 ¾mA
IOH3 Audio Source Current 3V VOH=2.7V -1.5 -2¾mA
IOL4 Segment 0~39 Output Sink Current 3V VOL=0.3V 80 130 ¾mA
IOH4 Segment 0~39 Output Source Current 3V VOH=2.7V -50 -90 ¾mA
IOL5 Segment 40~63 Output Sink Current 3V VOL=0.3V 40 80 ¾mA
IOH5 Segment 40~63 Output Source Current 3V VOH=2.7V -30 -60 ¾mA
RPH Pull-high Resistance of I/O Ports,
TMR0, TMR1 & INT 3V ¾30 60 100 kW
A.C. Characteristics Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
fSYS System Clock (RC OSC) 3V ¾400 ¾4000 kHz
fTIMER Timer Input Frequency (TMR0,TMR1) 3V ¾0¾4000 kHz
tWDTOSC Watchdog Oscillator 3V ¾45 90 180 ms
tWDT Watchdog Time-out Period (RC) 3V Without WDT
prescaler 12 23 45 ms
tRES External Reset Low Pulse width ¾¾ 1¾¾ms
tSST System Start-up Timer Period ¾Power-up or wake-up
from HALT ¾1024 ¾tSYS
tINT Interrupt Pulse Width ¾¾ 1¾¾ms
Note: tSYS=1/fSYS
HTG2190
Rev. 1.20 8 July 5, 2002

HTG2190
Rev. 1.20 9 July 5, 2002
T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4
F e t c h I N S T ( P C )
E x e c u t e I N S T ( P C - 1 ) F e t c h I N S T ( P C + 1 )
E x e c u t e I N S T ( P C ) F e t c h I N S T ( P C + 2 )
E x e c u t e I N S T ( P C + 1 )
P C P C + 1 P C + 2
S y s t e m C l o c k
O S C 2 ( R C o n l y )
P C
B a n k 0
B a n k 1
B a n k 2
B a n k 7
8192´1 6
B i t s
0000H
1FFFH
S t a c k
B a n k P o i n t e r
R e g i s t e r
B i t 7 , B i t 6 , B i t 5
A 1 5 , A 1 4 , A 1 3
B u ffe r
L a t c h d a t a o n E x e c u t i o n o f J u m p o r C a l l I n s t r u c t i o n
6 4 K P r o
g
r a m R O M A d d r e s s i n
g
A r c h i t e c t u r e
1 3 b i t s
P r o g r a m
C o u n t e r
2000H
3FFFH 4000H
5 F F F H E 000H
FFFFH
Execution flow
Functional Description
Execution flow
The system clock for the HTG2190 is derived from ei-
ther a crystal or an RC oscillator. It is internally divided
into four non-overlapping clocks. One instruction cycle
consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute within one cycle. If an instruc-
tion changes the program counter, two cycles are
required to complete the instruction.
Program counter -PC
The 13-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex-
ecuted.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle takes its place while the correct instruction is ob-
tained.
The lower byte of the program counter (PCL) is a
read/write register (06H). Moving data into the PCL per-
Mode Program ROM Address
*15 *14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
External or serial
input interrupt 0000000000000100
Timer/Event
Counter 0 overflow 0000000000001000
Timer/Event
Counter 1 overflow 0000000000001100
Timer 2 overflow 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Timer 3 overflow 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0
Skip PC+2
Loading PCL *15 *14 *13 *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, call branch BP.7 BP.6 BP.5 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from
subroutine S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Program ROM address
Note: *15~*0: Program ROM address S15~S0: Stack register bits
@7~@0: PCL bits BP.5~BP.7: Bit 5~7 of bank pointer (04H)
#12~#0: Instruction code bits

HTG2190
Rev. 1.20 10 July 5, 2002
forms a short jump. The destination must be within 256
locations.
When a control transfer takes place, an additional
dummy cycle is required.
Program memory -ROM
The program memory, which contains executable pro-
gram instructions, data and table information, is com-
posed of a 65536 x 16 bit format. However as the PC
(program counter) is comprised of only 13 bits, the re-
maining 3 ROM address bits are managed by dividing
the program memory into 8 banks, each bank having a
range between 0000H and 1FFFH. To move from the
present ROM bank to a different ROM bank, the higher 3
bits of the ROM address are set by the BP (Bank
Pointer), while the remaining 13 bits of the PC are set in
the usual way by executing the appropriate jump or call
instruction. As the full 16 address bits are latched during
the execution of a call or jump instruction, the correct
value of the BP must first be setup before a jump or call
is executed. When either a software or hardware inter-
rupt is received, note that no matter which ROM bank
the program is in the program will always jump to the ap-
propriate interrupt service address in Bank 0. The origi-
nal full 16 bit address will be stored on the stack and
restored when the relevant RET/RETI instruction is exe-
cuted, automatically returning the program to the origi-
nal ROM bank. This eliminates the need for
programmers to manage the BP when interrupts occur.
Certain locations in Bank 0 of program memory are re-
served for special usage:
·ROM Bank 0 (BP5~BP7=000B)
The ROM bank 0 ranges from 0000H to 1FFFH.
·Location 000H
This area is reserved for the initialization program. Af-
ter a chip reset, the program always begins execution
at location 000H.
·Location 004H
This area is reserved for the external interrupt or serial
input interrupt service routine. If the INT input pin is
activated, and the interrupt is enabled and the stack is
not full, the program will jump to location 004H and be-
gins execution.
·Location 008H/00CH
This area is reserved for the Timer/Event Counter 0/1 in-
terrupt service program. If a timer interrupt results from a
Timer/Event Counter 0/1 overflow, and if the interrupt is
enabled and the stack is not full, the program will jump to
location 008H/00CH and begins execution.
·Location 010H/014H
This area is reserved for the timer 2/3 interrupt service
program. If a timer interrupt resulting from a timer 2/3
overflow, and if the interrupt is enabled and the stack
is not full, the program will jump to location
010H/014H and begins execution.
·Location 018H
This area is reserved for the PWM D/A buffer empty
interrupt service program. After the system latch a D/A
code at RAM address 28H, the interrupt is enable, and
the stack is not full, the program begins execution at
location 018H.
·Location 020H
For best condition, this location is reserved as the be-
ginning when writing a program.
·ROM Bank 1~7 (BP5~BP7=001B~111)
The range of the ROM starts from n000H to
(n+1)FFFH. (n=2,4,6,8,10,12,14)
·Table location
Any location in the ROM space can be used as look up
table. The instructions TABRDC [m] (use for any
bank) and TABRDL [m] (only used for last page of pro-
gram ROM) transfers the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
0000H
0004H
0008H
D e v i c e i n i t i a l i z a t i o n p r o g r a m
E x t e r n a l o r s e r i a l i n p u t i n t e r r u p t s u b r o u t i n e
T i m e r / e v e n t c o u n t e r 0 i n t e r r u p t s u b r o u t i n e
P r o g r a m
R O M
1 6 b i t s
F F F F H
T i m e r / e v e n t c o u n t e r 1 i n t e r r u p t s u b r o u t i n e
000C H
T i m e r 2 i n t e r r u p t s u b r o u t i n e
T i m e r 3 i n t e r r u p t s u b r o u t i n e
010H
014H
D / A b u f f e r e m p t y i n t e r r u p t
018H
Program memory
Instruction Table Location
*15 *14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
TABRDC [m] #7 #6 #5 #4 #3 #2 #1 #0 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 11111111@7@6@5@4@3@2@1@0
Table location
Note: @7~@0: TBLP register bit7~bit0 *15~*0: Program ROM table address bit15~bit0
#7~#0: TBHP register bit7~bit0