Holtek HT49RU80 User manual

HT49RU80/HT49CU80
LCD Type 8-Bit MCU
Rev. 1.10 1 March 2, 2007
Features
·Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
·8 input lines and 7 output lines
·16 bidirectional I/O lines
·Two external interrupt inputs
·One 8-bit and two 16-bit programmable timer/event
counters with PFD - programmable frequency divider
function
·LCD driver with 48´2, 48´3or47´4 segments
·16K´16 program memory
·576´8 data memory RAM
·Real Time Clock - RTC
·RTC 8-bit prescaler
·Watchdog Timer
·Buzzer output
·On-chip crystal, RC and 32768Hz crystal oscillator
·HALT function and wake-up feature reduce power
consumption
·16-level subroutine nesting
·UART - Universal Asynchronous Receiver
Transmitter
·Bit manipulation instruction
·16-bit table read instruction
·Up to 0.5ms instruction cycle with 8MHz system clock
·63 powerful instructions
·All instructions executed within 1 or 2 machine cycles
·Low voltage reset/detector functions
·100-pin QFP package
General Description
These devices are 8-bit, high performance, RISC archi-
tecture microcontrollers specifically designed for a wide
range of LCD applications. The mask version, the
HT49CU80, is fully pin and functionally compatible with
the OTP version HT49RU80 device.
The advantages of low power consumption, I/O flexibil-
ity, programmable frequency divider, timer functions,
oscillator options, power-down and wake-up functions
and buzzer driver in addition to a flexible and
configurable LCD interface, enhance the versatility of
these devices to control a wide range of LCD-based ap-
plication possibilities such as measuring scales, elec-
tronic multimeters, gas meters, timers, calculators,
remote controllers and many other LCD-based indus-
trial and home appliance applications.
Technical Document
·Tools Information
·FAQs
·Application Note
-HA0017E Controlling the Read/Write Function of the HT24 Series EEPROM Using the HT49 Series MCUs
-HA0024E Using the RTC in the HT49 MCU Series
-HA0025E Using the Time Base in the HT49 MCU Series
-HA0026E Using the I/O Ports on the HT49 MCU Series
-HA0027E Using the Timer/Event Counter in the HT49 MCU Series

Block Diagram
HT49RU80/HT49CU80
Rev. 1.10 2 March 2, 2007
P r o g r a m
C o u n t e r
P r o g r a m
M e m o r y
I n s t r u c t i o n
R e g i s t e r
I n s t r u c t i o n
D ecoder
T i m i n g
G e n e r a t i o n
O S C 2
O S C 4
O S C 1
R E S
V D D
V S S
O S C 3
I n t e r r u p t
C i r c u i t
I T C
M P MUX
M U X
D a t a
M e m o r y
A L U
S h i f t e r
S T A T U S
A C C
P A
P o r t A
MUX
P o r t B
W D T O S C
R T C O S C
O S C 3
O S C 4
R T C
S T A C K
L C D
M e m o r y
B P
L C D D r i v e r
C O M 0 ~
C O M 2
C O M 3 /
S E G 4 7
S E G 0 ~
S E G 4 6
T i m e B a s e
W D T
P C
P C 0 / T X , P C 1 / R X ,
P C 2 ~ P C 7
H A L T
E / D I S
L V D / L V R
T M R 1
T M R 0 O V
fS Y S
T i m e B a s e O u t
fS Y S / 4
fS Y S / 4
fS Y S
R T C O u t
T M R 0
fS Y S / 4
T M R 0 C
T M R 0
MUX
T M R 1 C
T M R 1
MUX
P F D 0
P F D 1
T M R 2
fS Y S / 4
T M R 2 C
T M R 2
MUX
P B 0 / I T 0 , P B 1 / I T 1
P B 2 / T M R 0 , P B 3 / T M R 1
P B 4 / T M R 2 , P B 5 ~ P B 7
P B
P o r t C
P A 0 / B Z , P A 1 / B Z
P A 2 , P A 3 / P F D
PA4~PA7
P o r t D P D 0 / S E G 4 0 , P D 1 / S E G 4 1
P D 2 / S E G 4 2 , P D 3 / S E G 4 3
P D 4 / S E G 4 4 , P D 5 / S E G 4 5
P D 6 / S E G 4 6
P D
T X
R X
U A R T
I T 0 , I T 1

Pin Assignment
HT49RU80/HT49CU80
Rev. 1.10 3 March 2, 2007
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0
8 18 28 38 48 58 68 78 88 99 09 19 29 39 49 59 69 79 89 91 0 0
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
P A 5
C
C
C
C
C
P A 6
P A 7
P B 0 / I T 0
P B 1 / I T 1
P B 2 / T M R 0
P B 3 / T M R 1
P B 4 / T M R 2
P B 5
P B 6
P B 7
P C 0 / T X
P C 1 / R X
P C 2
P C 3
P C 4
P C 5
P C 6
P C 7
C
C
C
C
V M A X
V S S
C S E G 3 7
S E G 3 8
S E G 3 9
P D 0 / S E G 4 0 P D 1 / S E G 4 1 P D 2 / S E G 4 2 P D 3 / S E G 4 3 P D 4 / S E G 4 4 P D 5 / S E G 4 5 P D 6 / S E G 4 6 C O M 3 / S E G 4 7
C O M 2
C O M 1
C O M 0
C 2 C 1 V 2 V 1 V L C D
S E G 9
S E G 1 0
S E G 1 1
C
S E G 1 2
S E G 1 3
S E G 1 4
S E G 1 5
S E G 1 6
S E G 1 7
S E G 1 8
S E G 1 9
S E G 2 0
S E G 2 1
S E G 2 2
S E G 2 3
S E G 2 4
S E G 2 5
S E G 2 6
S E G 2 7
S E G 2 8
S E G 2 9
S E G 3 0
S E G 3 1
C
S E G 3 2
S E G 3 3
S E G 3 4
S E G 3 5
S E G 3 6
S E G 8
S E G 7
S E G 6
S E G 5
S E G 4
S E G 3
S E G 2
S E G 1
S E G 0
O S C 4 O S C 3
V D D
O S C 2 O S C 1
R E S
P A 0 / B Z P A 1 / B Z
P A 2
P A 3 / P F D
P A 4
H T 4 9 R U 8 0 / H T 4 9 C U 8 0
1 0 0 Q F P - A

Pad Description
Pad Name I/O Options Description
PA0/BZ
PA1/BZ
PA2
PA3/PFD
PA4~PA7
I/O
Wake-up
CMOS or NMOS
Pull-high
PA0/PA1 or BZ/BZ
PA3 or PFD
Bidirectional 8-bit input/output port. Each pin on this port can be configured
as a wake-up input by a configuration option. Configuration options deter-
mine whether pins PA0~PA3 are configured as CMOS outputs or NMOS in-
put/output pins. If PA0~PA3 are configured as NMOS input/output pins,
then pull-high options are available but apply to all 4 pins, not individual
pins. Pins PA4~PA7 are always configured as NMOS input/output pins with
pull-high resistors connected. All inputs are Schmitt Trigger types. Pins
PA0, PA1 and PA3 are pin-shared with BZ, BZ and PFD respectively, the
function of which is chosen via configuration options.
PB0/INT0
PB1/INT1
PB2/TMR0
PB3/TMR1
PB4/TMR2
PB5~PB7
I¾
8-bit Schmitt Trigger input port. Each input pin is connected to an internal
pull-high resistor. Pins PB0 and PB1 are pin-shared with INT0 and INT1
respectively. Pins PB2, PB3 and PB4 are pin-shared with TMR0, TMR1
and TMR2 respectively.
PC0/TX
PC1/RX
PC2~PC7
I/O CMOS or NMOS
Pull-high
Bidirectional 8-bit input/output port. Two configuration options determine
whether the four pins PC0~PC3 and the four pins PC4~PC7 are config-
ured as CMOS outputs or NMOS input/output pins. Pins must be config-
ured as CMOS outputs or NMOS input/output pins in blocks of four pins,
individual pins cannot be selected. If pins PC0~PC3 or PC4~PC7 are con-
figured as NMOS input/output pins, then a pull-high option is available for
each block of four pins. Individual pins cannot be selected to have a
pull-high option. All inputs are Schmitt Trigger types. Pins PC0 and PC1
are pin-shared with UART pins TX and RX respectively.
PD0/SEG40~
PD6/SEG46 OCMOS Output or SEG Output
7-bit output port. Each pin can be setup as either a CMOS output or a SEG
output via configuration options.
VLCD I ¾LCD power supply. This pad is implemented for LCD power only. The
VLCD levels can be greater or less than the VDD levels.
VMAX ¾¾ IC maximum voltage, connect to VDD, VLCD or V1.
V1, V2, C1, C2 I ¾LCD voltage pump
COM0~COM2
COM3/SEG47 O1/2, 1/3 or 1/4 Duty
The 1/4 LCD duty cycle configuration option will determine whether pin
COM3/SEG47 is configured as a SEG47 segment driver or as a common
COM3 output driver for the LCD panel. COM0~COM2 are the LCD com-
mon outputs.
SEG0~SEG39 O ¾LCD driver outputs for LCD panel segments
OSC1
OSC2
I
OCrystal or RC
OSC1 and OSC2 are connected to an external RC network or external
crystal (determined by configuration option) for the internal system clock.
For external RC system clock operation, OSC2 is an output pin for 1/4
system clock. If an RTC oscillator on pins OSC3 and OSC4 is used as a
system clock, then the OSC1 and OSC2 pins should be left floating.
OSC3
OSC4
I
O
RTC or
System Clock
OSC3 and OSC4 are connected to a 32768Hz crystal to form a Real Time
Clock for timing purposes or to form a system clock.
RES I¾Schmitt Trigger reset input, active low.
VDD ¾¾ Positive power supply
VSS ¾¾ Negative power supply, ground
HT49RU80/HT49CU80
Rev. 1.10 4 March 2, 2007

Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°Cto125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40°Cto85°C
IOL Total ..............................................................150mA IOH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings²may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage ¾LVR disabled, fSYS=4MHz 2.2 ¾5.5 V
LVR disabled, fSYS=8MHz 3.3 ¾5.5 V
VLCD LCD Power Supply (Note *) ¾VA£5.5V 2.2 ¾5.5 V
IDD1 Operating Current
(Crystal OSC, RC OSC)
3V No load, fSYS=4MHz,
UART Off
¾12mA
5V ¾35mA
IDD2 Operating Current
(Crystal OSC, RC OSC)
3V No load, fSYS=4MHz,
UART On
¾1.5 3.0 mA
5V ¾36mA
IDD3 Operating Current
(Crystal OSC, RC OSC) 5V No load, fSYS=8MHz, UART Off ¾48mA
IDD4 Operating Current
(Crystal OSC, RC OSC) 5V No load, fSYS=8MHz, UART On ¾510mA
IDD5
Operating Current
(fSYS=RTC OSC)
3V
No load, UART Off ¾0.3 0.6 mA
5V ¾0.6 1 mA
ISTB1
Standby Current
(*fS=fSYS/4)
3V No load, system HALT,
LCD Off at HALT, UART Off
¾¾ 1mA
5V ¾¾ 2mA
ISTB2
Standby Current
(*fS=RTC OSC)
3V No load, system HALT,
LCD On at HALT, C type,
UART Off
¾2.5 5.0 mA
5V ¾10 20 mA
ISTB3
Standby Current
(*fS=WDT OSC)
3V No load, system HALT
LCD On at HALT, C type,
UART Off
¾25 mA
5V ¾610
mA
ISTB4
Standby Current
(*fS=RTC OSC)
3V No load, system HALT,
LCD On at HALT, R type,
1/2 bias, UART Off
¾17 30 mA
5V ¾34 60 mA
ISTB5
Standby Current
(*fS=RTC OSC)
3V No load, system HALT,
LCD On at HALT, R type,
1/3 bias, UART Off
¾13 25 mA
5V ¾26 50 mA
ISTB6
Standby Current
(*fS=WDT OSC)
3V No load, system HALT,
LCD On at HALT, R type,
1/2 bias, UART Off
¾14 25 mA
5V ¾28 50 mA
ISTB7
Standby Current
(*fS=WDT OSC)
3V No load, system HALT,
LCD On at HALT, R type,
1/3 bias, UART Off
¾10 20 mA
5V ¾20 40 mA
HT49RU80/HT49CU80
Rev. 1.10 5 March 2, 2007

Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
VIL1
Input Low Voltage for I/O Ports,
TMR0, TMR1, TMR2, INT0 and
INT1
¾¾ 0¾0.3VDD V
VIH1
Input High Voltage for I/O Ports,
TMR0, TMR1, TMR2, INT0 and
INT1
¾¾
0.7VDD ¾VDD V
VIL2 Input Low Voltage (RES) ¾¾ 0¾0.4VDD V
VIH2 Input High Voltage (RES) ¾¾
0.9VDD ¾VDD V
IOL1 I/O Port Sink Current
3V VOL=0.1VDD
612
¾mA
5V 10 25 ¾mA
IOH1 I/O Port Source Current
3V VOH=0.9VDD
-2-4 ¾mA
5V -5-8¾mA
IOL2 LCD Common and Segment
Current
3V VOL=0.1VA
210 420 ¾mA
5V 350 700 ¾mA
IOH2 LCD Common and Segment
Current
3V VOH=0.9VA
-80 -160 ¾mA
5V -180 -360 ¾mA
RPH Pull-high Resistance
3V ¾20 60 100 kW
5V 10 30 50 kW
VLVR Low Voltage Reset Voltage ¾¾ 2.7 3.0 3.3 V
VLVD Low Voltage Detector Voltage ¾¾ 3.0 3.3 3.6 V
Note: ²*²for the value of VA refer to the LCD driver section.
²*fS²please refer to the WDT clock option
A.C. Characteristics Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
fSYS1 System Clock
(Crystal OSC, RC OSC)
¾2.2V~5.5V 400 ¾4000 kHz
¾3.3V~5.5V 400 ¾8000 kHz
fSYS2 System Clock
(32768Hz Crystal OSC) ¾¾ ¾
32768 ¾Hz
fRTCOSC RTC Frequency ¾¾ ¾
32768 ¾Hz
fTIMER Timer I/P Frequency
(50% duty)
¾2.2V~5.5V 0 ¾4000 kHz
¾3.3V~5.5V 0 ¾8000 kHz
tWDTOSC Watchdog Oscillator Period
3V ¾45 90 180 ms
5V ¾32 65 130 ms
tRES External Reset Low Pulse Width ¾¾ 1¾¾ms
tSST System Start-up Timer Period ¾Wake-up from HALT ¾1024 ¾*tSYS
tLVR Low Voltage Width to Reset ¾¾0.25 1 2 ms
tINT Interrupt Pulse Width ¾¾ 1¾¾ms
Note: *tSYS= 1/fSYS1 or 1/fSYS2
HT49RU80/HT49CU80
Rev. 1.10 6 March 2, 2007

HT49RU80/HT49CU80
Rev. 1.10 7 March 2, 2007
Functional Description
Execution Flow
The system clock is derived from either a crystal or an
RC oscillator or a 32768Hz crystal oscillator. It is inter-
nally divided into four non-overlapping clocks. One in-
struction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
The pipelining scheme makes it possible for each in-
struction to be effectively executed in a cycle. If an in-
struction changes the value of the program counter, two
cycles are required to complete the instruction.
Program Counter -PC
The program counter (PC) is 14 bits wide and controls
the sequence in which the instructions stored in the pro-
gram ROM are executed. The contents of the PC can
specify a maximum of 16384 addresses.
After accessing a program memory word to fetch an in-
struction code, the value of the PC is incremented by
²1². The PC then points to the memory word containing
the next instruction code.
When executing a jump instruction, a conditional skip
execution, loading a PCL register, a subroutine call, an
initial reset, an internal interrupt, an external interrupt, or
returning from a subroutine, the PC manages the pro-
gram transfer by loading the address corresponding to
each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; oth-
erwise the program proceeds to the next instruction.
T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4
F e t c h I S T ( P C )
E x e c u t e I S T ( P C - 1 ) F e t c h I S T ( P C + 1 )
E x e c u t e I S T ( P C ) F e t c h I S T ( P C + 2 )
E x e c u t e I S T ( P C + 1 )
P C P C + 1 P C + 2
S y s t e m C l o c k
O S C 2 ( R C o n l y )
P C
Execution Flow
Mode Program Counter
*13 *12~*8 *7 *6 *5 *4 *3 *2 *1 *0
Initial Reset 0 00000 00000000
External Interrupt 0 0 00000 00000100
External Interrupt 1 0 00000 00001000
Timer/Event Counter 0 Overflow 0 00000 00001100
Timer/Event Counter 1 Overflow 0 00000 00010000
UART Interrupt 0 00000 00010100
Multi Function Interrupt 0 00000 00011000
Skip Program Counter + 2 (within the current bank)
Loading PCL *13 *12~*8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch BP.5 #12~#8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine S13 S12~S8 S7 S6 S5 S4 S3 S2 S1 S0
Program Counter
Note: *13~*0: Program counter bits S13~S0: Stack register bits
#12~#0: Instruction code bits @7~@0: PCL bits
1 3 1 2 8 7 0
P r o g r a m C o u n t e r
B P
. 5
B a n k P o i n t e r ( B P )
B P
. 6
B P
. 7

HT49RU80/HT49CU80
Rev. 1.10 8 March 2, 2007
The lower byte of the PC, known as PCL, is a readable
and writeable register. Moving data into the PCL performs
a short jump. The destination is within 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
Program Memory -ROM
The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organised into
8192´16´2 banks which are addressed by the program
counter and table pointer.
The BP register bits5~bits7 are used to select the Pro-
gram Memory bank. When BP.7~BP.5 = 000B, Program
Memory bank 0 is selected and ranges from 0000H to
1FFFH. When BP.7~BP.5 = 001B, Program Memory
bank 1 is selected which ranges from 2000H to 3FFFH.
The CALL and JMP instruction provide for a full 13 bits
of addressing to allow branching anywhere within the 8K
program memory bank. When executing a CALL or JMP
instruction, the highest bit of the address is provided by
BP.5. When executing a CALL or JMP instruction, the
bank select bit must be correctly programmed to ensure
that the desired program memory bank is addressed. If
a return from a CALL instruction or an interrupt is exe-
cuted, the entire 14-bit program counter is popped off
the stack.
Certain locations in the ROM are reserved for special
usage:
·Location 000H
Location 000H is reserved for program initialisation.
After a chip reset, the program always begins execu-
tion at this location.
·Location 004H
Location 004H is reserved for the external interrupt
service program. If the INT0 input pin is activated, and
the interrupt is enabled, and the stack is not full, the
program will jump to this location and begin execution.
·Location 008H
Location 008H is reserved for the external interrupt
service program also. If the INT1 input pin is activated,
and the interrupt is enabled, and the stack is not full,
the program will jump to this location and begin
execution.
·Location 00CH
Location 00CH is reserved for the Timer/Event Coun-
ter 0 interrupt service program. If a timer interrupt re-
sults from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the pro-
gram will jump to this location and begin execution.
·Location 010H
Location 010H is reserved for the Timer/Event Coun-
ter 1 interrupt service program. If a timer interrupt re-
sults from a Timer/Event Counter 1 overflow, and if the
interrupt is enabled and the stack is not full, the pro-
gram will jump to this location and begin execution.
·Location 014H
This location is reserved for the UART interrupt ser-
vice program. If a UART interrupt results from a UART
TX or RX, and the interrupt is enabled and the stack is
not full, the program will jump to this location and be-
gin execution.
·Location 018H
This location is reserved for the multi function interrupt
service program. If a multi function interrupt results
from a Timer/Event Counter 2 overflow, a time base
interrupt occurs, or an RTC counter overflow, and the
related interrupts are enabled and the multi function
interrupt is enabled and the stack is not full, the pro-
gram will jump to this location and begin execution.
D e v i c e i n i t i a l i z a t i o n p r o g r a m
E x t e r n a l i n t e r r u p t 0 s u b r o u t i n e
T i m e r / e v e n t c o u n t e r 0 i n t e r r u p t s u b r o u t i n e
P r o g r a m R O M
B a n k 0
E x t e r n a l i n t e r r u p t 1 s u b r o u t i n e
U A R T I n t e r r u p t S u b r o u t i n e
M u l t i F u n c t i o n I n t e r r u p t S u b r o u t i n e
T i m e r / e v e n t c o u n t e r 1 i n t e r r u p t s u b r o u t i n e
3 F F F H
0 0 0 H
0 0 4 H
0 0 8 H
0 1 4 H
0 1 8 H
0 0 C H
0 1 0 H
1 F F F H
1 6 b i t s
o t e : n r a n g e s f r o m 0 t o 1 F
P r o g r a m R O M
B a n k 1
Look-up table (256 w ords)
Look-up table (256 w ords)
1F00H
n00H
n F F H
Look-up table (256 w ords)
3F00H
Program Memory
Instruction(s) Table Location
*13~*8 *7 *6 *5 *4 *3 *2 *1 *0
TABRDC [m] TBHP @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 111111 @7 @6 @5 @4 @3 @2 @1 @0
Table Location
Note: *13~*0: Table location bits TBHP: Table pointer higher-order bits
@7~@0: Bits of TBLP

HT49RU80/HT49CU80
Rev. 1.10 9 March 2, 2007
·Table location
Any location in the program memory can be used as
look-up tables. The instructions ²TABRDC [m]²(page
specified by TBHP and TBLP) and ²TABRDL [m]²(the
last page) transfer the contents of the lower-order byte
to the specified data memory, and the higher-order
byte to TBLH (08H). The higher-order byte table
pointer TBHP (1FH) and lower-order byte table
pointer TBLP (07H) are read/write registers, which in-
dicate the table locations. Before accessing the table
data, the location has to be placed in the TBHP and
TBLP. The TBLH register is read only and cannot be
restored. If the main routine and the interrupt service
routine both employ the table read instruction, the
contents of the TBLH register in the main routine are
likely to be changed by the table read instruction used
in the interrupt service routine. If this happens errors
can occur. Therefore, using the table read instruction
in the main routine and in the interrupt service routine
simultaneously should be avoided. However, if the ta-
ble read instruction has to be used in both the main
routine and in the interrupt service routine the interrupt
should be disabled prior to executing the table read in-
struction. It should not be re-enabled until TBLH in the
main routine has been backed up. All table related in-
structions require 2 cycles to execute.
Stack Register -STACK
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organised into 16 levels and is neither part of the data
memory nor part of the program memory, and is neither
readable nor writeable. Its activated level is indexed by
a stack pointer, known as SP, and is neither readable
nor writeable. At the start of a subroutine call or an inter-
rupt acknowledge, the contents of the program counter
are pushed onto the stack. At the end of the subroutine
or interrupt routine, indicated by a return instruction,
RET or RETI, the contents of the program counter are
restored to their previous value from the stack. After a
chip reset, the SP will point to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the ac-
knowledge is still inhibited. Once the Stack Pointer is
decremented, by RET or RETI, the interrupt is serviced.
This feature prevents stack overflow, allowing the pro-
grammer to use the structure easily. Likewise, if the
stack is full, and a ²CALL²is subsequently executed, a
stack overflow occurs and the first entry is lost. Only the
most recent 16 return addresses are stored.
Data Memory -RAM
Not including the LCD memory, the data memory, has a
total capacity of 608´8 bits, and is divided into two func-
tional groups, namely, the special function registers and
the general purpose data memory most of which are
readable/ writeable, although some are read only. The
General Purpose Data Memory is subdivided into three
banks, Banks 0, 2 and 3 each of which has a capacity of
192 ´8bits. The bank pointer, BP, selects which bank is
to be used, however care should be exercised when
manipulating the bank pointer as it is also used to select
the Program Memory bank.
BP RAM Bank
00000 0
00001 1
00010 2
00011 3
The general purpose data memory, addressed from 40H
to FFH (bank0, 2, 3), is used for data and control infor-
mation under instruction commands.
The RAM areas can directly handle arithmetic, logic, in-
crement, decrement, and rotate operations. Except for
some dedicated bits, each bit in the RAM can be set and
reset by the bit manipulation instructions ²SET [m].i²
and ²CLR [m].i². They are also indirectly accessible
through Memory pointer register 0, MP0, or Memory
pointer register 1, MP1.
There is also a special part of memory for the LCD mem-
ory. Bits in this special part memory are mapped to the
LCD pixel one by one. This LCD memory is located in
data memory bank 1.
Indirect Addressing Registers
Locations 00H and 02H are indirect addressing regis-
ters that are not physically implemented. Any read/write
operation of [00H] and [02H] accesses the data memory
pointed to by MP0 and MP1, respectively. Reading lo-
cations 00H or 02H indirectly returns the result 00H.
Writing to it indirectly leads to no operation.
The direct transfer of data between two indirect ad-
dressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 8-bit registers used to
access the data memory by combining the correspond-
ing indirect addressing registers. MP0 can only be ap-
plied to memory located at bank 0, while MP1 can be
applied to data memory from bank 0, bank 2 and bank 3
as well as the LCD display memory which is located in
bank 1.
Accumulator -ACC
The accumulator, ACC, is related to ALU operations. It
is also mapped to location 05H in the data memory and
is capable of operating with immediate data. Any data
transfers between two data memory locations must
pass through the ACC.

HT49RU80/HT49CU80
Rev. 1.10 10 March 2, 2007
Arithmetic and Logic Unit -ALU
This circuit performs 8-bit arithmetic and logic opera-
tions and provides the following functions:
·Arithmetic operations - ADD, ADC, SUB, SBC, DAA
·Logical operations - AND, OR, XOR, CPL
·Rotations - RL, RR, RLC, RRC
·Increment and Decrement - INC, DEC
·Branch decisions - SZ, SNZ, SIZ, SDZ etc.
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register -STATUS
The status register is 8 bits wide and contains, a carry
flag (C), an auxiliary carry flag (AC), a zero flag (Z), an
overflow flag (OV), a power down flag (PDF), and a
watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
Except for the TO and PDF flags, bits in the status reg-
ister can be altered by instructions similar to other reg-
isters. Data written into the status register does not alter
the TO or PDF flags. Operations related to the status
register, however, may yield different results from those
intended. The TO and PDF flags can only be changed
by a Watchdog Timer overflow, device power-on, or
clearing the Watchdog Timer and executing the ²HALT²
instruction. The Z, OV, AC, and C flags reflect the status
of the latest operations.
On entering the interrupt sequence or executing the sub-
routine call, the status register will not be automatically
pushed onto the stack. If the contents of the status is im-
portant, and if the subroutine is likely to corrupt the status
register, precautions should be taken to save it properly.
Interrupts
The device provides two external interrupts, three inter-
nal timer/event counters interrupts, an internal time
base interrupt, an internal real time clock interrupt, and
an UART TX/RX interrupt. The interrupt control register
0, INTC0, and interrupt control register 1, INTC1, both
contain the interrupt control bits that are used to set the
enable/disable status and to record the interrupt request
flags.
Once an interrupt subroutine is serviced, other interrupts
are all blocked, by clearing the EMI bit. This scheme may
prevent any further interrupt nesting. Other interrupt re-
quests may take place during this interval, but only the in-
terrupt request flag will be recorded. If a certain interrupt
requires servicing within the service routine, the EMI bit
and the corresponding bit in the INTC0 or of INTC1 regis-
ter may be set in order to allow interrupt nesting. Once
the stack is full, the interrupt request will not be acknowl-
edged, even if the related interrupt is enabled, until the
SP is decremented. If immediate service is desired, the
stack should be prevented from becoming full.
S p e c i a l P u r p o s e
D a t a M e m o r y
: U n u s e d .
R e a d a s " 0 "
I n d i r e c t A d d r e s s i n g R e g i s t e r 0
M P 0
I n d i r e c t A d d r e s s i n g R e g i s t e r 1
M P 1
B P
A C C
P C L
T B L P
T B L H
R T C C
S T A T U S
I T C 0
T M R 0
T M R 0 C
T M R 1 H
T M R 1 L
T M R 1 C
P A
P B
P C
P D
I T C 1
T B H P
T M R 2 H
T M R 2 L
T M R 2 C
M F I C
U S R
U S R
U C R 1
U C R 2
T X R / R X R
B R G
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2 A H
2 B H
2 C H
2 D H
G e n e r a l P u r p o s e
D a t a M e m o r y
( 1 9 2 x 2 B y t e s )
B a n k
F F H
G e n e r a l P u r p o s e
D a t a M e m o r y
( 1 9 2 x 3 B y t e s )
B a n k 0
G e n e r a l P u r p o s e
D a t a M e m o r y
( 1 9 2 x 2 B y t e s )
6 F H
40H
L C D D i s p l a y M e m o r y
B a n k 1
B a n k 2
3 F H
40H
RAM Mapping

HT49RU80/HT49CU80
Rev. 1.10 11 March 2, 2007
All interrupts provide a wake-up function. As an interrupt
is serviced, a control transfer occurs by pushing the con-
tents of the program counter onto the stack followed by
a branch to a subroutine at a specified program memory
location. Only the contents of the program counter is
pushed onto the stack. If the contents of the register or
of the status register is altered by the interrupt service
program which corrupts the desired control sequence,
the contents should be saved in advance.
External interrupts are triggered by a high to low transi-
tion on the INT0 or INT1 pins, which will result in their
their related interrupt request flags, EIF0 and EEF1, be-
ing set. After the interrupt is enabled, the stack is not full,
and a high to low transition occurs on the external inter-
rupt pins, a subroutine call to location 04H or 08H occurs.
When the interrupt service routine is serviced, the inter-
rupt request flags, EIF0 and EIF1, and the global enable
bit, EMI, are all cleared to disable other interrupts.
The internal Timer/Event Counter 0 interrupt is
initialised by setting the Timer/Event Counter 0 interrupt
request flag, T0F. This will occur when the timer over-
flows. After the interrupt is enabled, and the stack is not
full, and T0F bit is set, a subroutine call to location 0CH
occurs. The related interrupt request flag, T0F, is reset,
and the EMI bit is cleared to disable further interrupts.
The Timer/Event Counter 1 is operated in the same
manner but its related interrupt request flag is T1F, and
its subroutine call location is 10H.
The UART interrupt is initialised by setting the interrupt
request flag, URF, that is caused by a regular UART re-
ceive signal, caused by a UART transmit signal. After
the interrupt is enabled, the stack is not full, and the URF
bit is set, a subroutine call to location 14H occurs. The
related interrupt request flag, URF, is reset and the EMI
bit is cleared to disable further interrupts.
The multi function interrupt is initialised by setting the in-
terrupt request flag, MFF, that is caused by a regular
internal Timer/Event Counter 2 overflow, caused by a
time base signal or caused by a real time clock signal.
After the interrupt is enabled, the stack is not full, and
the MFF bit is set, a subroutine call to location 18H oc-
curs. The related interrupt request flag, MFF, is reset
and the EMI bit is cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are all held until a ²RETI²in-
struction is executed or the EMI bit and the related inter-
rupt control bit are both set to 1 (if the stack is not full). To
return from the interrupt subroutine a ²RET²or ²RETI²
may be executed. RETI sets the EMI bit and enables an
interrupt service, but RET does not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Interrupt Source Priority Vector
External interrupt 0 1 004H
External interrupt 1 2 008H
Timer/Event Counter 0 overflow 3 00CH
Timer/Event Counter 1 overflow 4 010H
UART interrupt 5 014H
Multi function interrupt
(Timer 2, Time base, RTC) 6 018H
It is recommended that a program should not use the
²CALL subroutine²within the interrupt subroutine. It¢sbe
-
cause interrupts often occur in an unpredictable manner
or require to be serviced immediately in some applica-
tions. During that period, if only one stack is left, and en-
abling the interrupt is not well controlled, operation of the
²call²in the interrupt subroutine may damage the origi-
nal control sequence.
Bit No. Label Function
0C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction, otherwise AC is cleared.
2 Z Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
3OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa, otherwise OV is cleared.
4 PDF PDF is cleared by either a system power-up or executing the ²CLR WDT²instruction. PDF is
set by executing the ²HALT²instruction.
5TO
TO is cleared by a system power-up or executing the ²CLR WDT²or ²HALT²instruction. TO is
set by a WDT time-out.
6, 7 ¾Unused bit, read as ²0²
STATUS (0AH) Register

HT49RU80/HT49CU80
Rev. 1.10 12 March 2, 2007
Bit No. Label Function
0 EMI Controls the master (global) interrupt (1=enable; 0=disable)
1 EEI0 Controls the external interrupt 0 (1=enable; 0=disable)
2 EEI1 Controls the external interrupt 1 (1=enable; 0=disable)
3 ET0I Controls the Timer/Event Counter 0 overflow interrupt (1=enable; 0=disable)
4 EIF0 External interrupt 0 request flag (1=active; 0=inactive)
5 EIF1 External interrupt 1 request flag (1=active; 0=inactive)
6 T0F Timer/Event Counter 0 overflow request flag (1=active; 0=inactive)
7¾Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No. Label Function
0 ET1I Controls the Timer/Event Counter 1 overflow interrupt (1=enable; 0=disable)
1 EURI Controls the UART TX or RX interrupt (1=enable; 0:disable)
2 EMFI Controls the multi-function interrupt (1=enable; 0:disable)
3, 7 ¾Unused bit, read as ²0²
4 T1F Timer/Event Counter 1 overflow request flag (1=active; 0=inactive)
5 URF UART TX or RX interrupt request flag (1=active; 0=inactive)
6 MFF Multi function interrupt request flag (1=active; 0=inactive)
INTC1 (1EH) Register
Bit No. Label Function
0 ET2I Controls the Timer/Event Counter 2 overflow interrupt (1=enable; 0=disable)
1 ETBI Controls the time base interrupt (1=enable; 0=disable)
2 ERTI Controls the real time clock interrupt (1=enable; 0=disable)
3, 7 ¾Unused bit, read as ²0²
4 T2F Timer/Event Counter 2 interrupt request flag (1=active; 0=inactive)
5 TBF Time base interrupt request flag (1=active; 0=inactive)
6 RTF Real time clock interrupt request flag (1=active; 0=inactive)
MFIC (23H) Register

HT49RU80/HT49CU80
Rev. 1.10 13 March 2, 2007
Oscillator Configuration
These devices contain three kinds of system clocks, an
RC oscillator, a crystal oscillator and a 32768Hz crystal
oscillator, the choice of which is determined by configu-
ration options. No matter what type of oscillator is se-
lected, the signal is used for the system clock. The
power down mode stops the system oscillator if it is an
RC or crystal oscillator type. The 32768Hz crystal sys-
tem oscillator will continue to run even if in the power
down mode. If the 32768Hz crystal oscillator is selected
as the system oscillator, the system oscillator will con-
tinue to run but fSYS and instruction execution will cease.
Since the system oscillator is also designed for timing
purposes, the internal timing such as that for the RTC,
the time base and WDT operation continues to run even
if the system enters the power down mode.
Of the three oscillators, if the RC oscillator is used, an
external resistor between OSC1 and VSS is required,
whose range should be from 24kWto 1MW. A frequency
equal to the system clock divided by 4, is available on
pin OSC2. This pin can be used for synchronisation pur-
poses but as it is an open drain output a pull-high resis-
tor should be connected. The RC oscillator provides the
most cost effective solution, but, the frequency of the os-
cillation may vary with VDD, temperature, and process
variations. It is therefore, not suitable for timing sensitive
operations where accurate oscillator frequencies are
desired.
If the crystal oscillator is selected, a crystal connected
between OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator. No
other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two ex-
ternal capacitors connected between OSC1/OSC2 and
ground are required.
A further oscillator circuit designed for the real time clock
also exists. This operates at a sole frequency of
32768Hz, for which a 32768Hz crystal should be con-
nected between pins OSC3 and OSC4.
The RTC oscillator circuit can be controlled to start up
quickly by clearing the ²QOSC²bit in the RTCC register.
After power on, as the RTC oscillator will be in the quick
start up mode, it is recommended that it be turned off af-
ter about 2 seconds to conserve power.
The WDT oscillator is a free running on-chip RC oscilla-
tor requiring no external components. Although when
the system enters the power down mode, the system
clock stops, the WDT oscillator will continue to run with a
period of approximately 65ms at 5V. The WDT oscillator
can be disabled by a configuration option to conserve
power.
Watchdog Timer -WDT
The WDT clock source is sourced from its own dedi-
cated RC oscillator (WDT oscillator), from the instruction
clock (system clock/4) or the real time clock oscillator
(RTC oscillator). The timer is designed to prevent a soft-
ware malfunction or sequence from jumping to an un-
known location with unpredictable results. The WDT can
be disabled by a configuration option. If the WDT is dis-
abled, all instruction executions relating to the WDT will
lead to no operation.
The WDT time-out period is fS/215~fS/216.
S y s t e m C l o c k / 4
D i v i d e r
W D T C l e a r
O p t i o n
S e l e c t
W D T
O S C
1 2 k H z
R T C
O S C
32768H z
C K T
R
C K T
R
f
S
T i m e - o u t R e s e t f
S
/ 2
1 5
~ f
S
/ 2
1 6
D i v i d e r
Watchdog Timer
C r y s t a l O s c i l l a t o r R C O s c i l l a t o r
O S C 1O S C 1
O S C 2 fS Y S / 4 O S C 2
V
D D
3 2 7 6 8 H z C r y s t a l /
R T C O s c i l l a t o r
V
D D
470pF
O S C 3
O S C 4
System Oscillator

HT49RU80/HT49CU80
Rev. 1.10 14 March 2, 2007
If the WDT clock source chooses the internal WDT oscil-
lator as its clock source, the time-out period may vary
with temperature, VDD, and process variations. If the
clock source is chosen to be the instruction clock, then
when the power down mode is entered, it must be noted
that the WDT will stop counting and lose its protective
function.
When the device operates in a noisy environment, using
the WDT oscillator is strongly recommended, since the
power down mode will stop the system clock.
The WDT overflow under normal operation initialises a
²chip reset²and sets the status bit ²TO². In the power
down mode, the overflow initialises a ²warm reset², and
only the program counter and SP are reset to zero. To
clear the WDT contents, there are three methods to be
adopted. These are an external reset (a low level on the
RES pin), a software instruction, and a ²HALT²instruction.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the sin-
gle ²CLR WDT²instruction while the second is to use
the two commands ²CLR WDT1²and ²CLR WDT2². For
the first option, a simple execution of ²CLR WDT²will
clear the WDT while for the second option, both ²CLR
WDT1²and ²CLR WDT2²must both be executed to
successfully clear the WDT. Note that for this second
option, if ²CLR WDT1²is used to clear the WDT, succes-
sive executions of this instruction will have no effect,
only the execution of a ²CLR WDT2²instruction will
clear the WDT. Similarly after the ²CLR WDT2²instruc-
tion has been executed, only a successive ²CLR WDT1²
instruction can clear the Watchdog Timer.
Multi-function Timer
These devices provide a multi-function timer for the
WDT, time base and RTC but with different time-out pe-
riods. The multi-function timer consists of an 8-stage di-
vider and a 7-bit prescaler, with the clock source coming
from the WDT OSC, the RTC OSC or the instruction
clock which is the system clock divided by 4. The
multi-function timer also provides a selectable fre-
quency signal, ranging from fS/22to fS/28, for the LCD
driver circuits, and a selectable frequency signal, ranging
from fS/22to fS/29, for the buzzer output selectable by
configuration options. To obtain a proper display, it is
recommended that a frequency as near as possible to
4kHz is selected for the LCD driver circuits.
Time Base
The time base offers a periodic time-out period to gener-
ate a regular internal interrupt. Its time-out period
ranges from /212 to fS/215 selected by a configuration op-
tion. If a time base time-out occurs, the related interrupt
request flag, TBF, will be set. If the interrupt is enabled,
and the stack is not full, a subroutine call to location 18H
will take place. The time base time-out signal can also
be applied as a clock source to Timer/Event Counter 1 in
order to get a longer time-out period.
Real Time Clock -RTC
The real time clock, abbreviated as RTC, is operated in
the same manner as the time base in that it is used to
supply a regular internal interrupt. Its time-out period
ranges from fS/28to fS/215 the actual value setup by soft-
ware programming . Writing data to the RT2, RT1 and
RT0 bits in the RTCC register provides various time-out
periods. If an RTC time-out occurs, the related interrupt
request flag, RTF, will be set. If the interrupt is enabled,
and the stack is not full, a subroutine call to location 18H
will take place. The real time clock time-out signal can
also be used as a clock source for Timer/Event Counter
0 in order to get longer time-out periods.
RT2 RT1 RT0 RTC Clock Divided Factor
000 2
8*
001 2
9*
010 2
10*
011 2
11*
100 2
12
101 2
13
110 2
14
111 2
15
Note: ²*²not recommended to be used
f s
D i v i d e r P r e s c a l e r
O p t i o n
L C D D r i v e r ( f S/ 2 2~ f S/ 2 8)
B u z z e r ( f S/ 2 2~ f S/ 2 9)
T i m e B a s e I n t e r r u p t
fS/ 2 1 2 ~ f S/ 2 1 5
O p t i o n
D i v i d e r
f
S
8 t o 1
M u x .
P r e s c a l e r
R T 2
R T 1
R T 0 R T C I n t e r r u p t
f
S
/ 2
8
~ f
S
/ 2
1 5
Real Time Clock

HT49RU80/HT49CU80
Rev. 1.10 15 March 2, 2007
Power Down Mode -HALT
The power down mode is initialised when a ²HALT²in-
struction is executed and results in the following.
·The system oscillator and fSYS turn off but the WDT or
RTC oscillator keeps running, if the WDT oscillator or
the real time clock is selected.
·The contents of the data memory and registers remain
unchanged.
·The WDT is cleared and starts recounting, if the WDT
clock source is sourced from the WDT oscillator or the
real time clock oscillator.
·All I/O ports maintain their original status.
·The PDF flag is set but the TO flag is cleared.
·The LCD driver keeps running, if the WDT OSC or
RTC OSC is selected.
The system will exit from power down mode by way of
an external reset, an interrupt, an external falling edge
signal on port A or a WDT overflow. An external reset
causes a device initialisation, while a WDT overflow per-
forms a ²warm reset². After examining the TO and PDF
flags, the reason for a chip reset can be determined. The
PDF flag is cleared by a system power-up or by executing
the ²CLR WDT²instruction, and is set by executing the
²HALT²instruction. However if the TO flag is set and a
WDT time-out occurs, the corresponding wake-up only
resets the program counter and the stack pointer, and
leaves the other registers in their original state.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each pin
on port A can be independently selected to wake up the
device using configuration options. Awakening from an
I/O port stimulus, the program resumes execution at the
next instruction. When awakening from an interrupt, two
sequences may occur. If the related interrupt is disabled
or the interrupt is enabled but the stack is full, the pro-
gram resumes execution at the next instruction. But if
the interrupt is enabled, and the stack is not full, the reg-
ular interrupt response takes place.
When an interrupt request flag is set before entering the
power down mode, the system cannot be awakened us-
ing that interrupt.
If a wake-up event occurs, it takes 1024 tSYS system
clock periods to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the wake-up results in
the next instruction execution, the execution will be per-
formed immediately after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the power down
mode.
Reset
There are three ways in which a reset may occur.
·RES is reset during normal operation
·RES is reset during HALT
·WDT time-out is reset during normal operation
The WDT time-out during a power down differs from
other chip reset conditions, as it will perform only a
²warm reset²that resets only the program counter and
SP and leaves the other circuits in their original state.
Some registers remain unaffected during other reset
conditions. Most registers are reset to their ²initial condi-
tion²once the reset conditions are met. By examining
the PDF and TO flags, the program can distinguish be-
tween different ²chip resets².
TO PDF RESET Conditions
0 0 RES reset during power-on
u u RES reset during normal operation
0 1 RES Wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT Wake-up HALT
Note: ²u²stands for unchanged
R E S
V
D D
1 0 0 k W
1 0 k W
0.1mF *
0 . 0 1 mF *
Reset Circuit
Note: ²*²Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.

HT49RU80/HT49CU80
Rev. 1.10 16 March 2, 2007
To guarantee that the system oscillator is running and
stabilised, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the sys-
tem awakes from the power down mode. After awaken-
ing from the power down mode, an SST delay is added.
An extra option load time delay is added during a reset
and power on.
The functional unit chip reset status is shown below.
Program Counter 000H
Interrupt Disabled
Prescaler Cleared
WDT Cleared. After master reset,
WDT starts counting
Timer/event Counter Off
Input/output Ports Input mode
Stack Pointer Points to the top of the stack
Timer/Event Counter
Three timer/event counters are implemented in the de-
vice, one 8-bit programmable count-up counter and two
16-bit programmable count-up counter.
The Timer/Event Counter 0 clock source may be
sourced from the system clock, the system clock/4, the
RTC time-out signal or from an external source. The
system clock source or the system clock/4 source is se-
lected by a configuration option.
The Timer/Event Counter 1 clock source may be
sourced from the TMR0 overflow, the system clock, the
time base time-out signal, the system clock/4 or an ex-
ternal source. The three former clock sources are se-
lected by configuration options. Using the external clock
input allows external events to be counted, time
intervals or pulse widths to be measured, or an accurate
time base to be generated. Using the internal clock al-
lows an accurate time base to be generated.
The Timer/Event Counter 2 contains a 16-bit program-
mable count-up counter whose clock may be sourced
from an external source or an internal clock source. The
internal clock source comes from fSYS/4. The external
clock input allows the user to count external events,
measure time intervals or pulse widths, or to generate
an accurate time base.
There are two registers related to the Timer/Event
Counter 0; TMR0 and TMR0C. Two physical registers
are mapped to the TMR0 location. Writing to TMR0
places the starting value in the Timer/Event Counter 0
register while reading TMR0 takes the contents of the
Timer/Event Counter 0. The TMR0C register is a
timer/event counter control register, which defines the
timer options.
There are three registers related to the Timer/Event
Counter 1; TMR1H, TMR1L and TMR1C. Writing to
TMR1L will only transfer the data into an internal
lower-order byte buffer (8-bit) and writing TMR1H will
transfer the specified data and the contents of the
lower-order byte buffer to TMR1H and TMR1L registers,
respectively. The Timer/Event Counter 1 preload regis-
ter is changed by each writing TRM1H operations.
Reading TMR1H will latch the contents of TMR1H and
TMR1L counters to the destination and the lower-order
byte buffer, respectively. Reading the TMR1L will read
the contents of the lower-order byte buffer. The TMR1C
is the Timer/Event Counter 1 control register, which de-
fines the operating mode, counting enable or disable
and an active edge.
There are three registers related to the Timer/Event
Counter 2; TMR2H (20H), TMR2L (21H), TMR2C (22H).
Writing TMR2L will only place the written data to an in-
ternal lower-order byte buffer (8-bit) and writing TMR2H
will transfer the specified data and the contents of the
lower-order byte buffer to TMR2H and TMR2L registers,
respectively. The Timer/Event Counter 2 preload regis-
ter is changed by each writing TRM2H operations.
Reading TMR2H will latch the contents of the TMR2H
and TMR2L counters to the destination and the
lower-order byte buffer, respectively. Reading the
TMR2L will read the contents of the lower-order byte
buffer. The TMR2C is the Timer/Event Counter 2 control
register, which defines the operating mode, counting en-
able or disable and an active edge.
The T0M0, T0M1 (TMR0C), T1M0, T1M1 (TMR1C) and
T2M0, T2M1 (TMR2C) bits define the operation mode.
The event count mode is used to count external events,
which means that the clock source is from an external
(TMR0/TMR1/TMR2) pin. The timer mode functions as
a normal timer with the clock source coming from the in-
R E S
V D D
S S T T i m e - o u t
C h i p R e s e t
tSST
Reset Timing Chart
W D T
H A L T
R e s e t
E x t e r n a l
R E S
C o l d
R e s e t
P o w e r - o n D e t e c t i o n
S S T
1 0 - b i t R i p p l e
C o u n t e r
fS Y S
W a r m R e s e t
Reset Configuration

HT49RU80/HT49CU80
Rev. 1.10 17 March 2, 2007
The register states are summarised below:
Register Reset
(Power On)
WDT Time-out
(Norma Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
BP 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Program Counter 0000H 0000H 0000H 0000H 0000H
TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
RTCC 0000 0111 0000 0111 0000 0111 0000 0111 00uu uuuu
STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu
INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu
TMR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMR0C 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u---
TMR1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMR1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMR1C 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u---
PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PB xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
PC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PD -111 1111 -111 1111 -111 1111 -111 1111 -uuu uuuu
INTC1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu
TBHP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TMR2H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMR2L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMR2C 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u---
MFIC -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu
USR 0000 1011 0000 1011 0000 1011 0000 1011 uuuu uuuu
UCR1 0000 00x0 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu
UCR2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
TXR/RXR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
BRG xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
Note: ²*²stands for warm reset
²u²stands for unchanged
²x²stands for unknown

HT49RU80/HT49CU80
Rev. 1.10 18 March 2, 2007
ternal selected clock source. Finally, the pulse width
measurement mode can be used to count the high or
low level duration of the external signal (TMR0/TMR1/
TMR2), and the counting is based on the internal se-
lected clock source.
In the event count or timer mode, the timer/event coun-
ter starts counting at the current contents in the
timer/event counter and ends at FFH (FFFFH). Once an
overflow occurs, the counter is reloaded from the
timer/event counter preload register, and generates an
interrupt request flag (T0F: bit 6 of the INTC0; T1F: bit 4
of the INTC1; T2F: bit 4 of the MFIC).
In the pulse width measurement mode with the values of
the T0ON/T1ON/T2ON and T0E/T1E/T2E bits equal to
²1², after the TMR0/TMR1/TMR2 has received a tran-
sient from low to high (or high to low if the T0E/T1E/T2E
bit is ²0²), it will start counting until the TMR0/TMR1/
TMR2) returns to the original level and resets the
T0ON/T1ON/T2ON. The measured result remains in
the timer/event counter even if the activated transient
occurs again. In other words, only 1-cycle measurement
can be made until the T0ON/T1ON/T2ON is set. The cy-
cle measurement will re-function as long as it receives
further transient pulse. In this operation mode, the
timer/event counter begins counting not according to
the logic level but to the transient edges. In the case of
counter overflows, the counter is reloaded from the
timer/event counter register and issues an interrupt re-
quest, as in the other two modes, i.e., event and timer
modes.
To enable the counting operation, the Timer ON bit
(T0ON/T1ON/T2ON; bit 4 of the TMR0C/TMR1C/
TMR2C) should be set to ²1². In the pulse width mea-
surement mode, the T0ON/T1ON/T2ON is automati-
cally cleared after the measurement cycle is completed.
But in the other two modes, the T0ON/T1ON/T2ON can
only be reset by instructions. The overflow of the
Timer/Event Counter 0/1 is one of the wake-up sources
and can also be applied to a PFD (Programmable Fre-
quency Divider) output at PA3 by options. Only one PFD
(PFD0 or PFD1) can be applied to PA3 by options. No
matter what the operation mode is, writinga0to
ET0I/ET1I/ET2I disables the related interrupt service.
When the PFD function is selected, executing ²CLR
[PA].3²instruction to enable PFD output and executing
²SET [PA].3²instruction to disable PFD output.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also re-
loads that data to the timer/event counter. But if the
timer/event counter is turned on, data written to the
timer/event counter is kept only in the timer/event coun-
ter preload register. The timer/event counter still contin-
ues its operation until an overflow occurs.
When the timer/event counter (reading TMR0/TMR1/
TMR2) is read, the clock is blocked to avoid errors, as
this may results in a counting error. Blocking of the clock
should be taken into account by the programmer.
It is strongly recommended to load a desired value into
the TMR0/TMR1/TMR2 register first, before turning on
the related timer/event counter, for proper operation
since the initial value of TMR0/TMR1/TMR2 is un-
known. Due to the timer/event counter scheme, the pro-
grammer should pay special attention on the instruction
to enable then disable the timer for the first time, when-
ever there is a need to use the timer/event counter func-
tion, to avoid unpredictable result. After this procedure,
the timer/event counter function can be operated nor-
mally. The following example is given, using one 8-bit
and one 16-bit width Timer (timer 0; timer 1) cascaded
into 24-bit width.
START:
mov a, 09h ; Set ET0I & EMI bits to
mov intc0, a ; enable Timer 0 and
; global interrupt
mov a, 01h ; Set ET1I bit to enable
mov intc1, a ; Timer 1 interrupt
mov a, 80h ; Set the operating mode as
mov tmr1c, a ; timer mode and select the mask
; option clock source
mov a, 0a0h ; Set the operating mode as timer
mov tmr0c, a ; mode and select the system
; clock/4
set tmr1c.4 ; Enable then disable Timer 1
clr tmr1c.4 ; for the first time
mov a, 00h ; Load a desired value into
mov tmr0, a ; the TMR0/TMR1 register
mov a, 00h ;
mov tmr1l, a ;
mov tmr1h, a ;
set tmr0c.4 ; Normal operating
set tmr1c.4 ;
END

HT49RU80/HT49CU80
Rev. 1.10 19 March 2, 2007
T 0 E
S y s t e m C l o c k
T 0 M 1
T 0 M 0
T M R 0
T 0 O
P u l s e W i d t h
M e a s u r e m e n t
M o d e C o n t r o l
T i m e r / E v e n t C o u n t e r 0
P r e l o a d R e g i s t e r
T i m e r / E v e n t
C c o u n t e r 0
D a t a B u s
R e l o a d
O v e r f l o w
t o I n t e r r u p t
O p t i o n M
U
X
T 0 S
S y s t e m C l o c k / 4
P F D 0
R T C O u t
fI T
T 0 M 1
T 0 M 0
Timer/Event Counter 0
T 1 E
S y s t e m C l o c k
T 1 M 1
T 1 M 0
T M R 1
T 1 M 1
T 1 M 0
T 1 O
P u l s e W i d t h
M e a s u r e m e n t
M o d e C o n t r o l
O p t i o n
S e l e c t
M
U
X
T 1 S
S y s t e m C l o c k / 4
T i m e B a s e O u t
T M R 0 O v e r f l o w
P F D 1
1 6 - B i t
P r e l o a d R e g i s t e r
D a t a B u s
R e l o a d
O v e r f l o w t o I n t e r r u p t
L o w B y t e
B u f f e r
H i g h B y t e L o w B y t e
1 6 - B i t T i m e r / E v e n t C o u n t e r
Timer/Event Counter 1
T 2 E
T 2 M 1
T 2 M 0
T M R 2
T 2 M 1
T 2 M 0
T 2 O
P u l s e W i d t h
M e a s u r e m e n t
M o d e C o n t r o l
S y s t e m C l o c k / 4
1 6 - B i t
P r e l o a d R e g i s t e r
D a t a B u s
R e l o a d
O v e r f l o w t o I n t e r r u p t
L o w B y t e
B u f f e r
H i g h B y t e L o w B y t e
1 6 - B i t T i m e r / E v e n t C o u n t e r
Timer/Event Counter 2
M
U
X
1 / 2 P F D
P F D S o u r c e O p t i o n
P A 3 D a t a C T R L
P F D 0
P F D 1
PFD Source Option

HT49RU80/HT49CU80
Rev. 1.10 20 March 2, 2007
Bit No. Label Function
0~2 ¾Unused bit, read as ²0²
3 T0E
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1= count on falling edge;
0= count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1= start counting on the rising edge, stop on the falling edge;
0= start counting on the falling edge, stop on the rising edge
4 T0ON Enables/disables the timer counting (0=disable; 1=enable)
5 T0S 2 to 1 multiplexer control inputs which selects the timer/event counter clock source
(0=RTC outputs; 1= system clock or system clock/4)
6
7
T0M0
T0M1
Defines the operating mode (T0M1, T0M0)
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TMR0C (0EH) Register
Bit No. Label Function
0~2 ¾Unused bit, read as ²0²
3 T1E
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1= count on falling edge;
0= count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1= start counting on the rising edge, stop on the falling edge;
0= start counting on the falling edge, stop on the rising edge
4 T1ON Enables/disables timer counting (0= disable; 1= enabled)
5 T1S 2 to 1 multiplexer control inputs to select the timer/event counter clock source
(0= option clock source; 1= system clock/4)
6
7
T1M0
T1M1
Defines the operating mode (T1M1, T1M0)
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TMR1C (11H) Register
Bit No. Label Function
0~2 ¾Unused bit, read as ²0²
3 T2E
Defines the TMR2 active edge of the timer/event counter:
In Event Counter Mode (T2M1,T2M0)=(0,1):
1= count on falling edge;
0= count on rising edge
In Pulse Width measurement mode (T2M1,T2M0)=(1,1):
1= start counting on the rising edge, stop on the falling edge;
0= start counting on the falling edge, stop on the rising edge
4 T2ON Enables/disables the timer counting (0=disable; 1=enable)
5¾Unused bit, read as ²0²
6
7
T2M0
T2M1
Defines the operating mode (T2M1, T2M0):
01=Event count mode (External clock)
10=Timer mode (Internal clock)
11=Pulse width measurement mode (External clock)
00=Unused
TMR2C (22H) Register