Honeywell H112 User manual

INHRFACE AND INSTALLATION
H112 Digital Controller
Honeyivell

Doc. No. 70130072243A
M-1165
H112 DIGITAL CONTROLLER
INTERFACE and INSTALLATION
Instruction Manual
October 1969
Honeyivell
COMPUTER CONTROL DIVISION

COPYRIGHT 1969, by Honeywell Inc., Computer Control
Division, Fiamingham, Massachusetts. Contents of this publication
may not be leproduced in any fonn in whole or in part, without per-
mission of the copyright owner. AU rights reserved.
Printed in U.S.A.
Published by the Publications Department,
Honeywell Inc., Computer Control Division

TABLE OF CONTENTS
SECTION I
INTRODUCTION
Page
Scope of Manual ]^_2
Applicable Documents 2_1
Description ij
General Interface Characteristics j_2
SECTION II
PROGRAMMED I/O TRANSFERS
I/O Instructions
OCP -Output Control Pulse 2-1
OTA -Output Transfer From Accumulator, If Ready 2-1
INA -Input Transfer to Accumulator, If Ready 2-1
SKS -Skip If Set 2-2
SMK -Set Interrupt Mask 2-2
STL -Stall On Line 2-2
I/O Bus Circuits 2_2
Programmed I/O Bus Signals 2-3
Data Bus (KDBOl- through KDB12-) 2-3
Address Bus Lines (KABOl- through KAB06-) 2-3
Instruction Lines (KOTAL-, KINAL-, KOCPL-, KSKSL-) 2-3
Set Mask (KSMKL-) 2-3
Strobe Signal (KSTRB-) 2-3
Interrupt Signal (KINTL-) 2-3
Load Signal (KLOAD-) 2-4
Test Line (KTSTL-) 2-4
Stall Line (KSTAL-) 2-4
Master Clear (KXCLR-) 2-4
Power Failure (KPWFL-) 2-4
Signal Timing -, .
Interfacing the Programmed I/O Bus 2-12
Logic Design to Complete Instructions 2-12
OCP -Output Control Pulse 212
OTA -Output Transfer from Accumulator 2-13
INA -Input Transfer to Accumulator 2-15
SKS -Skip if Set 2-16
SMK -Set Mask 2-16
STL -Stall Instruction 217
Interrupts
Interface Example for Programmed I/O Data Transfers 2-20

CONTENTS (Cont)
Page
SECTION III
LOAD MODE TRANSFERS 3-1
SECTION IV
DIRECT DATA CHANNEL OPTION
Signals 4-1
DDC Interface 4-1
DDC Signals 4-5
DDC Subchannel -Example 14-6
DDC Subchannel -Example 24-9
SECTION V
MACHINE CONTROL INTERFACE
Signals 5-1
MASTER CLEAR (XCLR) 5-1
STOP/RUN (XXSS) 5-1
LOAD (XLDSW) 5-1
START LINES (XSRT-, XXSRT+, XXGND-) 5-2
RUN INDICATOR (TRUN-X) 5-2
SECTION VI
INTERFACE UNIT CONSTRUCTION
Circuits 6-1
Packaging 6-1
Power Supply 6-2
Specifications 6-3
Coding (Location Information) 6-4
Cables 6-4
Configuration 6-4
Rack Dimensions 6-6
SECTION VII
INSTALLATION
v_yOntr Oi.xer dimensions 7-1
Mounting 7-1
Weight 7-1
Environment 7-1
Powex' 7- i
Portable Control Panel 7-2
APPENDIX A
SPECIAL [1- PACS A-1

Figure
2.-1
2-2
2.-3
2.-4
2.-5
2--6
2--7
2.-8
2--9
2- 10
2--11
2- 12
2-13
2- 14
2-15
2-•16
2-17
2- 18
3-•1
3- 2
4- 1
4- 2
4- 3
4- 4
4- 5
5- 1
6- 1
6- 2
APPENDIX B
DEVICE ADDRESS AND SMK BITS ASSIGNMENT B- 1
APPENDIX C
HI 12 INSTALLATION AND ACCESSORIES DRAWING C-1
APPENDIX D
HI 12 AC POWER WIRING D-
1
ILLUSTRATIONS
Page
OCP Timing 2-6
OTA Timing 2-7
INA Timing 2-8
SKS Timing 2-9
SMK Timing 2-10
I/O Bus Cable Routing, PAC View 2-11
OCP Gating 2-13
OTA Gating with Skip Criteria 2-13
Data Gating on OTA Command 2-14
Typical Methods of Gating Data on OTA Commands 2-14
INA Gating 2-15
Data Gating to Data Bus on INA Commands 2-16
SKS Gating 2-16
SMKl Using Bit 5to Control Mask Flip-Flop 2-17
STL Gating 2-17
SMK Logic 2-19
Gating with Mask Flip-Flop 2-20
Programmed I/O Interface with an External Device 2-23
Timing for Load Mode 3_3
Typical Load Mode Interface from Paper Tape Reader 3-4
DDC Interfacing 4_2
Direct Data Channel Timing (Composite) 4-3
Example 1of aDDC Subchannel 4_7
Core Map and Address Word 4_9
Example 2of aDDC Subchannel 4-10
Typical Remote Control Panel Wiring 5_3
System Coding Diagram £,_5
Controller Configuration £,_6

TABLES
Table Page
2-1 Programmed I/O Bus Signals 2-5
3-1 Signal Functions 3-2
4-1 DDC Bus Signals 4-4
5-1 Machine Control Interface Signals 6-2
6-1 Current Computation 6-2

SECTION I
INTRODUCTION
SCOPE OF MANUAL
This manual describes the characteristics of the various interfaces between the
Honeywell HI 12 Controller and customer-designed external equipment. Afunctional
description is given for each method of HI 12 input/output with individual requirements
specified. Also defined are control lines, timing requirements, and interface drive and
load requirements.
APPLICABLE DOCUMENTS
Title Doc. No.
HI 12 Programmers Reference Manual 70130072242
H112 Central Processor Description 70130072244
DESCRIPTION
The Honeywell H112 Controller has four types of input/output: Programmed l/O; Load
Mode Transfers; Machine Control Interface; and optionally available Direct Data Channel.
The standard programmed input/output structure in the HI 12 is asingle cable, duplex,
"party line" system. Six l/O instructions, plus reassignable, programmed priority inter-
rupts, make the controller's parallel transfer l/O bus capable of awide variety of applications.
Programmed l/o data transfers take place under software control. The priority inter-
rupt line may be utilized during these transfers to identify device ready status; or alternately,
device ready status may be determined by repeated testing either by an SKS command or by
the skip test incorporated into the data transfer instructions. Twelve bit parallel transfers
are made to and from the accumulator via the programmed I/O bus.
Load Mode Transfers also occur over the l/O bus but are entirely under the control of
the HI 12 hardware. The direction of load mode transfers is always into the controller.
The Machine Control Interface makes available certain functions (run, stop, load,
clear, start, and single instruction execution) to the system, whether or not the control panel
is present. This feature allows the HI 12 to operate without the control panel. Using the
plug-in panel feature reduces unit cost and prevents unauthorized personnel from interfering
with HI 12 operation.
The Direct Data Channel option provides an l/O path for high-speed data transfers
between the controller and l/O devices. Transfers between the channel located in the
controller and subchannels located in the peripheral devices utilize both the programmed
1-1

I/O bus and the DDC bus. All transfers are under subchannel control; however, atransfer
may be initiated by acommand from the program to the peripheral device over the I/O bus.
The address of the memory location to be transferred as well as the direction and time of
transfer are under subchannel control. This option gives the HI 12 adirect memory transfer
capability.
GENERAL INTERFACE CHARACTERISTICS
The input/output characteristics of the HI 12 have been carefully tailored to provide
maximum interface flexibility, with the widest possible interface tolerances. l/O signals
are true in the ground states and relatively immune to noise. Timing requirements give
adequate time for adevice to respond; and wide strobe pulses eliminate capacitive losses.
All l/O instructions have the same length, making timing consistent for programmed
l/O transfers. Also, included as part of the standard instruction complement, is the stall
instruction for convenient synchronization (with very low latency time) to external devices.
1-2

SECTION n
PROGRAMMED l/O TRANSFERS
This section is divided into the following parts.
a. Input/Output Instructions
b. Input/Output Circuits
c. Programmed l/O Bus Signals
d. Signal Timing
e. List of Signals, Mnemonics, and Pin Nunnbers
f.Interfacing the Programmed l/O Bus
g. Interrupts with Recommended Gating
h. Example of a Programmed l/O Interface
I/O INSTRUCTIONS
The following list of instructions are used to communicate between the program and
the external system. Part of the hardware to execute these instructions is in the mainframe.
This hardware causes the various signals to be propagated on the l/O bus. The remaining
hardware to execute the instructions is in the interface unit. This hardware receives and
transmits data and answers interrogations with the proper pulses. See Appendix Bfor
device address and mask bit assignments.
OCP -Output Control Pulse
This instruction is used by the program to command an action; e. g. ,start the reader,
reset the clock, etc. The 6-bit address field of this instruction specifies the action and device.
OTA -Output Transfer From Accumulator, If Ready
This instruction first deternnines whether the interface is ready for an output data
transfer. If the interface is ready, a12-bit parallel transfer from the accunaulator to the
interface takes place and the next sequential instruction is skipped. If the interface is not
ready, the transfer does not take place and the next sequential instruction is executed.
The 6-bit address field of the instruction specifies the recipient of the data.
INA -Input Transfer to Accumulator, If Ready
As in the OTA, this instruction first determines whether the interface specified by the
instruction's address field is ready to transfer data to the mainframe. If ready, the accumu-
lator is cleared and 12 bits (or less) of data is transferred to the accumulator in parallel.
If the interface is not ready, the accumulator is cleared, but the transfer does not take
place.
2-1

SKS -Skip If Set
This instruction is used to test a condition, line, or flip-flop in the interface. The
6-bit address field of the instruction specifies the condition to be tested. The program is
informed of the status of the condition by having the next sequential instruction following
the SKS skipped or not skipped depending on the status.
SMK -Set Interrupt Mask
This instruction is used to set and reset mask flip-flops in the various interfaces. An
interface is allowed to generate an interrupt only if its mask bit is set and is prohibited
from interrupting if its mask bit is reset. Each interface is assigned one bit of the
accumulator which is copied into its mask bit upon execution of the appropriate SMK
instruction. There are two SMK instructions, differentiated by one bit in the address field.
Thus, there can be up to 24 mask flip-flops.
STL -Stall On Line
This instruction is used to synchronize the controller with the external systemi.
When the STL instruction is executed, the controller will stall or wait until the appropriate
line in the bus is made true. The program will then continue from the instruction immedi-
ately follovring the STL. By feeding an external clock or other synchronization signal into
the bus the controller can be slaved to the external source.
l/O BUS CIRCUITS
All signals into and out of the controller are considered active or true when at
ground and passive or false when at +6 volts. All levels are [jl-PAC (0 to +6 volts) levels.
The controller will drive on output lines 16 receiver loads consisting of astandard
|JL-PAC gate input in parallel with a6800-ohm resistor to +6 volts, and adiode with anode
to ground. Each input line to the controller appears as one receiver load; however,
peripheral devices load the input lines in parallel. Thus, each line may appear as up to
17 loads to aparticular device including the device's own load and the controller's input
load.
The I/O bus timings are guaranteed only when driven and received with circuits such
as the CS-517 driver/receiver PAC (see Appendix), Astandard cable whose total length is
less than 25 feet must be between the controller and all interfaces.
Signal edges are guaranteed to fall within the specified time, but they may cross the
gate threshold more than once in that period. It is arecommended practice, therefore, to
design for this contingency.
The standard devices are designed such that each interface loads each line by no more
than one load and drives each line with no more than one driver.
2-2

PROGRAMMED I/O BUS SIGNALS
Data Bus (KDBOl- through KDB12- )
Signals KDBOl- through KDB12- from the controller represent the contents of the ac-
cumulator (A-register) during OOP, SMK, and OTA commands. During INA commands the
addressed peripheral device places data on this bus for eventual gating into the accumulator.
The interface must leave these lines at +6 volts until adata transfer to the controller is nnade
in response to an INA. Thus these signals are bidirectional, being outputs during OTA's,
SMK's and OOP's and inputs during INA commands. Aline will be at ground when the cor-
respondingly numbered bit in the accumulator is set and +6V when reset. To transfer aONE
into the accumulator in particular bit position during an INA command, the corresponding
line must be grounded.
Address Bus Lines (KABOl- through KAB06-)
The six output signals KABOl- through KAB06- are the least significant bits of the W-
register and carry the address portion of the I/O instruction. KABOl- corresponds to instruc-
tion bit 1and KAB06- to bit 6.
Instruction Lines (KOTAL-, KINAL-. KOCPL-, KSKSL- )
An output on one of the lines KOTAL-, KINAL-, KOCPL-, KSKSL- indicates that the
execution of an OTA, INA, OOP, or SKS, respectively is in progress. Execution of an SMK
causes the OCP line (KOCPL-) to pulse.
Set Mask (KSMKL- )
The output signal KSMKL- will be at ground during the execution of either an SMKO or
SMKl instruction. The peripheral device is to use this line with KAB01+ or KABOl- to deter-
mine which instruction is being executed and the appropriate data bus bit to set or reset the
mask flip-flop. (KABOl- is used for SMKO and KAB01+ is used for SMKl).
Strobe Signal (KSTRB- )
The output signal KSTRB- indicates that an active (ground) test signal has been recognized
during either an INA, OTA, or SKS instruction, that the next instruction will be skipped, and
that a data transfer, if any, will take place.
During OCP and OTA commands, this signal also serves to define the time when the
address and data lines are stable. During OTA, INA, and in some cases during SKS commands,
STROBE is used to reset aready flip-flop. This signal is also active, but redundant during
execution of an SMK.
Interrupt Signal (KINTL- )
KINTL- is an input signal to the controller. This line is made active (ground) to inter-
rupt the program, and held until the interrupt is recognized. The line is made +6 volts when
the controller resets the interrupt via separate programming action. This is usually accom-
plished via data transfer or OCP instruction.
2-3

Load Signal (KLOAD-)
KLOAD- is active (ground) when the load function is activated from either the external
machine control interface or the panel. It is an output from the controller and initiates load
mode input transfers.
Test Line (KTSTL-)
If aperipheral device is ready for adata transfer, it responds to address and instruc-
tion signals by making the KTSTL- input signal active (ground). This signal is used during an
INA or OTA instruction or if askip is to occur during an SKS instruction. This line serves no
function during OCP. The interface must leave the KTSTL- line at +6 volts until addressed.
Stall Line (KSTAL-)
KSTAL- must be made active (ground) with apulse which must be greater than 500 ns
long to guarantee restarting the controller after the execution of an STL instruction. If
KSTAL- is at ground during execution of the STL instruction, the machine does not stop.
This line is an input signal to the controller.
Master Clear (KXCLR- )
KXCLR- is active (ground) during the operation of the MASTER CLEAR pushbutton on
the panel, during the activation of the remote clear line, and during apower on or off
sequence. KXCLR- is an output signal from the controller.
Power Failure (KPWFL-)
An active (ground) level on the KPWFL- output line indicates that operation of the con-
troller will be terminated because of apower failure or power turn-off operation. After this
line becomes active, there is at least 1millisecond of program execution time remaining
before all processing will stop due to lack of power. This output signal is supplied only if the
power failure interrupt option is included in the machine.
SIGNAL TIMING
Figures 2-1 through 2-5 show the timing requirements for each command. Unless
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state.
Table 2-1 lists the mnemonics, functions, and pin assignments for the lines in the
l/O bus.
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machine.
2-4

Table 2-1,
Programmed l/O Bus Signals
Mnemonics
KDBOl-
KDB02-
KDB03-
KDB04-
KDB05-
KDB06-
KDB07-
KDB08-
KDB09-
KDBIO-
KDB 11-
KDB12-
Function
Data Bus Bit 1
Data Bus Bit 2
Data Bus Bit 3
Data Bus Bit 4
Data Bus Bit 5
Data Bus Bit 6
Data Bus Bit 7
Data Bus Bit 8
Data Bus Bit 9
Data Bus Bit 10
Data Bus Bit 11
Data Bus Bit 12
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
KABOl-
KAB02-
KAB03-
KAB04-
KAB05-
KAB06-
Address Bus Bit 1
Address Bus Bit 2
Address Bus Bit 3
Address Bus Bit 4
Address Bus Bit 5
Address Bus Bit 6
13
14
15
16
17
18
KOTAL-
KINAL-
KOCPL-
KSKSL-
KSMKL-
KSTRB-
KINTL-
KLOAD-
KTSTL-
KSTAL-
KXCLR-
KGND-
KPWFL-
OTA Instruction
INA Instruction
OCP Instruction
SKS Instruction
SMK Instruction
Strobe Signal
Interrupt Signed
Load Signal
Test Line
Stall Line
SPARE (Unas signed)
Master Clear
Ground
Power Failure
19
20
21
22
23
24
25
26
27
28
29
30
31
32
The l/O bus originates in mainframe slot C18. Figure 2-6 shows the mainframe
drawer configuration, available option area, and l/O cable routing.
2-5

TIME, ^SECONDS
DATA BUS KDBOI-THRU KDBI2-
ADDRESS BUS KABOI- THRU
KAB06 -
INSTRUCTION SIGNAL KOCPL-
STROBE SIGNAL KSTRB-
0.9
800 NS MIN
3. 9
4.0
4.0 4.8
2.3 2.9 3.1 3.7
A6242
Figxrre 2-1. OCP Timing

DATA BUS KDBOl-THRU KDBI2-
ADDRESS BUS KABOI- THRU KAB06-
INSTRUCTION SIGNAL KOTAL-
STROBE STROBE SIGNAL KSTRB-
TEST SIGNAL KTSTL-
A6250
TIME, /A SECONDS
23
I.I
0. 9
800 NS Ml N
39
4.0
'"i"i
4.8
IT
2.3 2.9 3.1 3.7
Figure 2-2. OTA Timing

TIME, uSECONDS
ADDRESS BUS KABOI-THRU
KAB06-
INSTRUCTION SIGNAL KINAL-
TEST SIGNAL KTSTL-
DATA BUS INPUT KDBOI-
THRU KDBI2-
STROBE SIGNAL KSTRB-
A62f62
0. 9
I.9
2. 3
4.0
5.2
52
2.3 2.9 3.1 3.7
800 NS MIN
Figure 2-3. INA Timing

TIME, ft SECONDS
ADDRESS BUS KABOI-
THRU KAB06-
INSTRUCTION SIGNAL
KSKSL-
TEST SIGNAL KTSTL-
STROBE SIGNAL
KSTRB —
0.9
800 NS MIN
1.9
4.0
4.0 4.8
2.3 29 3.1 3.7
5.2
A6245
Figure 2-4. SKS Timing
1

I
DATA BUS KDBOI-THRU
KDBI2-
ADDRESS BUS {KABOI±)
INSTRUCTION SIGNAL KSMKL-
A6258
II
TIME, /i SECONDS
23
800 NS MIN
39
4
2 3 2.9 3, I3.7
Figure 2-5. SMK Timing

NEXT DRAWER IF 4K
I/O BUS Q
(SLOT CIS)
POWER
SUPPLY
MAIN-
FRAME
NEXT DRAWER IF 8K
FIRST
OPTION
FRONT PANEL
4K
OPTION AREA
I/O BUS
CABLE
6431
RIBBON JUMPER
(ONLY IF 4K)
Figure 2-6. I/O Bus Cable Routing, PAC View
2-11