Honeywell H112 User manual

INHRFACE AND INSTALLATION
H112 Digital Controller
Honeyivell

Doc. No. 70130072243A
M-1165
H112 DIGITAL CONTROLLER
INTERFACE and INSTALLATION
Instruction Manual
October 1969
Honeyivell
COMPUTER CONTROL DIVISION

COPYRIGHT 1969, by Honeywell Inc., Computer Control
Division, Fiamingham, Massachusetts. Contents of this publication
may not be leproduced in any fonn in whole or in part, without per-
mission of the copyright owner. AU rights reserved.
Printed in U.S.A.
Published by the Publications Department,
Honeywell Inc., Computer Control Division

TABLE OF CONTENTS
SECTION I
INTRODUCTION
Page
Scope of Manual ]^_2
Applicable Documents 2_1
Description ij
General Interface Characteristics j_2
SECTION II
PROGRAMMED I/O TRANSFERS
I/O Instructions
OCP -Output Control Pulse 2-1
OTA -Output Transfer From Accumulator, If Ready 2-1
INA -Input Transfer to Accumulator, If Ready 2-1
SKS -Skip If Set 2-2
SMK -Set Interrupt Mask 2-2
STL -Stall On Line 2-2
I/O Bus Circuits 2_2
Programmed I/O Bus Signals 2-3
Data Bus (KDBOl- through KDB12-) 2-3
Address Bus Lines (KABOl- through KAB06-) 2-3
Instruction Lines (KOTAL-, KINAL-, KOCPL-, KSKSL-) 2-3
Set Mask (KSMKL-) 2-3
Strobe Signal (KSTRB-) 2-3
Interrupt Signal (KINTL-) 2-3
Load Signal (KLOAD-) 2-4
Test Line (KTSTL-) 2-4
Stall Line (KSTAL-) 2-4
Master Clear (KXCLR-) 2-4
Power Failure (KPWFL-) 2-4
Signal Timing -, .
Interfacing the Programmed I/O Bus 2-12
Logic Design to Complete Instructions 2-12
OCP -Output Control Pulse 212
OTA -Output Transfer from Accumulator 2-13
INA -Input Transfer to Accumulator 2-15
SKS -Skip if Set 2-16
SMK -Set Mask 2-16
STL -Stall Instruction 217
Interrupts
Interface Example for Programmed I/O Data Transfers 2-20

CONTENTS (Cont)
Page
SECTION III
LOAD MODE TRANSFERS 3-1
SECTION IV
DIRECT DATA CHANNEL OPTION
Signals 4-1
DDC Interface 4-1
DDC Signals 4-5
DDC Subchannel -Example 14-6
DDC Subchannel -Example 24-9
SECTION V
MACHINE CONTROL INTERFACE
Signals 5-1
MASTER CLEAR (XCLR) 5-1
STOP/RUN (XXSS) 5-1
LOAD (XLDSW) 5-1
START LINES (XSRT-, XXSRT+, XXGND-) 5-2
RUN INDICATOR (TRUN-X) 5-2
SECTION VI
INTERFACE UNIT CONSTRUCTION
Circuits 6-1
Packaging 6-1
Power Supply 6-2
Specifications 6-3
Coding (Location Information) 6-4
Cables 6-4
Configuration 6-4
Rack Dimensions 6-6
SECTION VII
INSTALLATION
v_yOntr Oi.xer dimensions 7-1
Mounting 7-1
Weight 7-1
Environment 7-1
Powex' 7- i
Portable Control Panel 7-2
APPENDIX A
SPECIAL [1- PACS A-1

Figure
2.-1
2-2
2.-3
2.-4
2.-5
2--6
2--7
2.-8
2--9
2- 10
2--11
2- 12
2-13
2- 14
2-15
2-•16
2-17
2- 18
3-•1
3- 2
4- 1
4- 2
4- 3
4- 4
4- 5
5- 1
6- 1
6- 2
APPENDIX B
DEVICE ADDRESS AND SMK BITS ASSIGNMENT B- 1
APPENDIX C
HI 12 INSTALLATION AND ACCESSORIES DRAWING C-1
APPENDIX D
HI 12 AC POWER WIRING D-
1
ILLUSTRATIONS
Page
OCP Timing 2-6
OTA Timing 2-7
INA Timing 2-8
SKS Timing 2-9
SMK Timing 2-10
I/O Bus Cable Routing, PAC View 2-11
OCP Gating 2-13
OTA Gating with Skip Criteria 2-13
Data Gating on OTA Command 2-14
Typical Methods of Gating Data on OTA Commands 2-14
INA Gating 2-15
Data Gating to Data Bus on INA Commands 2-16
SKS Gating 2-16
SMKl Using Bit 5to Control Mask Flip-Flop 2-17
STL Gating 2-17
SMK Logic 2-19
Gating with Mask Flip-Flop 2-20
Programmed I/O Interface with an External Device 2-23
Timing for Load Mode 3_3
Typical Load Mode Interface from Paper Tape Reader 3-4
DDC Interfacing 4_2
Direct Data Channel Timing (Composite) 4-3
Example 1of aDDC Subchannel 4_7
Core Map and Address Word 4_9
Example 2of aDDC Subchannel 4-10
Typical Remote Control Panel Wiring 5_3
System Coding Diagram £,_5
Controller Configuration £,_6

TABLES
Table Page
2-1 Programmed I/O Bus Signals 2-5
3-1 Signal Functions 3-2
4-1 DDC Bus Signals 4-4
5-1 Machine Control Interface Signals 6-2
6-1 Current Computation 6-2

SECTION I
INTRODUCTION
SCOPE OF MANUAL
This manual describes the characteristics of the various interfaces between the
Honeywell HI 12 Controller and customer-designed external equipment. Afunctional
description is given for each method of HI 12 input/output with individual requirements
specified. Also defined are control lines, timing requirements, and interface drive and
load requirements.
APPLICABLE DOCUMENTS
Title Doc. No.
HI 12 Programmers Reference Manual 70130072242
H112 Central Processor Description 70130072244
DESCRIPTION
The Honeywell H112 Controller has four types of input/output: Programmed l/O; Load
Mode Transfers; Machine Control Interface; and optionally available Direct Data Channel.
The standard programmed input/output structure in the HI 12 is asingle cable, duplex,
"party line" system. Six l/O instructions, plus reassignable, programmed priority inter-
rupts, make the controller's parallel transfer l/O bus capable of awide variety of applications.
Programmed l/o data transfers take place under software control. The priority inter-
rupt line may be utilized during these transfers to identify device ready status; or alternately,
device ready status may be determined by repeated testing either by an SKS command or by
the skip test incorporated into the data transfer instructions. Twelve bit parallel transfers
are made to and from the accumulator via the programmed I/O bus.
Load Mode Transfers also occur over the l/O bus but are entirely under the control of
the HI 12 hardware. The direction of load mode transfers is always into the controller.
The Machine Control Interface makes available certain functions (run, stop, load,
clear, start, and single instruction execution) to the system, whether or not the control panel
is present. This feature allows the HI 12 to operate without the control panel. Using the
plug-in panel feature reduces unit cost and prevents unauthorized personnel from interfering
with HI 12 operation.
The Direct Data Channel option provides an l/O path for high-speed data transfers
between the controller and l/O devices. Transfers between the channel located in the
controller and subchannels located in the peripheral devices utilize both the programmed
1-1

I/O bus and the DDC bus. All transfers are under subchannel control; however, atransfer
may be initiated by acommand from the program to the peripheral device over the I/O bus.
The address of the memory location to be transferred as well as the direction and time of
transfer are under subchannel control. This option gives the HI 12 adirect memory transfer
capability.
GENERAL INTERFACE CHARACTERISTICS
The input/output characteristics of the HI 12 have been carefully tailored to provide
maximum interface flexibility, with the widest possible interface tolerances. l/O signals
are true in the ground states and relatively immune to noise. Timing requirements give
adequate time for adevice to respond; and wide strobe pulses eliminate capacitive losses.
All l/O instructions have the same length, making timing consistent for programmed
l/O transfers. Also, included as part of the standard instruction complement, is the stall
instruction for convenient synchronization (with very low latency time) to external devices.
1-2

SECTION n
PROGRAMMED l/O TRANSFERS
This section is divided into the following parts.
a. Input/Output Instructions
b. Input/Output Circuits
c. Programmed l/O Bus Signals
d. Signal Timing
e. List of Signals, Mnemonics, and Pin Nunnbers
f.Interfacing the Programmed l/O Bus
g. Interrupts with Recommended Gating
h. Example of a Programmed l/O Interface
I/O INSTRUCTIONS
The following list of instructions are used to communicate between the program and
the external system. Part of the hardware to execute these instructions is in the mainframe.
This hardware causes the various signals to be propagated on the l/O bus. The remaining
hardware to execute the instructions is in the interface unit. This hardware receives and
transmits data and answers interrogations with the proper pulses. See Appendix Bfor
device address and mask bit assignments.
OCP -Output Control Pulse
This instruction is used by the program to command an action; e. g. ,start the reader,
reset the clock, etc. The 6-bit address field of this instruction specifies the action and device.
OTA -Output Transfer From Accumulator, If Ready
This instruction first deternnines whether the interface is ready for an output data
transfer. If the interface is ready, a12-bit parallel transfer from the accunaulator to the
interface takes place and the next sequential instruction is skipped. If the interface is not
ready, the transfer does not take place and the next sequential instruction is executed.
The 6-bit address field of the instruction specifies the recipient of the data.
INA -Input Transfer to Accumulator, If Ready
As in the OTA, this instruction first determines whether the interface specified by the
instruction's address field is ready to transfer data to the mainframe. If ready, the accumu-
lator is cleared and 12 bits (or less) of data is transferred to the accumulator in parallel.
If the interface is not ready, the accumulator is cleared, but the transfer does not take
place.
2-1