HP 13255 User manual

BP 13255
MEMORY CONTROLLER MODULE
Manual Part 10. 13255-912q9
1/.2S.;l
PRINTED
JUN-23-81
DATA TERMINAL
TECHNICAL INFORMATION
HEWLETT ifi PACKARD
Printed in U.S.A.

13255
Processor (8085A-2) Module 13255-91249/02
REV FEB-14-82
1.0 INTRODUCTION.
The processor (8085A-2) module functions as the .. in controlling unit
for the 2747F terminal. It also contains the hardware to intertace the
processor to the external keyboard. The processor retches instructions
trom memory and pertorms I/O operations on other .adul.s attached to
the terminal data bus (backplane ass.bly). !be 8085A-2 lIOdule has the
capability ot down loading code in a RAM based 2647F.
2.0 OPERATING PARAMETERS.
A summary of operating parameters tor the Processor (8085A-2) Module is
contained in tables 1.0 through 6.7
Table 1.0 Physical Parameter.
================================================================================
1 PART 1 Size (L x Wx D) Weight 1
I NUMBER 1 NOMENCLATURE 1 +/-0.100 Inche. 1 (Pounds) 1
/==============1==============================1======================1=========1
1 I 1 1 1
I 02640-60249 I PROCESSOR (8085A-2) I 12.5 x 4.0 x 0.5 1 0·5 1
1 I I 1 1
1 I I 1 1
1 I 1 1 1
1==============================================================================1
I 1
1 NUMBER OF BACKPLANE SLOTS REQUIRED: 1 I
1 I
================================================================================

HP 13255
MEMORY CONTROLLER MODULE
Manual Part 10. 13255-912q9
PRIM'l'ED
1/:IS-.;2
JUH-23-81
IOTlCE
The information contained in this document is subject to change
without notice.
HEWLETl'-PACKARD MAKES 10 WARRANTY OF AMY KIND WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT lOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Hewlett-Packard
shall not be liable for errors contained herein or tor incidental or
consequential damages in connection with the furnishing, performance,
or use of this material.
This document contains proprietary information which is protected by
copyright. All rights are reserved. No part of this document may be
photocopied or reproduced without the prior written consent of Hewlett-
Packard Company.
Copyright c 1982 by HEWLETT-PACKARD COMPANY
NOTE: This document is part of the 2647F DATA TERMINAL product
series Technical Information Package (HP 13255).

13255
Processor (8085A-2) Module
1.0 INTRODUCTION.
13255-91249/02
REV FEB-14-82
The processor (8085A-2) aodule functions as the .. in controllin, unit
for the 2747F terminal. It also contains the hardware to interface the
processor to the external keyboard. The processor f.tch •• in.truction.
trom memory and performs I/O operation. on other .odul.. attached to
the terllinal data bus (backplane ass.bly). 'l'b. 8085A-2 lIOdule has the
capability ot down loading code in a RAM based 2647F.
2.0 OPERATING PARAMETERS.
A summary of operating parameters tor the Proces.or (8085A-2) Modul. i.
contained in tables 1.0 through 6.7
Table 1.0 Physical Parameters
-===============================================================================
PART 1 I Size (L x Wx D) I Weisht
NUMBER 1 NOMENCLATURE 1 +/-0.100 Inches I (Pounds)
==============1==============================1======================1=========
1 1 I
02640-60249 I PROCESSOR (8085A-2) I 12.5 x 4.0 x 0.5 I 0.5
I I I
I I I
I 1 1
==============================================================================
NUMBER OF BACKPLANE SLOTS REQUIRED: 1
================================================================================

13255
13255-91252/03
Rev JUN-23-81
Memory Controller
Table 2.0 Reliability and Environmental Information
===============================================================================-
1
1
Environmental: ( X ) HP Class B () Other:
1
1
I Restrictions: Type tested at product level
,
1
1==============================================================================
1
1
Failure Rate: 4.774 (percent per 1000 hours)
,
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Table 3.0 Power Supply and Clock Requirements -Measured
(+/- 5% Unless Otherwise Specified)
--------------------------------------------------------------------------------
-------------------------------------- ----------------------------------------
+5 Volt Supply
+12 Volt Supply -12 Volt Supply -42 Volt Supply
@ 0.5 A
mA
NOT APPLICABLE NOT APPLICABLE NOT APPLICABLE
-------------------------------------- ---------------------------------------
-------------------------------------- ---------------------------------------
115 volts AC 220 volts AC
A A
NOT APPLICABLE NOT APPLICABLE
------------------------------------------------------------------------------
------------------------------------------------------------------------------
Clock Frequency:
4.915 MHz
================================================================================
Table 4.0 Jumper Definition
================================================================================
PCA Function I
I
Designation I I
1=============1================================================================1
1 I I
I 1 I
1 Wl 1 RAM/ROM Based Terminal (see section 3.8) I
I I ,
I I I
================================================================================

13255
Memory Controller
Table
5.0
Connector Information
13255-91252/04
Rev JUN-23-81
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Connector
I
Signal
Signal
and Pin No. I
Name Description
------------- -------------- -------------------------------------------------
------------- -------------- -------------------------------------------------
P1,
Pin 1
+5V
+5 Volt Power Supply
-2
GND Ground Common Return
(Power and Signal)
-3
SYSCLK
4.915 MHz
System Clock
-4
Not Used
-5
ADDRO
Negative True, Address Bit
0
-6 ADDR1
Negative True, Address
Bit
1
-1
ADDR2
Negative True, Address
Bit
2
-8
ADDR3
Negative True, Address Bit
3
-9
ADDR4
Negative True, Address Bit 4
-10
ADDR5
Negative
True,
Address Bit
5
-11
ADDR6
Negative
True,
Address Bit
6
-12
ADDR1
Negative True, Address Bit
1
-13
ADDRa
Negative True, Address Bit
8
-14
ADDR9
Negative True,
Address Bit
9
-15
ADDR10
Negative True,
Address Bit
10
-16 ADDR11
Negative True,
Address Bit
11
-11
ADDR12
Negative True, Address Bit 12
-18
ADDR13
Negative True,
Address Bit
13
-19
ADDR14
Negative True, Address Bit 14
-20
ADDR15
Negative True, Address Bit
15
-21 10
Negative
True, Input
Output/Memory
-22
GND
Ground Common Return
(Power and Signal)
==============-=================================================================

13255
Memory Controller
Table 5.0
Connector Information (cont)
13255-91252/05
Rev JUN-23-81
-----------------------------------------------.---------------------------------
----------------------------- --------------------------------------------------
Connector I
and Pin No.1
-------------
-------------
P1, Pin A
-B
-C
-D
-E
-F
-H
-J
-K
-L
-M
-N
-p
-R
-S
-T
-u
-v
-W
-x
-y
-z
Signal
Name
--------------
--------------
GND
PON
BUS 0
BUS 1
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7
WRITE
WAIT
ADDR16
ADDR17
ADDR18
REQ
Signal
Description
-------------------------------------------------
-------------------------------------------------
Ground Common Return (Power and Signal)
Not Used
Not Used
Positive True, System Power On
Negative True, Data Bus Bit 0
Negative True, Data Bus Bit 1
Negative True, Data Bus Bit 2
Negative True, Data Bus Bit 3
Negative True, Data Bus Bit 4
Negative True, Data Bus Bit 5
Negative True, Data Bus Bit 6
Negative True, Data Bus Bit 7
Negative True, Write/Read Type Cycle
Not Used
Negative True, Assert Wait State
Not Used
Not Used
Positive True, Address Bit 16
Positive True, Address Bit 17
Positive True, Address Bit 18
Negative True, Request (Bus Data Valid)
Not Used
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------

13255
Memory Controller
13255-91252/06
Rev JUN-23-81
3.0 FUNCTIONAL DESCRIPTION. Refer to the block diagram (figure 1),
schematic diagram (figure 2 and 3), the timing diagram (figure 4), and
the parts list (02640-60252).
The Memory Controller Module provides program and variable space for
the terminal. It consists of memory drivers and series termination
resistors, data port, memory array, address multiplexer, refresh
address generator, refresh timer, refresh cycle generator, bus
interface and board select circuitry, and a memory cycle generator.
3.1 SERIES TERMINATION RESISTORS
The series termination resistors m1n1m1ze undershoot by terminating the
bus lines with the line impedance. This approximates to 20 ohms since
it consists of an 80 ohm line with distributed, lumped, and capacitive
lo~ds. Current limit protection is provided free which limits the
driver output to 75 mA if two or more array inputs are shorted
together.
3.2 DATA PORT
3.2.1
3.2.2
The data port consists of a 74LS244 data in driver (U46) and a 74LS373
data out transparent latch. This port is enabled whenever BOARD SELECT
(U53-6) and REQ (P1-Y) are both low, causing U56-3 to go low. The
direction of data flow is arbitrated by WRITE (P1-P) in the following
manner: if WRITE is high, then U56-8 will be active, resulting in data
transmission from the Memory Controller to the data bus. If WRITE is
low, then U56-6 will be active, and the data flow will be from the bus
to the memory array. Data is latched in the output latch by the trail-
ing edge of CAS, the COllunn address strobe.
The transparent data latch (U27) allows data to propagate through the
latch prior to being latched. This means the RAM access time is
optimized and if a higher speed RAM is used, the memory will appear to
be correspondingly higher in speed. The data is latched so that
completion of the memory cycle does not depend on the completion of the
processor memory handshake.

13255
Memory Controller
13255-91252/07
REV JUN-23-81
3.3 MEMORY ARRAY
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
3.4.3
The memory array consists of up to thirty-two 64K RAMS.
socketed to allow field upgrade and repair.
The RAMs are
The power distribution is via a low impedance 4-layer PC board struc-
ture. The ceramic capacitors which supply the transient current are
organized such that some redundancy exists. This allows reliable oper-
ation with one open circuit component.
The
memory array is organized as four modules of equal size (if all are
loaded). The entire array is activated by the start of a memory cycle,
which is when U71-9 goes low. At that time, a row address strobe is
sent to all four banks. The column address s"i;robe passes through a
four to one decoder which determines which module is selected for read
or write.
ADDRESS MULTIPLEXER
The address multiplexer consists of two 74LS258 quad inverting 2 to 1
line tri-state multiplexers (U75,76) and a 74LS244 octal tri-state buf-
fer (U55).
The 74LS258 multiplexers select the row or column address from the ter-
minal bus address lines for memory cycles. Which address is selected
is determined by R/C (delay line R12-2). These multiplexers are put in
the hi-Z state during refresh cycles and during power on (when refresh
is occuring continuously).
The function of the 74LS244 buffer is to either transfer or block the
re.fresh address counter outputs from the internal address bus. This
buffer is enabled whenever refresh cycles are occuring (i.e. refresh
cycle or power on).

13255
Memory Controller
13255-91252/08
REV JUN-23-81
3.4.4
Whether the multiplexer is in the refresh or memory state is controlled
by a 74LS74 D-flip flop (U24). This flip flop can be set to the re-
fresh state in one of two ways: the power on signal is fed to the pre-
set input to initialize the system and to allow for continuous refresh
during power on. The flip flop can also be clocked to the refresh
state by the signal RFSH (U14-8) which indicates the start of a refresh
cycle. The multiplexor is reset to the memory state by the signal RFSH
STALL (U13-5) at the clear input. This occurs halfway through the RAS
pre charge time of the previous refresh cycle to allow the memory ad-
dresses sufficient setup time before the next memory cycle.
3.5 REFRESH ADDRESS GENERATOR
3.6
3.6.1
The refresh address generator consists of a 74LS393 dual four bit
counter (U45). This counter is allowed to come up in an indeterminant
state and is then continuously clocked through the 128 possible refresh
addresses. The eigth bit also counts although it is not necessary as a
refresh address line. The counter is clocked by the signal COUNT (U26-
6). COUNT is the inverted refresh row address strobe, and therefore
the refresh address generator is clocked each refresh cycle by the
trailing edge of the row address strobe.
REFRESH TIMER
Each row of the dynamic memories must be completely refreshed every 2
msec.
Since each memory is organized into 128 rows, there must be 128
refresh cycles every 2 msec to avoid loss of information. This means
that a refresh cycle must occur every 15.63 usec. The system clock is
4.915 MHz. If this clock is divided by 64 and the resulting edge used
to trigger a refresh cycle, a refresh will occur every 13.02 usec.