HP 13255 User manual

BP 13255
MEMORY CONTROLLER MODULE
Manual Part 10. 13255-912q9
1/.2S.;l
PRINTED
JUN-23-81
DATA TERMINAL
TECHNICAL INFORMATION
HEWLETT ifi PACKARD
Printed in U.S.A.

13255
Processor (8085A-2) Module 13255-91249/02
REV FEB-14-82
1.0 INTRODUCTION.
The processor (8085A-2) module functions as the .. in controlling unit
for the 2747F terminal. It also contains the hardware to intertace the
processor to the external keyboard. The processor retches instructions
trom memory and pertorms I/O operations on other .adul.s attached to
the terminal data bus (backplane ass.bly). !be 8085A-2 lIOdule has the
capability ot down loading code in a RAM based 2647F.
2.0 OPERATING PARAMETERS.
A summary of operating parameters tor the Processor (8085A-2) Module is
contained in tables 1.0 through 6.7
Table 1.0 Physical Parameter.
================================================================================
1 PART 1 Size (L x Wx D) Weight 1
I NUMBER 1 NOMENCLATURE 1 +/-0.100 Inche. 1 (Pounds) 1
/==============1==============================1======================1=========1
1 I 1 1 1
I 02640-60249 I PROCESSOR (8085A-2) I 12.5 x 4.0 x 0.5 1 0·5 1
1 I I 1 1
1 I I 1 1
1 I 1 1 1
1==============================================================================1
I 1
1 NUMBER OF BACKPLANE SLOTS REQUIRED: 1 I
1 I
================================================================================

HP 13255
MEMORY CONTROLLER MODULE
Manual Part 10. 13255-912q9
PRIM'l'ED
1/:IS-.;2
JUH-23-81
IOTlCE
The information contained in this document is subject to change
without notice.
HEWLETl'-PACKARD MAKES 10 WARRANTY OF AMY KIND WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT lOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Hewlett-Packard
shall not be liable for errors contained herein or tor incidental or
consequential damages in connection with the furnishing, performance,
or use of this material.
This document contains proprietary information which is protected by
copyright. All rights are reserved. No part of this document may be
photocopied or reproduced without the prior written consent of Hewlett-
Packard Company.
Copyright c 1982 by HEWLETT-PACKARD COMPANY
NOTE: This document is part of the 2647F DATA TERMINAL product
series Technical Information Package (HP 13255).

13255
Processor (8085A-2) Module
1.0 INTRODUCTION.
13255-91249/02
REV FEB-14-82
The processor (8085A-2) aodule functions as the .. in controllin, unit
for the 2747F terminal. It also contains the hardware to interface the
processor to the external keyboard. The processor f.tch •• in.truction.
trom memory and performs I/O operation. on other .odul.. attached to
the terllinal data bus (backplane ass.bly). 'l'b. 8085A-2 lIOdule has the
capability ot down loading code in a RAM based 2647F.
2.0 OPERATING PARAMETERS.
A summary of operating parameters tor the Proces.or (8085A-2) Modul. i.
contained in tables 1.0 through 6.7
Table 1.0 Physical Parameters
-===============================================================================
PART 1 I Size (L x Wx D) I Weisht
NUMBER 1 NOMENCLATURE 1 +/-0.100 Inches I (Pounds)
==============1==============================1======================1=========
1 1 I
02640-60249 I PROCESSOR (8085A-2) I 12.5 x 4.0 x 0.5 I 0.5
I I I
I I I
I 1 1
==============================================================================
NUMBER OF BACKPLANE SLOTS REQUIRED: 1
================================================================================

13255
13255-91252/03
Rev JUN-23-81
Memory Controller
Table 2.0 Reliability and Environmental Information
===============================================================================-
1
1
Environmental: ( X ) HP Class B () Other:
1
1
I Restrictions: Type tested at product level
,
1
1==============================================================================
1
1
Failure Rate: 4.774 (percent per 1000 hours)
,
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Table 3.0 Power Supply and Clock Requirements -Measured
(+/- 5% Unless Otherwise Specified)
--------------------------------------------------------------------------------
-------------------------------------- ----------------------------------------
+5 Volt Supply
+12 Volt Supply -12 Volt Supply -42 Volt Supply
@ 0.5 A
mA
NOT APPLICABLE NOT APPLICABLE NOT APPLICABLE
-------------------------------------- ---------------------------------------
-------------------------------------- ---------------------------------------
115 volts AC 220 volts AC
A A
NOT APPLICABLE NOT APPLICABLE
------------------------------------------------------------------------------
------------------------------------------------------------------------------
Clock Frequency:
4.915 MHz
================================================================================
Table 4.0 Jumper Definition
================================================================================
PCA Function I
I
Designation I I
1=============1================================================================1
1 I I
I 1 I
1 Wl 1 RAM/ROM Based Terminal (see section 3.8) I
I I ,
I I I
================================================================================

13255
Memory Controller
Table
5.0
Connector Information
13255-91252/04
Rev JUN-23-81
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Connector
I
Signal
Signal
and Pin No. I
Name Description
------------- -------------- -------------------------------------------------
------------- -------------- -------------------------------------------------
P1,
Pin 1
+5V
+5 Volt Power Supply
-2
GND Ground Common Return
(Power and Signal)
-3
SYSCLK
4.915 MHz
System Clock
-4
Not Used
-5
ADDRO
Negative True, Address Bit
0
-6 ADDR1
Negative True, Address
Bit
1
-1
ADDR2
Negative True, Address
Bit
2
-8
ADDR3
Negative True, Address Bit
3
-9
ADDR4
Negative True, Address Bit 4
-10
ADDR5
Negative
True,
Address Bit
5
-11
ADDR6
Negative
True,
Address Bit
6
-12
ADDR1
Negative True, Address Bit
1
-13
ADDRa
Negative True, Address Bit
8
-14
ADDR9
Negative True,
Address Bit
9
-15
ADDR10
Negative True,
Address Bit
10
-16 ADDR11
Negative True,
Address Bit
11
-11
ADDR12
Negative True, Address Bit 12
-18
ADDR13
Negative True,
Address Bit
13
-19
ADDR14
Negative True, Address Bit 14
-20
ADDR15
Negative True, Address Bit
15
-21 10
Negative
True, Input
Output/Memory
-22
GND
Ground Common Return
(Power and Signal)
==============-=================================================================

13255
Memory Controller
Table 5.0
Connector Information (cont)
13255-91252/05
Rev JUN-23-81
-----------------------------------------------.---------------------------------
----------------------------- --------------------------------------------------
Connector I
and Pin No.1
-------------
-------------
P1, Pin A
-B
-C
-D
-E
-F
-H
-J
-K
-L
-M
-N
-p
-R
-S
-T
-u
-v
-W
-x
-y
-z
Signal
Name
--------------
--------------
GND
PON
BUS 0
BUS 1
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7
WRITE
WAIT
ADDR16
ADDR17
ADDR18
REQ
Signal
Description
-------------------------------------------------
-------------------------------------------------
Ground Common Return (Power and Signal)
Not Used
Not Used
Positive True, System Power On
Negative True, Data Bus Bit 0
Negative True, Data Bus Bit 1
Negative True, Data Bus Bit 2
Negative True, Data Bus Bit 3
Negative True, Data Bus Bit 4
Negative True, Data Bus Bit 5
Negative True, Data Bus Bit 6
Negative True, Data Bus Bit 7
Negative True, Write/Read Type Cycle
Not Used
Negative True, Assert Wait State
Not Used
Not Used
Positive True, Address Bit 16
Positive True, Address Bit 17
Positive True, Address Bit 18
Negative True, Request (Bus Data Valid)
Not Used
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------

13255
Memory Controller
13255-91252/06
Rev JUN-23-81
3.0 FUNCTIONAL DESCRIPTION. Refer to the block diagram (figure 1),
schematic diagram (figure 2 and 3), the timing diagram (figure 4), and
the parts list (02640-60252).
The Memory Controller Module provides program and variable space for
the terminal. It consists of memory drivers and series termination
resistors, data port, memory array, address multiplexer, refresh
address generator, refresh timer, refresh cycle generator, bus
interface and board select circuitry, and a memory cycle generator.
3.1 SERIES TERMINATION RESISTORS
The series termination resistors m1n1m1ze undershoot by terminating the
bus lines with the line impedance. This approximates to 20 ohms since
it consists of an 80 ohm line with distributed, lumped, and capacitive
lo~ds. Current limit protection is provided free which limits the
driver output to 75 mA if two or more array inputs are shorted
together.
3.2 DATA PORT
3.2.1
3.2.2
The data port consists of a 74LS244 data in driver (U46) and a 74LS373
data out transparent latch. This port is enabled whenever BOARD SELECT
(U53-6) and REQ (P1-Y) are both low, causing U56-3 to go low. The
direction of data flow is arbitrated by WRITE (P1-P) in the following
manner: if WRITE is high, then U56-8 will be active, resulting in data
transmission from the Memory Controller to the data bus. If WRITE is
low, then U56-6 will be active, and the data flow will be from the bus
to the memory array. Data is latched in the output latch by the trail-
ing edge of CAS, the COllunn address strobe.
The transparent data latch (U27) allows data to propagate through the
latch prior to being latched. This means the RAM access time is
optimized and if a higher speed RAM is used, the memory will appear to
be correspondingly higher in speed. The data is latched so that
completion of the memory cycle does not depend on the completion of the
processor memory handshake.

13255
Memory Controller
13255-91252/07
REV JUN-23-81
3.3 MEMORY ARRAY
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
3.4.3
The memory array consists of up to thirty-two 64K RAMS.
socketed to allow field upgrade and repair.
The RAMs are
The power distribution is via a low impedance 4-layer PC board struc-
ture. The ceramic capacitors which supply the transient current are
organized such that some redundancy exists. This allows reliable oper-
ation with one open circuit component.
The
memory array is organized as four modules of equal size (if all are
loaded). The entire array is activated by the start of a memory cycle,
which is when U71-9 goes low. At that time, a row address strobe is
sent to all four banks. The column address s"i;robe passes through a
four to one decoder which determines which module is selected for read
or write.
ADDRESS MULTIPLEXER
The address multiplexer consists of two 74LS258 quad inverting 2 to 1
line tri-state multiplexers (U75,76) and a 74LS244 octal tri-state buf-
fer (U55).
The 74LS258 multiplexers select the row or column address from the ter-
minal bus address lines for memory cycles. Which address is selected
is determined by R/C (delay line R12-2). These multiplexers are put in
the hi-Z state during refresh cycles and during power on (when refresh
is occuring continuously).
The function of the 74LS244 buffer is to either transfer or block the
re.fresh address counter outputs from the internal address bus. This
buffer is enabled whenever refresh cycles are occuring (i.e. refresh
cycle or power on).

13255
Memory Controller
13255-91252/08
REV JUN-23-81
3.4.4
Whether the multiplexer is in the refresh or memory state is controlled
by a 74LS74 D-flip flop (U24). This flip flop can be set to the re-
fresh state in one of two ways: the power on signal is fed to the pre-
set input to initialize the system and to allow for continuous refresh
during power on. The flip flop can also be clocked to the refresh
state by the signal RFSH (U14-8) which indicates the start of a refresh
cycle. The multiplexor is reset to the memory state by the signal RFSH
STALL (U13-5) at the clear input. This occurs halfway through the RAS
pre charge time of the previous refresh cycle to allow the memory ad-
dresses sufficient setup time before the next memory cycle.
3.5 REFRESH ADDRESS GENERATOR
3.6
3.6.1
The refresh address generator consists of a 74LS393 dual four bit
counter (U45). This counter is allowed to come up in an indeterminant
state and is then continuously clocked through the 128 possible refresh
addresses. The eigth bit also counts although it is not necessary as a
refresh address line. The counter is clocked by the signal COUNT (U26-
6). COUNT is the inverted refresh row address strobe, and therefore
the refresh address generator is clocked each refresh cycle by the
trailing edge of the row address strobe.
REFRESH TIMER
Each row of the dynamic memories must be completely refreshed every 2
msec.
Since each memory is organized into 128 rows, there must be 128
refresh cycles every 2 msec to avoid loss of information. This means
that a refresh cycle must occur every 15.63 usec. The system clock is
4.915 MHz. If this clock is divided by 64 and the resulting edge used
to trigger a refresh cycle, a refresh will occur every 13.02 usec.

13255
Memory Controller
13255-91252/09
REV JUN-23-81
3.6.2
The refresh timer consists of a 74LS393 dual four bit counter (U22) set
up as a divide by 64. The output of this counter is synchronized with
the falling edge of the system clock to avoid collisions between memory
and refresh cycles (the memory cycle is synchronized to the rising edge
of the system clock by the processor board). This synchronization is
accomplished by use of a 74s74 flip flop (U71). The synchronized out-
put (U71-6) feeds the preset input of another 74s74 flip flop (052)
which acts as a refresh pending latch. The output of this flip flop
(U52-5) is ANDed with the signal HEM BUSY (U52-8) which indicates if a
memory cycle is previously in progress. The positive true output of
this gate (014-8) is the signal RFSH, which indicates an active refresh
cycle in progress.
3.7 REFRESH CYCLE GENERATOR
3.7.1
3.7.2
The :refresh cycle generator generates a row address strobe which is fed
to the memory chips along with the refresh address; the combination of
these signals performs a RAS only refresh cycle for the memory array.
The cycle is triggered by the signal RFSH, inverted and presented to
the clock input of a 74LS112 J-K flip flop (U26). This flip flop is
tied to a permanent set state. Setting this flip flop causes the K
input of the other half of u26 to go high resulting in the toggle state
at the inputs of this flip flop (U26-2,3). The next rising edge of the
clock causes signal RFSH RAS to go low; it will remain so for one en-
tire clock cycle (204 nsec). Two 74LS74 D flip flops (013,23) extend
the refresh cycle by one more complete clock cycle to allow sufficient
RAS pre charge and address setup time as discussed above. U23-5 feeds
bac:k to the refresh timer to end the cycle and allow a new timing cycle
to begin.
During power on, the signal RESET forces u26 to the toggle state perma-
nently, resulting in continuous refreshing until RESET returns to the
high state.

13255
Memory Controller
13255-91252/10
REV JUN-23-B1
3.B
3.B.1
3.B.2
3.B.3
BUS INTERFACE AND BOARD SELECT CIRCUITRY
The bus interface circuitry consists of several buffer drivers, a wait
state generator and an 10 port designed to be used by OEM's for soft-
ware protection. The bus signals SYSCLK, REQ, and PON are buffered by
74LS244 drivers to reduce loading. In addition, SYSCLK and REQ are
also inverted to be used in that state by the timing circuitry.
The Memory Controller Module requires one additional wait state be add-
ed to the normal bus cycle in order to provide sufficient time to ac-
complish memory reads and writes. To add this extra state, a wait
state latch is used. This latch is a 74LSl12 J-K flip flop (U44).
This flip flop is set by (071-9), which signals the start of a memory
cycle and is cleared by CAS, the column address strobe. This timing
results in the addition of one extra wait state. WAIT is driven on to
the bus by a 74s03 open collector NAND gate (U42-3).
The Memory Controller Module incorporates a feature which will allow
any interested party to protect his applications software on the 2647F
by providing space for a four byte code which can be burned into a 32xB
PROM by the user; this code can be used to encrypt the applications
software by any number of algorithms. U41 is a socket for a 32xB field
programmable PROM (Harris 7603 or equivalent). The four byte code can
be accessed by reading 10 ports BAOO, BA02, BA04, and BA06 (hex). The
codes will appear to the processor to be the inverted state of what is
encoded in the PROM.

13255
Memory Controller
13255-91252/11
REV JUN-23-81
3.8.4
The board select circuitry combines the state of two of the three most
significant bus address lines, ADDR16 and ADDR18, as follows:
Table 6.0
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
ADDR18
ADDR17
ADDR16 FUNCTION
0 0 0 Code Page 0
0 0 1 Unused
0 1 0 Code Page 1
0 1 1 Unused
1 0 0
RAM Space for Variables
1 0 1 Unused
1 1 0 RAM
for BASIC Workspace
1 1 1 Display/IO Space
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
3.8.5
As can be seen from the above table, a RAM-based terminal would have to
respond to all four cases where ADDR16=0; a ROM-based terminal needs to
respond to the two cases where ADDR18 and ADDR16 =10 . When jumper W1 is
absent, the output of the AND gate (U14-6) passes the inverted value of
ADDR18.
This gets combined with the value of ADDR16 to generate MEMGO
(U42-6). It is also combined with 10 to generate BOARD SELECT (053-6)
which is used to enable the data port and to enable the row and column
address strobes to the memory array.
When W1 is present, u14-5 is tied to ground, therefore the output of
the AND gate (U14-6) is permanently low. In this case, MEMGO and BOARD
SELECT depend only on the value of ADDR16.

13255
Memory Controller
13255-91252/12
REV JUN-23-81
3.9
3.9.1
3·9·3
MEMORY CYCLE GENERATOR
The memory cycle generator is a synchronous sequntial state machine
composed
of several flip flops and gates. The purpose of this state
machine is to generate the row and column address strobes for memory
cycle operations with the appropriate timing.
A memory cycle begins when HEMGO goes low. This is synchronized with
the leading edge of REQ by a 74s74 flip flop (071). This also accom-
plishes the rising edge clock synchronization mentioned above in sec-
tion 3.6.2, as REQ is synchronized with the clock by the processor.
The output of this flip flop (071-9) represents a memory cycle pending.
This signal is ANDed with RFSH to prevent a memory cycle from starting
while a refresh cycle is in progress. The output of this gate(Ul5-6)
indicates an active memory cycle. The leading (negative) edge of this
cycle active signal sets HEM BUSY to the true state, thus
the start of any refresh cycle; it also clocks a 74LSl12
preventing
flip flop
which starts MEMRAS, the row address strobe (Ul2-12). Two flip flops
(U13 and U25) then maintain HEMRAS in the low state for 2 clock cycles
(408 nsec). The output of the second flip flop (U25-9) is the column
address strobe, CAS. It lasts for one clock cycle (204 nsec) and fol-
lows the leading edge of HEMRAS by 204 nsec subject to logic delays.
As with the refresh cycle generator, two 74LS74 D flip flops (U21) are
used to extend the memory cycle to allow for RAS pre charge time. The
output of the second of these (U21-5) resets HEM BUSY to the false
state, thus ending the memory cycle.
MEMRAS is ted to a delay line (HP part I 1810-0384, 50 nsec delay, taps
at 10 nsec intervals) where it is delayed 40 nsec to become R/C, the
signal which determines which halt of the address is fed through the
address multiplexers (see section 3.4.2).

13255
Memory Controller
13255-91252/13
REV JUN-23-81
3.9.5
MEMRAS is ANDed with BOARD SELECT the ORed with RFSH RAS to torm the
row address strobe signal to the memory array (Ul4-11). CAS is used to
latch data out; in addition, CAS is used to determine which module ot
memory is being addressed. This is accomplished with a 74LS138, 3 to 8
line decoder. This decoder uses ADDR18 and ADDR17 at the address pins
(Ul7-2,1) to determine which ot the tour memory modules is being ac-
cessed. When the decoder is enabled by BOARD SELECT, a CAS at the
other enable input (U17-5) produces a similar pulse at one ot four out-
puts; this pulse is used as the column address strobe for the accessed
module.

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JUN-23-81 13255-91252

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FIGURE 2
MEMORY CONTROLLER SCHEMATIC (PAGE 1)
JUN-23-81 13255-91252

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t. ALL CAPRClTOR5 AftE IN f'r1C.ROFARADS, ALL RESISTOR5 ARE' IN OHMS_
2_ VR3 INDICATCS NOM PULLE:1J r(J ti"V TIII1OU611 ,(R3, A It RESISTOR.
3. V18-111 28-211 38-311 'f8-'0/ SS-Sll 68-'" 7tJ-711 ,,-'" ARC IDENTICAL
.sOCkETS FOR '"K"" DYNAMIC RAM.
1(. All UNBL.J)'kED "ReUITRY 15 fI/fII!f.T OF THe I'1EMORT C.YCLE' 6CNCRATOR.
FIGURE 3
PI-N
Pf-,.,
PI-L
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PI-/-I
PI-r
PI-e
MEMORY CONTROLLER SCHEMATIC (PAGE 2)
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FIGURE 4
MEMORY CONTROLLER TIMING
JUN-23-81 13255-91252

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R£~EREtYCE OW65 ;
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BETWEEN T~RGETS IS 342. 90MM +.08MM (13.500 +.003IN)
ASSEMBLY DRAIJING
I.
2-08-82
NOTES;
UNLE 35 OTHERWI5E SF'ECIFIED:
ALL RESIST.4#CE IN fJHM5
ALL CAPAOTAlrCE IN MICROFARAf)S
MARA DATE ('!JDE (OPER 33)
(AIIASK /1.:; iiV[)ICA,Ei.J PI?t{)R TO WAvE SDLDE:R.
ITEMS U41( U5/, /.J18, LJ/9, LJ28, U29, U38, U39, U48, U49, U58, U59,
UIbB, Ll69, U7B, U79, UBB,A.ND U89 ARE NOT TO BE 1#5 TALL ED
OR MASKED,
FIGURE 5
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MEMORY CONTROLLER COMPONENT LOCATION DIAGRAM
JUN-23-81 13255-91252