IBM MPC603EC User manual

MPC603EC/D
(Motorola Order Number)
5/95
REV 2
MPR603HSU-03
(IBM Order Number)
The PowerPC name, PowerPC logotype, PowerPC Architecture, and PowerPC 603 are trademarks of International Business Machines Corp.
used by Motorola under license from International Business Machines Corp.
This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to
©
Motorola Inc. 1995
Instruction set and other portions © International Business Machines Corp. 1991–1995
™
603 Hardware Specifications
change or discontinue this product without notice.
Advance Information
PowerPC 603
™
RISC Microprocessor
Hardware Specifications
The PowerPC 603 microprocessor is an implementation of the PowerPC™ family of
reduced instruction set computer (RISC) microprocessors. This document contains
pertinent physical characteristics of the 603. For functional characteristics of the processor,
refer to the
PowerPC 603 RISC Microprocessor User’s Manual.
This document contains the following topics:
Topic Page
Section 1.1, “Overview” 2
Section 1.2, “General Parameters” 4
Section 1.3, “Electrical and Thermal Characteristics” 4
Section 1.4, “Pinout Diagram” 14
Section 1.5, “Pinout Listing” 15
Section 1.6, “Package Description” 17
Section 1.7, “System Design Information” 21
Section 1.8, “Ordering Information” 26
Appendix A, “General Handling Recommendations for the IBM Package” 27
In this document, the term “603” is used as an abbreviation for the phrase, “PowerPC 603
Microprocessor.” The PowerPC 603 microprocessors are available from Motorola as
MPC603 and from IBM as PPC603.

2 603 Hardware Specifications, REV 2
Preliminary—Subject to Change without Notice
1.1 Overview
The 603 is the first low-power implementation of the PowerPC microprocessor family of RISC
microprocessors. The 603 implements the 32-bit portion of the PowerPC Architecture™ specification,
which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data
types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit
integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture.
The 603 provides four software controllable power-saving modes. Three of the modes (doze, nap, and sleep
modes) are static in nature, and progressively reduce the amount of power dissipated by the processor. The
fourth is a dynamic power management mode that causes the functional units in the 603 to automatically
enter a low-power mode when the functional units are idle without affecting operational performance,
software execution, or any external hardware.
The 603 is a superscalar processor capable of issuing and retiring as many as three instructions per clock.
Instructions can execute out of order for increased performance; however, the 603 makes completion appear
sequential.
The 603 integrates five execution units—an integer unit (IU), a floating-point unit (FPU), a branch
processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute five
instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency
and throughput for 603-based systems. Most integer instructions execute in one clock cycle. The FPU is
pipelined so a single-precision multiply-add instruction can be issued every clock cycle.
The 603 provides independent on-chip, 8-Kbyte, two-way set-associative, physically addressed caches for
instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs
contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and
ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block
translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The 603 also
supports block address translation through the use of two independent instruction and data block address
translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously
with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture,
if an effective address hits in both the TLB and BAT array, the BAT translation takes priority.
The 603 has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603 interface protocol allows
multiple masters to compete for system resources through a central external arbiter. The 603 provides a
three-state coherency protocol that supports the exclusive, modified, and invalid cache states. This protocol
is a compatible subset of the MESI (modified/exclusive/shared/invalid) four-state protocol and operates
coherently in systems that contain four-state caches. The 603 supports single-beat and burst data transfers
for memory accesses; it also supports both memory-mapped I/O and direct-store addressing.
The 603 uses an advanced, 3.3-V CMOS process technology and maintains full interface compatibility with
TTL devices.
1.1.1 PowerPC 603 Microprocessor Features
Major features of the 603 are as follows:
• High-performance, superscalar microprocessor
— As many as three instructions issued and retired per clock
— As many as five instructions in execution per clock
— Single-cycle execution for most instructions
— Pipelined FPU for all single-precision and most double-precision operations

603 Hardware Specifications, REV 2 3
Preliminary—Subject to Change without Notice
• Five independent execution units and two register files
— BPU featuring static branch prediction
— A 32-bit IU
— Fully IEEE 754-compliant FPU for both single- and double-precision operations
— LSU for data transfer between data cache and GPRs and FPRs
— SRU that executes condition register (CR) and special-purpose register (SPR) instructions
— Thirty-two GPRs for integer operands
— Thirty-two FPRs for single- or double-precision operands
• High instruction and data throughput
— Zero-cycle branch capability (branch folding)
— Programmable static branch prediction on unresolved conditional branches
— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
— A six-entry instruction queue that provides look-ahead capability
— Independent pipelines with feed-forwarding that reduces data dependencies in hardware
— 8-Kbyte data cache—two-way set-associative, physically addressed; LRU replacement
algorithm
— 8-Kbyte instruction cache—two-way set-associative, physically addressed; LRU replacement
algorithm
— Cache write-back or write-through operation programmable on a per page or per block basis
— BPU that performs CR look-ahead operations
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
— A 64-entry, two-way set-associative ITLB
— A 64-entry, two-way set-associative DTLB
— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
— Software table search operations and updates supported through fast trap mechanism
— 52-bit virtual address; 32-bit physical address
• Facilities for enhanced system performance
— A 32- or 64-bit split-transaction external data bus with burst transfers
— Support for one-level address pipelining and out-of-order bus transactions
— Bus extensions for direct-store operations
• Integrated power management
— Low-power 3.3 volt design
— Internal processor/bus clock multiplier that provides 1/1, 2/1, 3/1 and 4/1 ratios
— Three power saving modes: doze, nap, and sleep
— Automatic dynamic power reduction when internal functional units are idle
• In-system testability and debugging features through JTAG boundary-scan capability

4 603 Hardware Specifications, REV 2
Preliminary—Subject to Change without Notice
1.2 General Parameters
The following list provides a summary of the general parameters of the 603.
Technology 0.5
µ
CMOS (four-layer metal)
Die size 11.5 mm x 7.4 mm
Transistor count 1.6 million
Logic design Fully-static
Max. internal frequency 80 MHz
Max. bus frequency 66.67 MHz
Package Surface mount, 240-pin CQFP
Power supply 3.3
± 5% V dc
For ordering information, refer to Section 1.8, “Ordering Information.”
1.3 Electrical and Thermal Characteristics
This section provides both the AC and DC electrical specifications and thermal characteristics for the 603.
The following specifications are preliminary and subject to change without notice.
1.3.1 DC Electrical Characteristics
Table 1 and Table 2 provide the absolute maximum ratings, thermal characteristics, and DC electrical
characteristics for the 603.
Table 1. Absolute Maximum Ratings
Characteristic Symbol Value Unit
Supply voltage Vdd –0.3 to 4.0 V
Input voltage Vin –0.3 to 5.5 V
Storage temperature range Tstg –55 to 150 ° C
Notes : 1.Functional operating conditions are given in AC and DC electrical specifications. Stresses beyond the
maximum listed may affect device reliability or cause permanent damage to the device.
2. Caution : Input voltage must not be greater than the supply voltage by more than 2.5 V at all times
including during power-on reset.
Table 2. Thermal Characteristics
Characteristic Symbol Value Rating
Motorola wire-bond CQFP package thermal resistance,
junction-to-case (typical)
θ
JC
2.2 ° C/W
IBM C4-CQFP package thermal resistance,
junction-to-heat sink base
θ
JS 1.1
° C/W
Note: Refer to Section 1.7, “System Design Information,” for more information about thermal management.

603 Hardware Specifications, REV 2 5
Preliminary—Subject to Change without Notice
Table 3 provides the DC electrical characteristics for the 603.
Table 4 provides the power dissipation for the 603.
Table 3. DC Electrical Specifications
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ T
j
≤ 105 ° C
Characteristic Symbol Min Max Unit
Input high voltage (all inputs except SYSCLK) VIH 2.2 5.5 V
Input low voltage (all inputs except SYSCLK) VIL GND 0.8 V
SYSCLK input high voltage CVIH 2.4 5.5 V
SYSCLK input low voltage CVIL GND 0.4 V
Input leakage current, Vin = 3.465 V
1
Vin = 5.5 V
1
Iin —10 µ A
I
in — TBD
µ A
Hi-Z (off-state) leakage current, Vin
=
3.465 V
1
Vin
=
5.5 V
1
ITSI —10 µ A
I
TSI — TBD
µ A
Output high voltage, IOH
= –9
mA VOH 2.4 — V
Output low voltage, IOL
=14
mA VOL — 0.4 V
Capacitance, Vin =0V, f = 1 MHz
2
(excludes TS, ABB,
DBB, and ARTRY) Cin — 10.0 pF
Capacitance, Vin =0V, f = 1 MHz
2
(for TS, ABB, DBB, and
ARTRY) Cin — 15.0 pF
Notes : 1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and JTAG signals). For detailed
leakage information, please contact your local Motorola or IBM sales office.
2. Capacitance is periodically sampled rather than 100% tested.
Table 4. Power Dissipation
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ T
j
≤ 105 ° C
CPU Clock:
SYSCLK
Bus Frequency (SYSCLK) Unit
25 MHz 33 MHz 40 MHz 50 MHz 66 MHz
Full-On Mode
Typical
1:1 Max.
1.8 W
2.5 W
Typical
2:1 Max.
1.8 2.0 W
2.5 2.9 W
Doze Mode
1
1:1 Typical 740 mW
2:1 Typical 745 800 mW

6 603 Hardware Specifications, REV 2
Preliminary—Subject to Change without Notice
1.3.2 AC Electrical Characteristics
This section provides the clock andAC electrical characteristics for the 603.
1.3.2.1 Clock AC Specifications
Table 5 provides the clock AC timing specifications as defined in Figure 1. These specifications are for 25,
33.33, 40, 50, and 66.67 MHz bus clock (SYSCLK) frequencies.
Nap Mode
1
1:1 Typical 160 mW
2:1 Typical 140 160 mW
Sleep Mode
1
1:1 Typical 125 mW
2:1 Typical 110 130 mW
Sleep Mode—PLL Disabled
1
1:1 Typical 70 mW
2:1 Typical 30 40 mW
Sleep Mode—PLL and SYSCLK Disabled
1
1:1 Typical 2.0 mW
2:1 Typical 2.0 2.0 mW
Note : 1.The values provided for this mode do not include pad driver power (OVDD) or analog supply power
(AVDD).Worst-case AVDD = 15 mW.
Table 5. Clock AC Timing Specifications
Vdd = 3.3 ± 5% V dc, GND = 0 V dc , 0 ≤ T
J
≤ 105 ° C
Num Characteristic 25 MHz 33.33 MHz 40 MHz 50 MHz 66.67 Unit Notes
Min Max Min Max Min Max Min Max Min Max
Frequency of
operation 16.67 25.0 25.0 33.33 33.33 40.0 40.0 50.0 50.0 66.67 MHz
1 SYSCLK cycle
time 40.0 60.0 30.0 40.0 25.0 30.0 20.0 25.0 15.0 20.0 ns
2,3 SYSCLK rise
and fall time — 2.0 — 2.0 — 2.0 — 2.0 — 2.0 ns 1
4 SYSCLK duty
cycle
measured at
1.4 V
40.0 60.0 40.0 60.0 40.0 60.0 40.0 60.0 40.0 60.0 % 3
Table 4. Power Dissipation (Continued)
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ T
j
≤ 105 ° C
CPU Clock:
SYSCLK
Bus Frequency (SYSCLK) Unit
25 MHz 33 MHz 40 MHz 50 MHz 66 MHz

603 Hardware Specifications, REV 2 7
Preliminary—Subject to Change without Notice
Figure 1. SYSCLK Input Timing Diagram
1.3.2.2 Input AC Specifications
Table 6 provides the input AC timing specifications for the 603 as defined in Figure 2 and Figure 3. These
specifications are for 25, 33.33, 40, 50, and 66.67 MHz bus clock (SYSCLK) frequencies
.
8 SYSCLK
short- and
long-term jitter
— ± 150 — ± 150 — ± 150 — ± 150 — ± 150 ps 2
9 603 internal
PLL relock time — 100 — 100 — 100 — 100 — 100
µ s 3,4
Notes : 1.Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
2.This is the sum total of both short- and long-term jitter, and is guaranteed by design.
3.Timing is guaranteed by design and characterization, and is not tested.
4. PLL relock time is the maximum amount of time required for PLL lock after a stableVdd and SYSCLK are reached
during the power-on reset sequence.This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode.Also note that HRESET must be held asserted for a minimum of 255
bus clocks after the PLL relock time (100 µ s) during the power-on reset sequence.
5. Caution :The SYSCLK frequency and PLL_CFG0–PLL_CFG3 settings must be chosen such that the resulting
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective
maximum or minimum operating frequencies. Refer to the PLL_CFG0–PLL_CFG3 signal description in Section 1.7,
“System Design Information,” for valid PLL_CFG0–PLL_CFG3 settings, and to Section 1.8, “Ordering Information,”
for available frequencies and part numbers.
Table 5. Clock AC Timing Specifications (Continued)
Vdd = 3.3 ± 5% V dc, GND = 0 V dc , 0 ≤ T
J
≤ 105 °C
Num Characteristic 25 MHz 33.33 MHz 40 MHz 50 MHz 66.67 Unit Notes
Min Max Min Max Min Max Min Max Min Max
VM
CVil
CVih
SYSCLK
VM = Midpoint Voltage (1.4 V)
2 3
1

8 603 Hardware Specifications, REV 2
Preliminary—Subject to Change without Notice
Table 6. Input AC Timing Specifications
Vdd = 3.3 ±5% V dc, GND = 0 V dc, 0 ≤TJ≤105 °C
Num Characteristic 25 MHz 33.33 MHz 40 MHz 50 MHz 66.67 MHz Unit Notes
Min Max Min Max Min Max Min Max Min Max
10a Address/data/transfer
attribute inputs valid
to SYSCLK (input
setup)
4.5 — 4.0 — 3.5 — 3.0 — 2.5 — ns 2
10b All other inputs valid
to SYSCLK (input
setup)
6.5 — 6.0 — 5.5 — 5.0 — 4.5 — ns 3
10c Mode select inputs
valid to HRESET
(input setup)
(for DRTRY, QACK
and TLBISYNC)
8 *
tsys — 8 * tsys — 8 * tsys — 8 * tsys — 8 * tsys — ns 4,5, 6,7
11a SYSCLK to
address/data/transfer
attribute inputs
invalid (input hold)
1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns 2
11b SYSCLK to all other
inputs invalid (input
hold)
1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns 3
11c HRESET to mode
select inputs invalid
(input hold)
(for DRTRY, QACK,
and TLBISYNC)
0—0—0—0—0—ns4,6,7
Notes: 1.All input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4V of the
rising edge of the input SYSCLK. Both input and output timings are measured at the pin.See Figure 2.
2. Address/data/transfer attribute input signals are composed of the following: A0–A31, AP0–AP3, TT0–TT4,
TC0–TC1, TBST, TSIZ0–TSIZ2, GBL, DH0–DH31, DL0–DL31, DP0–DP7.
3. All other input signals are composed of the following:TS, XATS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA,
DRTRY, TEA, DBDIS,HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4.The setup and hold time is with respect to the rising edge of HRESET. See Figure 3.
5. tSYS is the period of the external clock (SYSCLK) in nanoseconds.
6.These values are guaranteed by design, and are not tested.
7.This specification is for configuration mode only. Also note that HRESET must be held asserted for a minimum of
255 bus clocks after the PLL relock time (100 µs) during the power-on reset sequence.

603 Hardware Specifications, REV 2 9
Preliminary—Subject to Change without Notice
Figure 2. Input Timing Diagram
Figure 3. Mode Select Input Timing Diagram
1.3.2.3 Output AC Specifications
Table 7 provides the output AC timing specifications for the 603 (shown in Figure 4). These specifications
are for 25, 33.33, 40, 50, and 66.67 MHz bus clock (SYSCLK) frequencies.
Table 7. Output AC Timing Specifications
Vdd = 3.3 ± 5%V dc, GND = 0V dc, CL = 50 pF, 0 ≤ TJ ≤ 105 ° C
Num Characteristic 25 33.33 40 50 66.67 Unit Notes
Min Max Min Max Min Max Min Max Min Max
12 SYSCLK to output
driven(outputenable
time)
1.0 — 1.0 — 1.0 — 1.0 — 1.0 — ns
13a SYSCLK to output
valid (5.5V to
0.8V—TS, ABB,
ARTRY, DBB)
— 14.0 — 13.0 — 12.0 — 11.0 — 10.0 ns 4
13b SYSCLK to output
valid (TS, ABB,
ARTRY, DBB)
— 13.0 — 12.0 — 11.0 — 10.0 — 9.0 ns 6
VMSYSCLK
VM = Midpoint Voltage (1.4V)
11a
ALL INPUTS
10b
10a
11b
MODE PINS
HRESET
10c
11c
VM
VM = Midpoint Voltage (1.4 V)

10 603 Hardware Specifications, REV 2
Preliminary—Subject to Change without Notice
14a SYSCLK to output
valid (5.5V to
0.8V— all except
TS, ABB, ARTRY,
DBB)
— 16.0 — 15.0 — 14.0 — 13.0 — 12.0 ns 4
14b SYSCLK to output
valid (all exceptTS,
ABB, ARTRY, DBB)
— 14.0 — 13.0 — 12.0 — 11.0 — 10.0 ns 6
15 SYSCLK to output
invalid (output hold) 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns 3
16 SYSCLK to output
high impedance (all
exceptARTRY,ABB,
DBB)
— 12.5 — 11.5 — 10.5 — 9.5 — 8.5 ns
17 SYSCLK to ABB ,
DBB, high
impedance after
precharge
— 1.0 — 1.0 — 1.0 — 1.0 — 1.2 t sys 5, 7
18 SYSCLK to AR TRY
high impedance
before precharge
— 12.0 — 11.0 — 10.0 — 9.0 — 8.0 ns
19 SYSCLK to AR TRY
precharge enable 0.2* tsys
+ 1.0
— 0.2 *
tsys
+ 1.0
— 0.2 *
tsys
+ 1.0
— 0.2 *
tsys
+ 1.0
— 0.2 *
tsys
+ 1.0
— ns 3, 5, 8
20 Maximum delay to
ARTRY precharge —1.0 —1.0 —1.0 —1.0 —1.2 tsys 5, 8
21 SYSCLK to AR TRY
high impedance
after precharge
— 2.0 — 2.0 — 2.0 — 2.0 — 2.25 t sys 5, 8
Notes: 1.All output specifications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8 V or 2.0V) of
the signal in question. Both input and output timings are measured at the pin. See Figure 4.
2. All maximum timing specifications assume CL= 50 pF.
3.This minimum parameter assumes CL = 0 pF.
4. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external voltage from
5.5 V to 0.8 V instead of from Vdd to 0.8V (5 V CMOS levels instead of 3.3 V CMOS levels).
5. tsys is the period of the external bus clock (SYSCLK) in nanoseconds (ns).The numbers given in the table must be
multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
6. Output signal transitions from GND to 2.0 V orVdd to 0.8 V.
7. Nominal precharge width for ABB and DBB is 0.5 tsysclk.
8. Nominal precharge width for ARTRY is 1.0 tsysclk.
Table 7. Output AC Timing Specifications (Continued)
Vdd = 3.3 ± 5%V dc, GND = 0V dc, CL = 50 pF, 0 ≤ TJ ≤ 105 ° C
Num Characteristic 25 33.33 40 50 66.67 Unit Notes
Min Max Min Max Min Max Min Max Min Max

603 Hardware Specifications, REV 2 11
Preliminary—Subject to Change without Notice
Figure 4. Output Timing Diagram
SYSCLK
12
14
13
15
16
16
ALL OUTPUTS
(Except TS, ABB
TS
ARTRY
ABB, DBB
VM VM
VM = Midpoint Voltage (1.4 V)
DBB, ARTRY) 15
VM
13
20
18
17
21
19

12 603 Hardware Specifications, REV 2
Preliminary—Subject to Change without Notice
1.3.3 JTAG ACTiming Specifications
Table 8 provides the JTAG AC timing specifications.
Figure 5 provides the JTAG clock input timing diagram.
.
Figure 5. Clock Input Timing Diagram
Table 8. JTAG AC Timing Specifications (Independent of SYSCLK)
Vdd = 3.3 ±5% V dc, GND = 0 V dc, CL = 50 pF, 0 ≤TJ≤105 °C
Num Characteristic Min Max Unit Notes
TCK frequency of operation 0 16 MHz
1 TCK cycle time 62.5 — ns
2 TCK clock pulse width measured at 1.4V 25 — ns
3 TCK rise and fall times 0 3 ns
4 TRST setup time to TCK rising edge 13 — ns 1
5 TRST assert time 40 — ns
6 Boundary-scan input data setup time 6 — ns 2
7 Boundary-scan input data hold time 27 — ns 2
8 TCK to output data valid 4 25 ns 3
9 TCK to output high impedance 3 24 ns 3
10 TMS,TDI data setup time 0 — ns
11 TMS,TDI data hold time 25 — ns
12 TCK to TDO data valid 4 24 ns
13 TCK to TDO high impedance 3 15 ns
Notes: 1.TRST is an asynchronous signal.The setup time is for test purposes only.
2. Non-test signal input timing with respect to TCK.
3. Non-test signal output timing with respect to TCK.
TCK
22
1
VM
VM
VM
3
3
VM = Midpoint Voltage (1.4 V)

603 Hardware Specifications, REV 2 13
Preliminary—Subject to Change without Notice
Figure 6 provides the TRST timing diagram.
Figure 6.TRST Timing Diagram
Figure 7 provides the boundary-scan timing diagram.
Figure 7. Boundary-Scan Timing Diagram
Figure 8 provides the test access port timing diagram.
Figure 8. Test Access Port Timing Diagram
4
5
TRST
TCK
67
Input Data Valid
8
9
8
Output Data Valid
Output Data Valid
TCK
Data Inputs
Data Outputs
Data Outputs
Data Outputs
10 11
Input Data Valid
12
13
12
Output Data Valid
Output Data Valid
TCK
TDI, TMS
TDO
TDO
TDO

14 603 Hardware Specifications, REV 2
Preliminary—Subject to Change without Notice
1.4 Pinout Diagram
Figure 9 contains the pin assignments for the 603.
Figure 9. PowerPC 603 Microprocessor Pin Assignments
GBL
A1
A3
VDD
A5
A7
A9
OGND
GND
OVDD
A11
A13
A15
VDD
A17
A19
A21
OGND
GND
OVDD
A23
A25
A27
VDD
DBWO
DBG
BG
AACK
GND
A29
QREQ
ARTRY
OGND
VDD
OVDD
ABB
A31
DP0
GND
DP1
DP2
DP3
OGND
VDD
OVDD
DP4
DP5
DP6
GND
DP7
DL23
DL24
OGND
OVDD
DL25
DL26
DL27
DL28
VDD
OGND
TT4
A0
A2
VDD
A4
A6
A8
OVDD
GND
OGND
A10
A12
A14
VDD
A16
A18
A20
OVDD
GND
OGND
A22
A24
A26
VDD
DRTRY
TA
TEA
DBDIS
GND
A28
XATS
TS
OVDD
VDD
OGND
DBB
A30
DL0
GND
DL1
DL2
DL3
OVDD
VDD
OGND
DL4
DL5
DL6
GND
DL7
DL8
DL9
OVDD
OGND
DL10
DL11
DL12
DL13
VDD
OVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
OVDD GND OGND CI WT QACK TBEN TLBISYNC RSRV AP0 AP1 OVDD OGND AP2 AP3 CSE TC0 TC1 OVDD CLK_OUT OGND BR APE DPE CKSTP_OUT CKSTP_IN HRESET PLL_CFG0 SYSCLK PLL_CFG1 PLL_CFG2 AVDD PLL_CFG3 VDD GND LSSD_MODE L1_TSTCLK L2 _TSTCLK TRST TCK TMS TDI TDO TSIZ0 TSIZ1 TSIZ2 OVDD OGND TBST TT0 TT1 SRESET INT SMI MCP TT2 TT3 OVDD GND OGND
240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212
211
210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181
OVDD DL29 DL30 DL31 GND DH31 DH30 DH29 OGND OVDD DH28 DH27 DH26 DH25 DH24 DH23 OGND DH22 OVDD DH21 DH20 DH19 DH18 DH17 DH16 OGND DH15 OVDD DH14 DH13 DH12 DH11 DH10 DH9 OGND OVDD DH8 DH7 DH6 DL22 DL21 DL20 OGND OVDD DL19 DL18 DL17 DH5 DH4 DH3 OGND OVDD DH2 DH1 DH0 GND DL16 DL15 DL14 OGND
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
100 101 102 103 104 105 106 107 108 109
110
111
112 113 114 115 116 117 118 119
120
1
TOP VIEW

603 Hardware Specifications, REV 2 15
Preliminary—Subject to Change without Notice
1.5 Pinout Listing
Table 9 provides the pinout listing for the 603.
Table 9. PowerPC 603 Microprocessor Pinout Listing
Signal Name Pin Number Active I/O
A0–A31 179, 2, 178, 3, 176, 5, 175, 6, 174, 7, 170,
11, 169, 12, 168, 13, 166, 15, 165, 16, 164,
17, 160, 21, 159, 22, 158, 23, 151, 30, 144,
37
High I/O
AACK 28 Low Input
ABB 36 Low I/O
AP0–AP3 231, 230, 227, 226 High I/O
APE 218 Low Output
ARTRY 32 Low I/O
AVDD 209 High Input
BG 27 Low Input
BR 219 Low Output
CI 237 Low Output
CLK_OUT 221 — Output
CKSTP_IN 215 Low Input
CKSTP_OUT 216 Low Output
CSE 225 High Output
DBB 145 Low I/O
DBDIS 153 Low Input
DBG 26 Low Input
DBWO 25 Low Input
DH0–DH31 115, 114, 113, 110, 109, 108, 99, 98, 97, 94,
93, 92, 91, 90, 89, 87, 85, 84, 83, 82, 81, 80,
78, 76, 75, 74, 73, 72, 71, 68, 67, 66
High I/O
DL0–DL31 143, 141, 140, 139, 135, 134, 133, 131, 130,
129, 126, 125, 124, 123, 119, 118, 117, 107,
106, 105, 102, 101, 100, 51, 52, 55, 56, 57,
58, 62, 63, 64
High I/O
DP0–DP7 38, 40, 41, 42, 46, 47, 48, 50 High I/O
DPE 217 Low Output
DRTRY 156 Low Input
GBL 1 Low I/O
GND 9, 19, 29, 39, 49, 65, 116, 132, 142, 152,
162, 172, 182, 206, 239 Low Input

16 603 Hardware Specifications, REV 2
Preliminary—Subject to Change without Notice
HRESET 214 Low Input
INT 188 Low Input
LSSD_MODE1205 Low Input
L1_TSTCLK1204 — Input
L2_TSTCLK1203 — Input
MCP 186 Low Input
OGND 8, 18, 33, 43, 53, 60, 69, 77, 86, 95, 103,
111, 120, 127, 136, 146, 161, 171, 181, 193,
220, 228, 238
Low Input
OVDD 10, 20, 35, 45, 54, 61, 70, 79, 88, 96, 104,
112, 121, 128, 138, 148, 163, 173, 183, 194,
222, 229, 240
High Input
PLL_CFG0–PLL_CFG3 213, 211, 210, 208 High Input
QACK 235 Low Input
QREQ 31 Low Output
RSRV 232 Low Output
SMI 187 Low Input
SRESET 189 Low Input
SYSCLK 212 — Input
TA 155 Low Input
TBEN 234 High Input
TBST 192 Low I/O
TC0–TC1 224, 223 High Output
TCK 201 — Input
TDI 199 High Input
TDO 198 High Output
TEA 154 Low Input
TLBISYNC 233 Low Input
TMS 200 High Input
TRST 202 Low Input
TSIZ0–TSIZ2 197, 196, 195 High I/O
Table 9. PowerPC 603 Microprocessor Pinout Listing (Continued)
Signal Name Pin Number Active I/O

603 Hardware Specifications, REV 2 17
Preliminary—Subject to Change without Notice
Notes:
1.These are test signals for factory use only and must be pulled up to VDD for normal machine operation.
2. OVDD inputs supply power to the I/O drivers and VDD inputs supply power to the processor core. Future
members of the 603 family may use different OVDD andVDD input levels; for example, OVDD = 3.3 V or
5.0 V, with VDD = 2.5 V.
1.6 Package Description
The following sections provide the package parameters and the mechanical dimensions for the 603. Note
that the 603 is currently offered in two types of CQFP packages—the Motorola wire-bond CQFP and the
IBM C4-CQFP.
1.6.1 Motorola Wire-Bond CQFP Package Description
The following sections provide the package parameters and mechanical dimensions for the Motorola
wire-bond CQFP package.
1.6.1.1 Package Parameters
The package parameters are as provided in the following list. The package type is 32 mm x 32 mm, 240-pin
ceramic quad flat pack.
Package outline 32 mm x 32 mm
Interconnects 240
Pitch 0.5 mm
TS 149 Low I/O
TT0–TT4 191, 190, 185, 184, 180 High I/O
VDD 4, 14, 24, 34, 44, 59, 122, 137, 147, 157,
167, 177, 207 High Input
WT 236 Low Output
XATS 150 Low I/O
Table 9. PowerPC 603 Microprocessor Pinout Listing (Continued)
Signal Name Pin Number Active I/O

18 603 Hardware Specifications, REV 2
Preliminary—Subject to Change without Notice
1.6.1.2 Mechanical Dimensions of the MotorolaWire-Bond CQFP Package
Figure 10 shows the mechanical dimensions for the wire-bond CQFP package.
Figure 10. Mechanical Dimensions of the Motorola Wire-Bond CQFP Package
*Reduced pin count shown for clarity. 60 pins per side
Min. Max.
A 30.86 31.75
B 34.6 BSC
C 3.75 4.15
D 0.5 BSC
E 0.18 0.30
F 3.10 3.90
G 0.13 0.175
H 0.45 0.55
J 0.25 –
AA 1.80 REF
AB 0.95 REF
θ12°6°
θ21°7°
R 0.15 REF
–H–
AB
θI
R
R
AA
θ2
H
Pin 240
C
A
B
Pin 1
DE
*Not to scale
G
F
J
Die Wire Bonds Ceramic Body
Alloy 42 Leads
Notes: 1. BSC—Between Standard Centers.
2. All measurements in mm.

603 Hardware Specifications, REV 2 19
Preliminary—Subject to Change without Notice
1.6.2 IBM C4-CQFP Package Description
The following sections provide the package parameters and mechanical dimensions for the IBM C4-CQFP
package.
1.6.2.1 Package Parameters
The package parameters are as provided in the following list. The package type is 32 mm x 32 mm, 240-pin
ceramic quad flat pack.
Package outline 32 mm x 32 mm
Interconnects 240
Pitch 0.5 mm
Lead plating Ni Au
Solder joint Sn/PB (10/90)
Lead encapsulation Epoxy
Solder-bump encapsulation Epoxy
Maximum module height 3.1 mm
Co-planarity specification 0.08 mm
Note: No solvent can be used with the C4-CQFP package. See AppendixA, “General Handling
Recommendations for the IBM Package,” for details.

20 603 Hardware Specifications, REV 2
Preliminary—Subject to Change without Notice
1.6.2.2 Mechanical Dimensions of the IBM C4-CQFP Package
Figure 11 shows the mechanical dimensions for the C4-CQFP package.
Figure 11. Mechanical Dimensions of the IBM C4-CQFP Package
*Reduced pin count shown for clarity. 60 pins per side
Min. Max.
A 31.8 32.2
B 34.4 34.8
C 3.05 3.15
D 0.45 0.55
E 0.18 0.28
Clip Leadframe
Chip
Tape Cast Ceramic
Epoxy Dam
Urethane
Solder-Bump Encapsulant
H
Jmin
Rad
0.08
F
G
A
B
E
Cmax
0.13 TOTAL sA-B
C
-
0.13 TOTAL sA-B
0.08 TOTAL MA-B
D
-A-
Pin 240
Pin 1
* Not to scale
All measurements in mm
Ang
-B-