IBM POWERPC 970MP Installation and operating instructions

IBM PowerPC® 970MP RISC Microprocessor
Application Note
PowerPC®970MP Differences
(Includes Differences for 970FX to 970MP)
Version: 1.0
Preliminary
November 15, 2006
®

Application Note
(Includes Differences for 970FX to 970MP)
IBM PowerPC® 970MP RISC Microprocessor Preliminary
Page 2 of 25
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November 15, 2006
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Title_970FX-MP_Differences.fm.1.0
November 15, 2006 -Preliminary
Note: This document contains information on products in the design, sampling and/or initial production phases
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Application Note
(Includes Differences for 970FX to 970MP)
Preliminary IBM PowerPC® 970MP RISC Microprocessor
AppNote_970FX-MP_Differences_TOC.fm.1.0
November 15, 2006
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1. Abstract ....................................................................................................................... 9
2. Overview ...................................................................................................................... 9
3. Processor Version Register (PVR) ............................................................................ 9
4. General Parameters .................................................................................................. 10
5. Design Enhancements for PowerPC 970MP .......................................................... 10
5.1 Dual Core Design ............................................................................................................................ 10
5.1.1 1MB L2 Cache per Core ........................................................................................................ 12
5.2 Processor Interconnect Bus ............................................................................................................ 13
5.2.1 SCOM control and status registers ........................................................................................ 13
5.2.2 Test Modes ............................................................................................................................ 13
5.2.2.1 Transmitter Pseudo-Random Data Test (RDT) .............................................................. 13
5.2.2.2 Transmitter Electrical Shorts Test (EST) ........................................................................ 13
5.2.2.3 Receiver Electrical Shorts Test (REST) ......................................................................... 14
5.2.2.4 Receiver Random Data Self Test ................................................................................... 15
5.2.3 Bus Configuration .................................................................................................................. 15
5.3 PowerTuning ................................................................................................................................... 17
5.3.1 Power Modes ......................................................................................................................... 17
5.3.2 Time Base and Decrementer ................................................................................................. 18
5.4 I2C Bus Interface ............................................................................................................................. 18
5.4.1 Clock Dithering (New feature for 970FX DD3.0, enhanced in 970MP) ................................. 18
5.4.2 Programmable Delays for Power Saving Mode Transitions .................................................. 19
5.5 Additional Dynamic Power Management ........................................................................................ 19
5.6 More Precise Kelvin Circuitry .......................................................................................................... 19
7. Timings ...................................................................................................................... 20
8. Package ..................................................................................................................... 20
8.1 Design Considerations for a 970MP Thermal Solution ................................................................... 20
8.1.1 Die Size ................................................................................................................................. 20
8.1.2 Capacitor Position ................................................................................................................. 21
8.2 Description of Signal Changes ........................................................................................................ 21
8.3 PowerPC 970MP Microprocessor Package Dimensions ................................................................ 22
Revision Log ................................................................................................................ 25

Application Note
(Includes Differences for 970FX to 970MP)
IBM PowerPC® 970MP RISC Microprocessor Preliminary
Page 4 of 25
AppNote_970FX-MP_Differences_TOC.fm.1.0
November 15, 2006

Application Note
(Includes Differences for 970FX to 970MP)
Preliminary IBM PowerPC® 970MP RISC Microprocessor
AppNote_970FX-MP_Differences_LOF.fm.1.0
November 15, 2006
Page 5 of 25
Figure 5-1. Dual Cores sharing processor interface ................................................................................. 11
Figure 5-2. 970MP Power Modes ............................................................................................................. 17
Figure 8-1. PowerPC 970MP Mechanical Package (Side and Top View) ................................................ 23
Figure 8-2. PowerPC 970MP Bottom Surface of CBGA Package (Bottom View) .................................... 24

Application Note
(Includes Differences for 970FX to 970MP)
IBM PowerPC® 970MP RISC Microprocessor Preliminary
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AppNote_970FX-MP_Differences_LOF.fm.1.0
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Application Note
(Includes Differences for 970FX to 970MP)
Preliminary IBM PowerPC® 970MP RISC Microprocessor
AppNote_970FX-MP_Differences_LOT.fm.1.0
November 15, 2006
Page 7 of 25
Table 3-1. PowerPC 970FX and 970MP Processor Version Registers (PVR) .......................................... 9
Table 4-1. General Parameters of the PowerPC 970FX and 970MP ...................................................... 10
Table 5-1. PowerPC 970MP Programmable Delay Parameters ............................................................. 16
Table 5-2. Power Mode States ................................................................................................................ 18
Table 5-3. PowerPC 970MP Latency of Deep Nap to Run Transition (Full Frequency Cycles) ............. 19
Table 8-1. PowerPC 970FX, and 970MP Die Size and Dimensions ....................................................... 20
Table 8-2. 970FX Pins Duplicated for each 970MP Processing Unit ...................................................... 21
Table 8-3. New 970MP Pins .................................................................................................................... 21
Table 8-4. Deleted 970FX Pins - not found on 970MP ............................................................................ 22

Application Note
(Includes Differences for 970FX to 970MP)
IBM PowerPC® 970MP RISC Microprocessor Preliminary
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AppNote_970FX-MP_Differences_LOT.fm.1.0
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Application Note
(Includes Differences for 970FX to 970MP)
Preliminary IBM PowerPC® 970MP RISC Microprocessor
AppNote_970FX-MP_Differences_Body.fm.1.0
November 15, 2006
1. Abstract
Page 9 of 25
1. Abstract
This preliminary application note describes the differences between the PowerPC®970FX microprocessor
and PowerPC 970MP microprocessor. The primary objective of the PowerPC 970FX remap to the 970MP is
to achieve a high frequency dual core processor. The design changes include a 1MB L2 cache per core,
support for higher bus speeds, power management improvements, and errata fixes.
2. Overview
The IBM 970MP RISC Microprocessor is a dual-core, 64-bit implementation of the IBM PowerPC®family of
reduced instruction set computer (RISC) microprocessors that are based on the PowerPC Architecture. This
dual microprocessor, also called the 970MP, includes a Vector/SIMD facility in each core which supports
high-bandwidth data processing and compute-intensive operations. The 970MP is designed to support
multiple system organizations, including desktop and low-end server applications, up through 4-way SMP
configurations.
The differences between the PowerPC 970FX and 970MP designs are described in the following sections:
• Process Version Register
• General Parameters
• Design Enhancements
• System Design Information
• Timings
•Package
3. Processor Version Register (PVR)
The PowerPC 970FX and 970MP have the following PVR values for the respective design revision levels.
Table 3-1. PowerPC 970FX and 970MP Processor Version Registers (PVR)
Design Revision Level 970FX PVR 970MP PVR
DD1.0 0x00391100 0x00440100
DD1.1 — 0x00440101
DD2.0 0x003C0200 —
DD2.1 0x003C0201 —
DD3.0 0x003C0300 —
DD3.1 0x003C0301 —

Application Note
(Includes Differences for 970FX to 970MP)
IBM PowerPC® 970MP RISC Microprocessor Preliminary
4. General Parameters
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AppNote_970FX-MP_Differences_Body.fm.1.0
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4. General Parameters
Table 4-1 provides a summary of the general parameters for the PowerPC 970FX and 970MP.
5. Design Enhancements for PowerPC 970MP
To create a dual core with improved power savings features, there were several enhancements made to the
PowerPC 970MP design.
This section describes the design enhancements to the 970MP.
5.1 Dual Core Design
The 970MP chip consists of two processing units (PUs), each containing an execution core with L1 caches, a
storage subsystem including L2 cache, and pervasive functions. In addition, a small amount of common logic
that is outside either PU is included to interface each PU to the single bus interface.
The two cores function as would two cores on separate chips for the most part. For example, they maintain
memory coherence via the bridge chip, they are able to Doze independently, and they have private access to
most processor resources including the L2. Also, like processors on separate chips, they scale frequency,
using the power tuning facility, together.
Sharing the same chip constrains the behavior of the two cores in several ways. First, the two PUs have
separate voltage planes for power, but the core voltages will always need to be within the delta specified in
the IBM PowerPC 970MP RISC Microprocessor Datasheet when the two processors are running. Also, the
core frequencies will always be the same. This would be true for two separate cores except for the Deep Nap
case, where one of two separate processors could reduce frequency to 1/64, while the other ran at functional
speed. The two 970MP cores must go into and come out of Deep Nap together.
The other difference between having dual cores on a single chip, versus two separate chips, is that they
share a single PI (processor interconnect) interface to the bridge chip. This requires that the interface
between the BIU and the PI logic be enhanced with buffers and muxes to support the sharing of the PI inter-
face between the two cores. Figure 5-1 on page 11 shows the relationship among the two cores and the
common logic.
For incoming PI data and commands, the output of the PI decoder is passed directly to both processors. For
outgoing PI data and commands, an arbiter and mux are introduced in front of the PI encoder to give one or
the other processor access to the outgoing PI bus at any given time. The arbiter implements a round robin
Table 4-1. General Parameters of the PowerPC 970FX and 970MP
Item 970FX Description 970MP Description
Die Size 66.2 sq. mm 153.8 sq. mm
Die Dimensions 7.07mm x 9.36mm 13.225 mm x 11.629 mm
Transistor Count 52 million 183 Million
Logic Design Static with some dynamic logic Static with some dynamic logic
Package 576-pin Ceramic ball grid array (CBGA)
25x25mm (1.0mm pitch)
575-pin Ceramic ball grid array (CBGA)
25x25mm (1.0mm pitch)