IBM 1 GB Microdrive Storage Card User manual

Series/1
GA34-0033-3
File No. S1-01
IBM Series/1
User's Attachment
Manual

GA34-0033-3
File No. $1-01
IBM Series/1
User's Attachment
Manual

Fourth Edition (September 1979)
This is a major revision of, and obsoletes, GA34-033-2 and Technical Newsletter GN34-0448.
This revision includes editorial and technical changes, which incorporate information about
the IBM 4952 Processor and the IBM General Purpose Interface Bus (GPIB) Adapter. Because
of the extensive changes, revision bars have been omitted; this manual should be reviewed in
its entirety.
Use this publication only for the purpose stated in the Preface.
Changes are periodically made to the information herein; any such changes will be reported in
subsequent revisions or Technical Newsletters.
It is possible that this material may contain reference to, or information about, IBM products
(machines and programs), programming, or services which are not announced in your country.
Such references or information must not be construed to mean that IBM intends to announce
such IBM products, programming, or services in your country.
Publications are not stocked at the address given below. Requests for copies of IBM publications
should be made to your IBM representative or the IBM branch office serving your locality.
This publication could contain technical inaccuracies or typographical errors. A form for readers’
comments is provided at the back of this publication. If the form has been removed, address your
comments to IBM Corporation, Systems Publications, Department 27T, P.O. Box 1328, Boca
Raton, Florida 33432. IBM may use and distribute any of the information you supply in any
way it believes appropriate without incurring any obligation whatever. You may, of course, con-
tinue to use the information you supply.
© Copyright International Business Machines Corporation 1976, 1977, 1979

Related Publications
Preface
This publication provides reference information to aid in designing logic
for communicating with an IBM Series/1 processor through the
input/output channel and several designated user attachment features. This
information is intended primarily for experienced engineers or technicians.
This publication is also useful to customers who need detailed information
for connecting their instruments and devices to the various attachment
features.
The reader should have a working knowledge of the information in the
appropriate IBM Series/1 processor and processor features description
manual.
The processor I/O channel architecture, or any aspect of the I/O
interfaces described in this publication, may be altered from time to time
by IBM or may be withdrawn by IBM in part or in whole.
This manual is organized as follows:
Chapter 1. Introduction describes the I/O channel and the user
attachment features.
Chapter 2. Processor I/O Channel describes the channel direct program
control (DPC) operations, cycle-steal (CS) operations, interrupts, and
initial program load (IPL).
Chapter 3. Timer Feature describes the timer feature, including signal
lines, interrupts, electrical characteristics, and physical characteristics.
Chapter 4. Teletypewriter Adapter Feature describes the teletypewriter
adapter feature, including interface options, timing sequences, electrical
characteristics, and physical characteristics.
Chapter 5. Integrated Digital Input/Output Feature describes the
integrated digital input/output feature, including operational, electrical,
and physical characteristics.
Chapter 6. Customer Direct Program Control (DPC) Adapter Feature
describes the customer direct program control adapter feature, including
operational, electrical, and physical characteristics.
Appendix A. General Purpose Interface Bus Adapter, RPQ D02118,
describes the Series/1 implementation of the digital interface contained in
IEEE Standard 488, including the commands and functions used by the
General Purpose Interface Bus (GPIB) Adapter.
Note: Installation instructions are shipped with each system order. These
instructions contain the information required for selecting options and
device addresses on the I/O attachment feature cards.
Additional publications are listed in the JBM Series/1 Graphic
Bibliography, GA34-0055.
Preface ili

iv GA34-0033

Chapter 1. Introduction 1-1
Processor I/O Channel 1-2
Channel Repower Feature 1-2
Channel Socket Adapter Feature 1-2
I/O Attachment Features 1-2
Timer Feature 1-2
Teletypewriter Adapter Feature 1-3
Integrated Digital Input/Output (1/0) Nonisolated
Feature 1-3
Customer Direct Program Control (DPC) Adapter
Feature 1-3
Customer Access Panel (CAP) Feature 1-3
General Purpose Interface Bus Adapter Feature 1-3
Chapter 2. Processor I/O Channel 2-1
Introduction 2-1
Functional Description of I/O Channel Signal Lines 2-2
Signal Line Groups 2-3
Functional Subsets of the Signal Lines 2-4
Service Group Line Definitions 2-7
Poll Group Line Definitions 2-12
Processor I/O Channel Operational Characteristics 2-15
Operational Sequences on the Channel 2-15
DPC Sequence Description 2-19
Interrupt-Service Sequence Description 2-22
Cycle-Steal Service Sequence Description 2-24
Poll Sequence Description 2-27
Processor-Initiated IPL Sequence Description 2-33
Host-Initiated IPL Sequence Description 2-36
Reset Sequences Description 2-39
Design Considerations for Operational Sequences 2-39
Operational Power Considerations 2-48
Processor I/O Channel Electrical Characteristics 2-50
Channel Signal Line Electrical Characteristics 2-50
Driver/Receiver Information 2-53
Other Attachment Considerations 2-65
Power Supply Electrical Characteristics 2-66
Processor I/O Channel Physical Characteristics 2-66
Signal Pin and Cable Assignments 2-66
I/O Channel Physical Components Description 2-70
Sequence of Plugging Device Attachments 2-73
Processor I/O Channel Attachment Features 2-73
Channel Repower Feature 2-73
Socket Adapter Feature 2-77
Chapter 3. Timer Feature 3-1
Introduction 3-1
Relationship to Other Features 3-3
Application Summary 3-3
Functional Description of the External Timer Signal
Lines 3-6
Signal Line Considerations 3-7
Application Sequences 3-7
Interval Timer 3-7
Pulse Counter 3-8
Contents
Pulse Duration Counter 3-8
Timer Feature Operational Characteristics 3-8
Interrupts 3-8
Interrupt Presentation 3-9
Status After Power Transitions and Resets 3-9
Timer Feature Electrical Characteristics 3-10
Timer Feature Physical Characteristics 3-11
Signal Pin Assignments 3-11
Pin Assignments Showing Customer Access Panel (CAP)
Connections 3-12
Jumper Selections 3-12
Timer Feature Design Considerations 3-12
Wiring Practices 3-12
Application Notes 3-12
Chapter 4. Teletypewriter Adapter Feature 4-1
Introduction 4-1
Relationship to Other Features 4-4
Application Summary 4-4
Data Transmission 4-11
Initial Program Load 4-12
Teletypewriter Adapter Operational Characteristics 4-12
Types of Receive Operations 4-13
Interrupt Presentation 4-14
Commands That Initiate Receive and Transmit
Operations 4-15
Transmit Operations 4-16
Receive Operations 4-17
Read Control and Write Control 4-20
System-Related Characteristics 4-21
Teletypewriter Adapter Electrical Characteristics 4-22
Teletypewriter Adapter Communications Lines 4-22
Driver/Receiver Information 4-26
Power Supplies 4-28
Teletypewriter Adapter Physical Characteristics 4-29
Physical Description 4-29
Signal Pin Assignments 4-29
Teletypewriter Adapter Design Considerations 4-30
Teletypewriter Device Information 4-30
Cable Connection to the Teletypewriter Adapter 4-30
Customer Access Panel (CAP) Connections 4-33
Chapter 5. Integrated Digital Input/Output Feature 5-1
Introduction 5-1
Digital Input (DI) 5-1
Digital Output (DO) 5-4
Integrated Digital I/O Operational Characteristics 5-4
Digital Output Operation 5-4
Digital Input Operation 5-6
Integrated Digital I/O Electrical Characteristics 5-7
Digital Input (DI) Characteristics 5-7
Digital and ‘External Sync’ Input Specifications 5-7
Digital Output (DO) Characteristics 5-8
Digital and ‘Ready’ Output Specifications 5-9
Integrated Digital I/O Physical Characteristics 5-9
Signal Pin Assignments 5-9
Contents Vv

Integrated Digital I/O to Customer Access Panel
Connections 5-12
Jumper Selections 5-17
Integrated Digital I/O Design Considerations 5-18
Application Notes 5-18
Chapter 6. Customer Direct Program Control (DPC) Adapter
Feature 6-1
Introduction 6-1
Relationship to Other Features 6-1
Application Summary 6-2
Functional Description of the DPC Adapter Signal Lines 6-3
1/O Active 6-3
Function Bits 6-4
Modifier Bits 6-4
Device Address 6-4
Data Bus Out 6-5
Interrupt Service Active 6-5
Strobe 6-5
Data BusIn 6-6
Interrupt Request 6-6
Condition CodeIn 6-6
Select Response 6-6
Halt or MCHK 6-7
System Reset 6-7
Power-On Reset 6-7
Diagnostic Mode and Diagnostic Mode Modifier 6-7
DPC Adapter Operational Characteristics 6-8
Output Sequence 6-8
Input Sequence 6-9
Interrupt-Service Sequence 6-10
DPC Adapter Electrical Characteristics 6-11
Drivers 6-1]
Receivers 6-12
DPC Adapter Physical Characteristics 6-13
Signal Pin Assignments 6-13
DPC Adapter to Customer Access Panel Connections 6-17
Jumper Selections 6-21
DPC Adapter Design Considerations 6-22
Application Notes 6-22
Appendix A. General Purpose Interface Bus Adapter
(RPQ DO2118) A-1
Introduction A-]
Adapter Functional Description A-1
Adapter Hardware Description A-2
Adapter Command Functions A-2
Application Summary A-5
Implementation of IEEE Standard 488 A-5
Index X-]
vi GA34-0033

Chapter 1. Introduction
A variety of interfaces are provided for attachment of the user’s own
input/output (I/O) devices and instruments to an IBM Series/1 processor.
Serial and parallel data paths, and a multifunction timer are provided. The
user may choose one of the I/O adapter features or design an I/O adapter
to communicate directly with the processor I/O channel.
Figure 1-1 shows the various methods of attachment and the available
attachment features. Each attachment is described in subsequent sections
of this chapter.
rs T4 Oo 4 ooo FF
| User's time , l Users ! .
| or count | instrument(s)/ | User S |
' dependen | device(s) device
i Signals __ “To “yO
Integrated .
Timer digital I/O ~ Telety pewriter
feature non-isolated adapter feature
Processor feature
Channel I/O channel ( |
controls
7/
Customer Channel
Channel
socket
DPC
adapter
repower
adapter
feature
feature
feature
i ) I/O
I User's channel
i
attachment
a
+
| card r r
Soa
saposes
—
|
Users
|
|
User's
r—
| device | | I/O adapter a
| |
_J. Le J LL we eH eH)
— L- ~
to other
pon
!
1
-———
ea
1
_
TTT
I/O
adapters
; User’s | ! User’s | | User’s |
| device | ‘device ) | device |
I
L—__ J Loe J Lo J
Figure 1-1. Relationship of user attachments to the processor I/O channel
Introduction 1-1

Processor I/O Channel
Input/output devices are attached to the processor through the I/O
channel. The channel, which can accommodate 256 device addresses, (1)
directs the flow of information between the I/O devices and main storage
and (2) contains the facilities for the control of the I/O operations. The
channel is asynchronous, with multidropped lines that link the processor
resource to its external facilities. I/O channel architecture includes
address, control, and data signal lines.
Channel Repower Feature
The channel repower feature isolates and redrives the I/O channel signal
and tag lines. The feature is used to extend the channel beyond the
processor enclosure.
Channel Socket Adapter Feature
The channel socket adapter feature consists of an IBM printed circuit card
that plugs into the backpanel of an IBM Series/1 processor or the IBM
4959 I/O Expansion Unit. The top edge of the IBM printed circuit card
has an industry-standard connector that accepts the user’s I/O adapter
card. To power the user’s circuits, +5 volts dc at 3 amperes, maximum, is
available at the connector.
I/O Attachment Features
The following I/O attachment features are available:
e Timer feature
e Teletypewriter adapter feature
e Integrated digital I/O nonisolated feature
e Customer direct program control (DPC) adapter feature
Timer Feature
The timer feature card has two separately addressable 16-bit timers. If
desired, time base and gating signals can be supplied, by the user, through
a connector on the top of the card.
Each timer can generate periodic or aperiodic interrupts with or without
the external gate.
Each timer can operate as an interval timer or pulse counter, or it can
operate as a self-contained pulse duration counter with end interrupt.
1-2 GA34-0033

Teletypewriter Adapter Feature
The teletypewriter adapter feature card provides a way of attaching a
serial I/O device. This feature provides a logical subset of the Electronic
Industries Association (EIA) RS232-C interface. Full-duplex operation and
initial program load (IPL) are supported by the adapter.
Attachment to a teletypewriter is by a dc-current loop (isolated or
nonisolated). Two other attachment options are offered: a TTL-compatible
interface and an EIA voltage-level interface.
Integrated Digital Input/Output (I/O) Nonisolated Feature
The integrated digital I/O nonisolated feature card contains:
¢ Two 16-point groups of nonisolated digital input/process interrupt
(DI/PI)
« Two 16-point groups of nonisolated digital output (DO)
Each group of DI/PI and DO has a ‘ready’ and a ‘sync’ line for
synchronizing operations with attached devices. The digital points for each
group and their associated ‘ready’ and ‘sync’ lines are available at three
top-card connectors.
Customer Direct Program Control (DPC) Adapter Feature
The direct program control (DPC) adapter feature card supplies a logical
subset of the I/O channel architecture. This feature provides a convenient
means of attaching I/O devices and subsystems to an IBM Series/1
processor, The interface circuits are TTL compatible. The adapter is
designed to perform direct program control functions only. The feature
card can be configured to accommodate 4, 8, or 16 I/O device addresses.
The adapter allows for interrupt vectoring of 16 interrupt sources.
There are 75 signal lines. These include: 18 data bus out, 18 data bus in,
16 interrupt request in, three function bits, four modifier bits, four device
address bits, and 12 control and response lines. The data flow is always 16
bits without parity option or 18 bits with parity option (two parity bits).
User attachment is through three top-card connectors.
Customer Access Panel (CAP) Feature
The customer access panel (CAP) feature provides an assembly for
mounting optional, quick-disconnect-type connectors for I/O equipment.
The assembly can accommodate one timer connector, one teletypewriter
connector, and up to four connectors for either the integrated digital I/O
feature or the customer direct program control (DPC) feature.
The assembly mounts to the standard EIA RS310B rack-mounting screw
holes at the rear of the enclosure frame.
General Purpose Interface Bus Adapter Feature
The IBM Series/1 General Purpose Interface Bus (GPIB) Adapter, RPQ
D02118, provides a 65K-byte cycle-steal interface for attaching up to 14
digital I/O devices to an IBM Series/1 processor. The devices attached via
the GPIB adapter must conform to the requirements described in IEEE
Standard 488-1978.
Introduction 1-3

1-4 GA34-0033

Introduction
Chapter 2. Processor I/O Channel
Input/output devices communicate with the processor and main storage
devices through the processor I/O channel. Attachment of the devices to
the channel is through an I/O adapter or I/O attachment logic card.
The channel directs the flow of information between the I/O devices, the
processor, and main storage. A maximum of 256 devices can be logically
addressed.
The processor I/O channel supports the following basic types of
operations:
e Direct program control (DPC) operations—an immediate data transfer
is made between main storage and the device for each Operate I/O
instruction. The data may consist of one byte or one word. The
operation may or may not terminate with an interrupt.
e Cycle-steal operations—an Operate I/O instruction can initiate
cycle-stealing data transfers of up to 65,535 bytes (per device control
block) between main storage and the device. Cycle-steal operations are
overlapped with processing operations. Word or byte transfers, device
control block (DCB) chaining, burst mode, and program-controlled
interrupts can be supported.
e Interrupt servicing operations—four preemptive priority interrupt
levels are available to facilitate device service. The device-interrupt
level is assignable by the program, and the device-interrupt capability
can be masked under program control.
e Initial program load (IPL) operations—a record consisting of initial
instructions for the processor is read into storage from either a local
I/O device or from a host system.
The channel provides comprehensive error checking, including time-outs,
sequence checking, and parity checking. Reporting of errors, exceptions,
and status is accomplished by (1) recording condition codes in the
processor during execution of Operate I/O instructions, and (2) recording
condition codes and an interrupt information byte (IIB) in the processor
during interrupt acceptance. Additional status words may be used by the
device, as necessary, to describe its status.
The I/O channel is asynchronous and multidropped. Asynchronous means
that there are no timing restrictions inherent in the architecture. The
response from a given I/O device triggers the next sequential action rather
than a specified timing condition. (Time-out conditions for error detection
are not excluded.) An asynchronous channel allows the attachment of
devices that have various speeds and technologies over a wide range of
distances or delays.
All I/O channel signal lines are TTL-level compatible. This allows the user
freedom in the design of I/O channel attachments.
Processor I/O Channel 2-1

The I/O channel signal lines are distributed internally via the processor
backpanel board to each I/O attachment card socket. Distribution of the
channel signal lines can be continued by connecting cables or a channel
repower feature from a processor I/O socket (usually the A-socket) to an
adjacent I/O expansion unit, as the particular processor or configuration
requires. Refer to the IBM Series/1 Configurator, GA34-0042, for details
about the requirements for the use of the repower feature.
IBM I/O attachment cards plug directly into the backpanel sockets.
External I/O devices are connected to the attachment cards via top-card
connectors.
Two features are available for connecting non-IBM devices directly to the
channel: the channel socket adapter feature and the channel repower
feature.
e Channel socket adapter feature—this feature consists of an IBM
printed circuit card that plugs into the backpanel of the processor unit
or I/O expansion unit. An industry-standard connector on the top
edge of the IBM printed circuit card accepts the user’s I/O adapter
card. For further information, see ‘““Socket Adapter Feature’’ in this
chapter.
e Channel repower feature—this feature is a logic card that repowers
and isolates the channel signal lines. This card can be installed in any
I/O socket, as the last series element on the channel, to allow
connection of additional I/O adapters or controllers. For further
information, see ‘‘Channel Repower Feature” in this chapter.
If the user connects directly to the channel at the backpanel sockets
instead of through one of the available features, the unit load, the power,
and the physical requirements must be considered. These and other
requirements are discussed in subsequent sections of this chapter.
CAUTION: To achieve adequate results, good design practices—both
electrical and mechanical—must be adhered to. IBM bears NO
RESPONSIBILITY for customer logic or hardware.
Functional Description of I/O Channel Signal Lines
2-2 GA34-0033
The I/O channel consists of 81 signal lines divided into two physical
groups: the service group and the poll group. Each group can operate
concurrently and asynchronously with the other group; however, the
initiation of sequences on the channel is interdependent.
The service group supports:
e Data and control information transfers
e IPL initiation
e Reset functions
The poll group supports:
e Cycle-steal requests from the devices
e« Interrupt requests from the devices
e Acknowlegement of both types of requests

Signal Line Groups
Service Group Signal Lines
Poll Group Signal Lines
The I/O channel signal lines are shown, by group, in Figures 2-1 and 2-2.
Note: The direction is shown for each line with the assumption that the
I/O channel originates on the left and the I/O attachments are on the
right.
The signal lines associated with the service group are shown in Figure 2-1.
Signal
name
Address bus bits 0-15
Address bus bit 16
Data bus
Address gate
Address gate return
Service gate
Service gate return
Condition code in bus
Cycle input indicator
Cycle byte indicator
Status bus
Data strobe
Initiate IPL
IPL
Halt or MCHK (machine check)
System reset
Power on reset
Total number of lines
Figure 2-1.
The signal lines associated with the poll group are shown in Figure 2-2.
Signal
name
Request in bus
Cycle steal request in
Poll identifier
Poll
Poll prime
Poll propagate
Poll return
Burst return
Total number of lines
Figure 2-2.
Direction
Service group signal lines
Direction
Poll group signal lines
Number
of lines
16
I
ar
jh
pom
—.
pooh
pooweeh,
& —
jh,
ww
——_
ey
peed,
peveenh
—
oo
in
&
Number
of lines
Processor I/O Channel 2-3

Functional Subsets of the Signai Lines
Basic Subset
2-4 GA34-0033
The I/O channel signal lines can have subsets, depending on the level of
function required by the I/O attachment. In order of increasing level of
function, these subsets are: |
e Basic subset
e Interrupt subset
e Cycle-steal/IPL subset
Attachment to a subset is a prerequisite for attachment to the next higher
level subset.
The basic subset consists of the buses and tags to support functions
initiated by the processor; for example, direct program control (DPC)
commands. This includes the data transfers associated with the DPC
command itself. The basic subset supports DPC devices that do not
interrupt. I/O signal lines in the basic subset are shown in Figure 2-3.
Service group signal lines
Signal Number
name Direction of lines
Address bus bits 0-15 (Note 1) ——=——=——> | ()
Address bus bit 16 ———— |
Data bus (Note 2) ————np 18
Address gate ———— |
Address gate return —— |
Condition code in bus —————— 3
Data strobe ——————s |
Halt or MCHK ae
System reset —————————p |
Power on reset ———esp |
Poll group signal lines
Poll (Note 3) —_—————> |
Poll prime (Note 3) ——_—_——————p |
Poll propagate (Note 3) en |
Notes:
1. Address bus bits 0-15 need only be received in this subset.
2. Bidirectional data bus capability is assumed for this subset; however, if the
direction of data flow within a device is fixed (specifically, a read-only device
attachment with no write or interrupt capability), the device need not implement
bidirectional data drivers and receivers. In this case, the device must reject all
commands requiring a transfer in other than the direction implemented by the
device. For the interrupt subset (described in “Interrupt Subset” in this chapter),
the device must implement bidirectional data bus drivers and receivers.
3. ‘Poll and "poll prime’ need only be received, logically ANDed, and redriven on
the ‘poll propagate’ line to maintain continuity of the serial poll mechanism. Any
card installed on the channel, even though it does not operate on the channel,
must propagate ‘poll’ and ‘poll prime.’
Figure 2-3. Basic subset

Interrupt Subset
The interrupt subset consists of control buses and tags to support an
interrupting source on the I/O channel. This subset provides the means to:
(1). present interrupt requests to the processor, (2) resolve contention, (3)
acknowledge an interrupt, and (4) accept an interrupt.
The interrupt subset, in conjunction with the basic subset, supports DPC
devices that are interrupting sources. The I/O signal lines in the interrupt
subset are shown in Figure 2-4.
Service group signal lines
Signal
name Direction
Service gate ———
Service gate return 6
Poll group signal lines
Signal
name Direction
Request in bus 6
Poll identifier SUSE
Poll A
Poll prime sneer
Poll propagate SEs
Poll return fee
Figure 2-4.
Interrupt subset
Number
of lines
1
I
Number
of lines
16
pk
hk
eek
Processor I/O Channel
2-5

Cycle-Steal/IPL Subset
The cycle-steal/IPL subset consists of control buses and tags to support
cycle-steal, burst transfer, and IPL operations. This subset provides the
means to present cycle-steal requests to the processor, to resolve
contention, and to service the cycle-steal transfers. The cycle-steal/IPL
subset, in conjunction with the basic and the interrupt subsets, supports
devices that cycle-steal and DPC devices capable of IPL. The I/O signal
lines in the cycle-steal/IPL subset are shown in Figure 2-5.
Service group signal lines
Signal Number
name Direction of lines
Address bus bits 0-15 (Note 1) Ge | 6
Cycle input indicator (————— |
Cycle byte indicator S|
Status bus mente
Initiate IPL (Note 2) ——cn |
IPL (Note 2) S|
Poll group signal lines
Signal Number
name Direction of lines
Cycle steal request in |
Burst return (Note 3) —— |
Notes:
1. Address bits 0-15 must have full bidirectional capability for this subset.
2. Required only for devices supporting IPL. Initiate IPL is not required for devices
that only support IPL from a host system.
3. Required only if burst cycle-steal transfers are supported by the device.
Figure 2-5. Cycle-steal/IPL subset
2-6 GA34-0033

Service Group Line Definitions
Address Bus Bits 0-15. This is a 16-bit bidirectional bus that is received
by all I/O devices. The bus is used on direct program control (DPC)
sequences to select and pass commands to the I/O devices. On DPC
sequences, address bus bits 0-15 are logically equal to the contents of bits
0-15 of the first word of the IDCB. The channel select bit (IDCB bit 0)
on address bus bit 0 can be ignored for device selection.
The address bus is also used on cycle-stealing sequences to present main
storage addresses to the channel controls. On cycle-steal service sequences,
address bits 0-15, which are driven by the I/O device, correspond to
storage address bits O-15 of the data to be transferred.
Address bus bits 0-15 are not used on interrupt-service sequences.
Address Bus Bit 16. This bit is an outbound tag received by all I/O
devices. When active, this tag signals a DPC sequence to the I/O devices.
The receiver for this tag is always enabled.
Data Bus. This is an 18-bit bidirectional bus with 16 bits of data and two
parity bits (odd parity by byte). The data bus transfers data and control
information: (1) between the processor and the I/O devices on DPC and
interrupt-service sequences, and (2) between cycle-stealing devices and
main storage on cycle-steal service sequences.
On DPC write sequences, data bus bits 0-15 are logically equal to the
contents of bits 16—31 (second word) of the IDCB. If a single byte is to
be transferred to the device, the byte is transferred from bits 24-31 of the
IDCB; bits 16—23 should all be 0’s. DPC write sequences are specified by
address bus bit 1 (IDCB bit 1) equal to a logical 1.
Parity is always maintained for both bytes of the data bus on DPC write
sequences; however, certain relaxations of the requirement to check parity
on both bytes are allowed if a DPC device is byte-oriented. A
byte-oriented device is a DPC device that does not use bits 16—23 of the
IDCB for any DPC write or control function as specified in bits 1-3 of the
IDCB. In this case, the device does not need to examine or parity check
data bus bits 0-7 on DPC write or control sequences. A device that uses
bits 16—23 of the IDCB for at least one DPC write sequence is not a
byte-oriented device. Cycle-stealing devices cannot be byte-oriented
devices because they implement the start functions.
On DPC read sequences, data bus bits O0Q—15 are driven by the device, and
correspond to bits 16-31 of the IDCB. If a single byte is to be transferred
from the device, the byte is transferred on data bus bits 8-15 with data
bus bits O—7 equal to logical 0’s. DPC read sequences are specified by
address bus bit 1 (IDCB bit 1) equal to logical 0. Parity must be
maintained on both bytes of the data bus on DPC read sequences.
On interrupt-service sequences, the data bus is used to pass the interrupt ID
word to the processor. Data bus bits 0—15 are driven by the device, and
correspond to bits 0-15 of the interrupt ID word. The first byte of the
interrupt ID word (bits 0—7) is the interrupt information byte; the second
byte (bits 8-15) is the device address of the device being serviced.
Processor I/O Channel 2-7

2-8 GA34-0033
Parity must be maintained on both bytes of the data bus on interrupt
service sequences.
On cycle-steal service sequences, the data bus bits have the following
meanings:
e Output, word transfer—data bus bits 0-15 are logically equal to the
contents of the word at the storage address presented by the device;
this storage address must be even. The device indicates an output word
transfer by presenting ‘cycle input indicator’ equal to logical 0 and
‘cycle byte indicator’ equal to logical 0.
e Input, word transfer—data bus bits O—15 are driven by the device and
correspond to the word to be placed at the storage address presented
by the device; this storage address must be even. The device indicates
an input word transfer by presenting ‘cycle input indicator’ equal to
logical 1 and ‘cycle byte indicator’ equal to logical 0.
e Output, byte transfer—the main storage address presented by the
device determines the alignment of the byte on the data bus. If the
storage address is even, data bus bits 0-7 are logically equal to the
contents of the byte at the storage address. If the storage address is
odd, data bus bits 8-15 are logically equal to the contents of the byte
at the storage address. The device indicates an output byte transfer by
presenting ‘cycle input indicator’ equal to logical 0 and ‘cycle byte
indicator’ equal to logical 1.
e Input, byte transfer—the device must align the byte on the data bus
according to the storage address being presented. If the storage
address is even, data bus bits 0-7 are driven by the device and
correspond to the byte to be placed at the storage address. If the
storage address is odd, data bus bits 8—15 are driven by the device and
correspond to the byte to be placed at the storage address. The device
indicates an input by presenting ‘cycle input indicator’ equal to logical
1 and ‘cycle byte indicator’ equal to logical 1.
The I/O architecture allows both byte and word cycle-steal data transfers
during the execution of a given cycle-steal operation. For example, an
operation transferring an even number of bytes into a data table on an odd
storage boundary could transfer one byte, then a number of words, and
then end with a byte transfer.
Parity is maintained on both bytes of the data bus during cycle-steal
output transfers. I/O devices must check both bytes of the data bus
regardless of whether a word or byte is being transferred. Parity must be
maintained on both bytes of the data bus on cycle-steal input transfers.
During byte transfers, the channel or device must maintain a stable data
bus and parity for purposes of parity checking by the receiver of the data.
However, the logical value of the particular byte not being used does not
have to be specified because it is parity checked only. For output byte
transfers, the value of the unused byte may be different on each transfer
and may be different among the Series/1 processors. For input byte
transfers, most device attachments, as a matter of practice, have found it
simplest to zero out the unused byte and force the parity bit accordingly.

Address Gate. This is an outbound tag used during DPC sequences. This
tag signals a device that it can respond to initial selection and begin
execution of the command specified by bits 0-7 of the address bus.
Address Gate Return. This is an inbound tag used by the selected device
during a DPC sequence. This tag signals: (1) the reception of ‘address
gate,’ (2) the activation of ‘condition code in bus,’ and (3) the activation
of ‘data bus’ for a read sequence.
Service Gate. This outbound tag signals the device that last captured a poll
that a cycle-steal or interrupt-service sequence can begin. The I/O device
detects the leading edge of this tag following a poll capture to begin the
sequence; this is called service gate capture.
Service Gate Return. This is an inbound tag used by a device to signal a
service gate capture and activation of ‘address bus’ (on a cycle-steal
sequence), ‘data bus,’ ‘condition code in bus,’ and other tags as required
by the particular cycle-steal or interrupt-service sequence.
Condition Code In Bus. This is a three-bit, binary encoded inbound bus
used by the I/O device on DPC, interrupt, and cycle-steal sequences.
On DPC and interrupt-service sequences, the ‘condition code in bus’
corresponds to the condition code indicators in the level status register
(LSR) as follows:
Condition LSR
code in bit indicator
0 Even
1 Carry
2 Overflow
On cycle-steal service sequences, the ‘condition code in bus’ is used by the
device to pass the address key to the channel. On cycle-steal data
transfers, condition code bits O—2 are logically equal to the cycle-steal
address key. This key is bits 5—7 of the DCB control word previously
fetched by the device. During cycle-steal transfers for fetching the DCB
and for reporting residual status, a value of logical 0 is used for the
address key. During IPL cycle-steal transfers, a value of logical O is also
used for the address key.
Cycle Input Indicator. This is an inbound tag used by the device on a
cycle-steal service sequence. This tag signals the channel that the
cycle-steal is either: (1) an output from storage or (2) an input to storage.
When the indicator is a logical 0, an output from storage is indicated;
when the indicator is a logical 1, an input to storage is indicated.
Cycle Byte Indicator. This is an inbound tag used by the device on a
cycle-steal service sequence. This tag signals the channel that the
cycle-steal is either: (1) a word transfer or (2) a byte transfer. When the
indicator is a logical 0, a word transfer is indicated; when the indicator is a
logical 1, a byte transfer is indicated.
Processor I/O Channel 2-9