IBM PowerPC 604 User manual

Overview
PowerPC 604 Processor Programming Model -
Cache and Bus Interface Unit Operation
Exceptions
Memory Management
Instruction Timing
Signal Descriptions
System Interface Operation
Performance Monitor
PowerPC Instruction Set Listings -
Invalid Instruction Forms -
Glossary of Terms and Abbreviations i!el
Index 111111

Overview
-PowerPC 604 Processor Programming Model
Cache and Bus Interface Unit Operation
-Exceptions
Memory Management
Instruction Timing
Signal Descriptions
System Interface Operation
Performance Monitor
-PowerPC Instruction Set Listings
B Invalid Instruction Forms
-Glossary of Terms and Abbreviations
Index

MPR604UMU-01 MPC604UM/AD
11/94
PowerPC™ 604
RISC Microprocessor User's Manual
IBM Microelectronics

e Motorola Inc. 1994
Portions hereof e International Business Machines corp. 1991-1994. All rights reserved.
This document oontalns lnfonnatlon on a now product under development Motorola reserves tho right to change or discontinue this proooct without
notice. Information In this document Is provided solely to enable system and software Implementers to use PoworPC microprocessors. There are no
express or Implied copyright licenses granted hereunder to design or fabricate PowerPC Integrated circuits or integrated clrcubs based on the Information
In this document.
The PoworPC 604 microprocessor embodies the Intellectual property of I BM and of Motorola. However. neither party assumes any rosponsl:llllty or
llabillty as to any aspects of tho performance, operation, or other attributes of the microprocessor as malketed by tho other party. Neither party Is lo be
considered an agent or representative of tho other party, and neither has granted any right or authority to tho other to assume or create any express or
Implied Obligations on bs bohatt. Information such as data sheets, as well as sales terms and conditions such as prices, schaooles, and support, for tho
microprocessor may vary as between IBM and Motorola. Accordingly, customers wishing to leam more Information about tho products as marketed by a
given party should oontact that party.
Both IBM and Motorola reserve the right to modtty this manual and/or any of the products as described heroin without further notice. Nothing in !his
manual, nor In any ol tho errata sheets, data sheets, and other supporting documentation, shall be Interpreted as conveying an express or Implied
warranty, representation, or guarantee regarding the suitability ol the products for any particular purpose. The parties do not assume any llablllty or
Obligation for damages olany kind arising out olthe application or use ol these materials. Any warranty or other Obligations as to the products described
herein shall be undertaken solely by Iha marketing party to the customer, undera separate sale agreement between tho malkoting party and tho customer.
In tho absence ol such an agreomon~ no llablllty Is assumed by tho malketing party for any damages, actual or otherwise.
"Typical" parameters can and do vary In dlllerent applications. All operating parameters, lncuding "Typlcals," must be validated for each customer
application by customer's technical experts. Neither IBM nor Motorola oonvey any license undertheir respective Intellectual property rights nor tho rights
of others. Tho prooocts described In this manual are not designed, Intended, or authorized for use as components In systems Intended for surgical Implant
Into tho bocly, or other applications Intended to support or sustain Itta, orforanyother application In which tho faluro cl the proooct could create a situation
where personal Injury or death may occur. Should customer purchase or use the products forany such unintended or unauthorized application, customer
shall lndemntty and hold IBM and Motorola and their respective officers, employees, subsidiaries, affiliates, and dlstrllutors harmless against all claims,
costs, damages, and expenses, and reasonable attorney lees arising out of, directly or lndlrectiy, any claim of personal Injury or death associated with
such unintended or unauthorized use, even tt such claim alleges that Motorola or IBM was negligent regarding tho design or manufacture of the part.
Motorola and @ are registered trademalks of Motorola. Inc. Motorola, Inc. Is an E<1Jal Opportunity/Affirmative Action Employer.
IBM Is a registered trademark, and IBM MD-oelectronics Is a trademark of IBM Corp.
PowerPC, PowerPC Architecture, POWER Architecture, PowerPC 601. PowerPC 603, PowerPC 604, and /ltlllVK are trademalks of IBM Corp.
used by Motorola under license from IBM Corp.

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1.2.1.3
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1.2.1.5
1.2.2
1.2.2.1
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1.2.4.1
1.2.4.2
1.2.5
1.2.5.1
1.2.5.2
1.2.5.3
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1.3
Contents
CONTENTS
Tltle
About This Book
Page
Number
Audience .............................................................................................................xxii
Organization........................................................................................................xxii
Suggested
Reading .............................................................................................xxiii
Conventions .......................................................................................................
xxiv
Acronyms and Abbreviations .............................................................................. xxv
Tenninology Conventions •.....•.•••..................•••••••.•..•..............•••••..•.•...•..•.•..•.. xxviii
Chapter 1
Overview
Overview .............................................................................................................. 1-1
PowerPC 604 Microprocessor Features ••••...............•...•.••.•••..•.....•...•••..........•.• 1-2
PowerPC 604 Microprocessor Hardware Implementation ............•......•••.•••.••..•.. 1-7
Instruction Flow ........................................................................ .' ...................... 1-8
Fetch Unit .................................................................................................... 1-8
Decode/Dispatch Unit .................................................................................. 1-9
Branch Processing Unit (BPU) .................................................................... 1-9
Completion Unit .......................................................................................... 1-9
Rename Buffers ......................................................................................... 1-10
Execution Units .............................................................................................. 1-10
Integer Units (IUs) ..................................................................................... 1-10
Floating-Point Unit (FPU) ......................................................................... 1-11
Load/Store Unit (LSU) .............................................................................. 1-11
Memory Management Units (MMUs) .•••••••....•..•.••..................••.••.•............... 1-12
Cache Implementation ..........•..•.••••••.••••••••••••••••••• ,••.......•.....................•......... 1-12
Instruction Cache ....................................................................................... 1-13
Data Cache •••.••.................••••••••.••••••..••..•.•.......................••...•••••••..••••••••••••• 1-13
System Interface/Bus Interface Unit (BIU) .........•.••..•••••••......•••.•...•..•.••••••.••. 1-14
Memory Accesses ..•..••••••..•............•..........•••..•••••••.•••••••••••••••••••••••••••••••••••• 1-16
Signals........................................................................................................ 1-16
Signal Coofiguration.................................................................................. 1-17
Clocking......................................................................................................... 1-18
PowerPC 604 Microprocessor Execution Model............................................... 1-19
iii

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1.3.2.7
1.3.2.7.1
1.3.2.7.2
1.3.3
1.3.3.1
1.3.3.1.1
1.3.3.1.2
1.3.4
1.3.5
1.4
1.5
2.1
2.1.1
2.1.2
2.1.2.1
2.1.2.2
2.1.2.3
2.1.2.4
2.1.2.4.1
2.1.2.4.2
2.1.2.4.3
2.1.2.4.4
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.3
2.3.1
2.3.1.1
iv
CONTENTS
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Page
Number
Levels of the PowerPC Architecture .............................................................. 1-19
Registers and Programming Model ................................................................ 1-20
General-Purpose Registers (GPRs) ............................................................ 1-22
Floating-Point Registers (FPRs) ................................................................ 1-22
Condition Register (CR) ••.•.•.•.............•..........•..............................••....••....• 1-22
Floating-Point Status and Control Register (FPSCR) ..................••.•.•....... 1-23
Machine State Register (MSR) ...........•••......••..............................•.•.••........ 1-23
Segment Registers (SRs) ••••.•..............•••........•..........................•..•.••...•...... 1-23
Special-Purpose Registers (SPRs) ••.•.....................................••..•............... 1-23
User-Level SPRs •••..•.....•......••.....•••...............................••••...•.•............... 1-23
Supervisor-Level SPRs ....•••••....••••.....................................••••••.............. 1-23
Instruction Set and Addressing Modes .......................................................... 1-25
PowerPC Instruction Set and Addressing Modles ....................•....••.••........ 1-25
Instruction Set ........................................................................................ 1-25
Calculating Effective Addresses ............................................................ 1-27
Exception Model .................•.•.••......................•......•...........•.....•.••••.••............. 1-28
Instruction Timing ......................................................................................... 1-33
Power Management-Nap Mode ...................................................................... 1-35
Performance Monitor •........••••.•...........................•............................••••••••.......... 1-35
Chapter 2
PowerPC 604
Processor Programming Model
The PowerPC 604 Processor Register Set ........................................................... 2-1
Register Set ...................................................................................................... 2-2
604-Specific Registers ..................................................................................... 2-8
Instruction Address Breakpoint Register (IABR) ....................•.•.............•.•. 2-8
Processor Identification Register (PIR) ....................................................... 2-9
Hardware Implementation-Dependent Register 0 .................••.................• 2-10
Performance Monitor Registers ......•••••.••..•••.............•.••••.••.............•...•..•... 2-11
Monitor Mode Control Register 0 (MMCRO) ....................................... 2-11
Performance Monitor Counter Registers (PMCl and PMC2) ..........•••.• 2-13
Sampled Instruction Address Register (SIA) ............•.•.••••..................•. 2-15
Sampled Data Address Register (SDA) ................................................. 2-16
Operand Conventions ......................................................................................... 2-16
Floating-Point Execution Models-UISA ............•••••••.....................•••.......... 2-16
Da~ Organization in Memory and Data Transfers ..•••••••••••.•.••............•••••..... 2-17
Alignment and Misaligned Accesses .......................•..••••••••.•................••••..... 2-17
Floating-Point Operand ...........••••.••.............................•.•••••••.••••..................... 2-17
Effect of Operand Placement on Performance •••..............•..••••••...........••••.•••. 2-19
Instruction Set Summary .................................................................................... 2-19
Classes of Instructions ................................................................................... 2-21
Definition of Boundedly Undefined .......................................................... 2-21
PowerPC 604 RISC Microprocessor User'sManual

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2.3.4.3.8
2.3.4.3.9
2.3.4.4
2.3.4.4.1
2.3.4.4.2
2.3.4.4.3
2.3.4.4.4
2.3.4.5
2.3.4.6
2.3.4.6.1
Contents
CONTENTS
Title
Page
Number
Defined Instruction Class .......................................................................... 2-21
Illegal Instruction Class ....................................................................•........ 2-22
Reserved Instruction Class .......................................................................• 2-23
Addressing Modes ......................................................................................... 2-23
Memory Addressing .................................................................................. 2-23
Memory Operands ..........•......................•...................•............................... 2-23
Effective Address Calculation ...................................................................2-24
Synchronization ...........................•.............................................................2-24
Context Synchronization .......................................................................2-24
Execution Synchronization.................................................................... 2-25
Instruction-Related Exceptions.............................................................. 2-25
Instruction Set Overview ............................................................................... 2-26
PowerPC UISA Instructions .......................................................................... 2-26
Integer Instructions .................................................................................... 2-26
Integer Arithmetic Instructions.............................................................. 2-26
Integer Compare Instructions ................................................................ 2-28
Integer Logical Instructions................................................................... 2-28
Integer Rotate and Shift Instructions..•.................................................. 2-29
Floating-Point Instructions ........................................................................2-30
Floating-Point Arithmetic Instructions.................................................. 2-30
Floating-Point Multiply-Add Instructions............................................. 2-31
Floating-Point Rounding and Conversion Instructions ......................... 2-31
Floating-Point Compare Instructions..................................................•.. 2-32
Floating-Point Status and Control Register Instructions ....................... 2-32
Floating-Point Move Instructions.......................................................... 2-33
Load and Store Instructions....................................................................... 2-33
Self-Modifying Code............................................................................. 2-34
Integer Load and Store Address Generation.......................................... 2-35
Register Indirect Integer Load Instructions ........................................... 2-35
Integer Store Instructions....................................................................... 2-36
Integer Load and Store with Byte Reverse Instructions........................ 2-37
Integer Load and Store Multiple Instructions........................................ 2-38
Integer Load and Store String Instructions............................................ 2-39
Floating-Point Load and Store Address Generation .............................. 240
Floating-Point Store Instructions........................................................... 2-41
Branch and Flow Control Instructions....................................................... 2-43
Branch Instruction Address Calculation................................................ 2-44
Branch Instructions................................................................................2-44
Condition Register Logical Instructions................................................ 2-45
Trap Instructions.................................................................................... 2-45
System Link:age Instruction-VISA..........................................................2-46
Processor Control Instructions-VISA ..................................................... 2-46
Move to/from Condition Register Instructions...................................... 2-46
v

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2.3.6.3.2
2.3.6.3.3
2.3.7
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Page
Number
Move to/from Special-Purpose Register Instructions (UISA)............... 2-47
Memory Synchronization Instructions-VISA......................................... 2-47
PowerPC VEA Instructions ...........................................................................2-48
Processor Control Instructions-VEA ......................................................2-48
Memory Synchronization Instructions-VEA ..........................................2-49
Memory Control Instructions-VEA ........................................................2-50
User-Level Cache Instructions-VEA..................................................2-50
Optional External Control Instructions...................................................... 2-52
PowerPC OEA Instructions ...........................................................................2-52
System Linkage Instructions-DEA .........................................................2-52
Processor Control Instructions-OBA ......................................................2-52
Memory Control Instructions-DEA ........................................................2-54
Supervisor-Level Cache Management Instruction-(OEA) .................2-54
Segment Register Manipulation Instructions (OEA).............................2-55
Translation Lookaside BufferManagement lnstructions-(OEA) ....... 2-55
Recommended Simplified Mnemonics..........................................................2-57
Chapter 3
Cache and Bus Interface UnitOperation
3.1 Data Cache Organization.....................................................................................3-3
3.2 Instruction Cache Organization ...........................................................................3-4
3.3 MMUs/Bus Interface Unit ...................................................................................3-5
3.4 Memory Coherency Actions................................................................................3-8
3.4.1 604-Initiated Load and Store Operations.........................................................3-8
3.5 Sequential Consistency........................................................................................3-9
3.5.1 Sequential Consistency Within a Single Processor .........................................3-9
3.5.2 Weak Consistency between Multiple Processors ............................................3-9
3.5.3 Sequential Consistency Within Multiprocessor Systems ..............................3-10
3.6 Memory and Cache Coherency..........................................................................3-10
3.6.1 Data Cache Coherency Protocol....................................................................3-11
3.6.2 Coherency and Secondary Caches.................................................................3-13
3.6.3 Page Table Control Bits.................................................................................3-13
3.6.4 MESI State Diagram......................................................................................3-13
3.6.5 Coherency Paradoxes in Single-Processor Systems ...................................... 3-14
3.6.6 Coherency Paradoxes
in Multiple-Processor Systems...................................3-15
3.7 CacheConfiguration..........................................................................................3-15
3.8 Cache Control Instructions ................................................................................3-16
3.8.1 Instruction Cache Block Invalidate (icbi)......................................................3-16
3.8.2 Instruction Synchronize (isync).....................................................................3-17
3.8.3 DataCache Block Touch (debt) and
Data Cache Block Touch for Store (dcbtst)..............................................3-17
3.8.4 Data Cache BlockSet
to Zero (dcbz)............................................................3-17
vi PowerPC 604 RISC Microprocessor User'sManual

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3.8.5 DataCache Block Store (dcbst) ....................................................................3-17
3.8.6 Data Cache BlockFlush (dcbf) .....................................................................3-18
3.8.7 DataCache Block Invalidate (dcbi) ........................•.............................•...••..3-18
3
.9 Basic Cache Operations .....................................................................................3-18
3.9.1 Cache Reloads................................................................................................3-18
3.9.2 CacheCast-Out Operation.............................................................................3-18
3.9.3 Cache Block Push Operation .........................................................................3-18
3.9.4 Atomic Memory References..........................................................................3-19
3.9.5 Snoop Response to Bus Operations...............................................................3-19
3.9.6 Cache Reaction to Specific Bus Operations ..................................................3-19
3.9.7 Enveloped High-Priority Cache Block Push Operation ................................ 3-22
3.9.8 Bus Operations Caused by Cache Control Instructions................................. 3-22
3.9.9 CacheControl Instructions ............................................................................3-23
3.10 Cache Actions...................................................................................................•3-23
3.11 Access to Direct-Store Segments............................................................•.....•....3-44
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.5
4.5.1
4.5.2
4.5.2.1
4.5.2.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
4.5.9
4.5.10
4.5.11
4.5.12
Contents
Chapter 4
Exceptions
PowerPC 604 Microprocessor Exceptions...........................................................4-2
Exception Recognition and Priorities ...............................................................•..4-5
Exception Processing...........................................................................................4-6
Enabling and Disabling Exceptions..........................•......................................4-9
Steps for Exception Processing......................................................................4-10
Setting MSR[RI] ............................................................................................4-10
Returning from an Exception Handler...........................................................4-11
Process Switching ..............................................................................................4-11
Exception Definitions ........................................................................................4-12
System Reset Exception (OxOOl00) ...............................................................4-13
Machine Check Exception (Ox00200) .......................................•.••................4-13
Machine Check Exception Enabled (MSR[ME] =
1) ................................4-14
Checkstop State (MSR[ME] =0) ..............................................................4-15
DSI Exception (Ox00300) ..............................................................................4-16
ISi Exception (Ox00400)................................................................................4-16
External Interrupt Exception (Ox00500) ........................................................4-16
Alignment Exception (Ox00600) ...............................•.......................•...........4-17
Program Exception (Ox00700).......................................................................4-17
Floating-Point Unavailable Exception (Ox00800) .........................................4-18
Decrementer Exception (Ox00900) ................................................................4-19
System Call Exception (OxOOCOO) ................................................................4-19
Trace Exception (OxOOD00) ..........................•................................................4-19
Floating-Point Assist Exception (OxOOEOO) ..........................••................••....4-19
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5.1.5
5.1.6
5.1.6.1
5.1.6.2
5.1.6.3
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5.2
5.3
5.4
5.4.1
5.4.1.1
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5.4.2
5.4.3
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5.4.4
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5.4.6
5.4.7
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
viii
CONTENTS
Title
Page
Number
Perfonnance Monitoring Interrupt (OxOOFOO) ...............................................4-20
Instruction Address Breakpoint Exception (Ox01300) ..................................4-20
System Management Interrupt (Ox01400) .....................................................4-20
Power Management ....................................................................................... 4-21
Chapter 5
Memory Management
MMU Overview ...................................................................................................5-2
Memory Addressing ........................................................................................5-4
MMU Organization..........................................................................................5-4
Address Translation Mechanisms....................................................................5-9
Memory Protection Facilities......................................................................... 5-11
Page History Infonnation................................................................................5-12
General
Flow of MMU Address Translation.................................................5-12
Real Addressing Mode and Block Address Translation Selection............ 5-12
Page and Direct-Store Interface Address Translation Selection............... 5-14
Selection of
Page Address Translation.......................................................5-16
Selection of Direct-Store Interface
Address Translation...........................5-16
MMU Exceptions Summary ..........................................................................5-16
MMU Instructions and Register Summary....................................................5-18
TLB Entry Invalidation..................................................................................5-19
Real Addressing Mode .......................................................................................5-20
Block Address Translation.................................................................................5-20
Memory Segment Model ...................................................................................5-20
Page History Recording ................................................................................. 5-21
Referenced Bit ...........................................................................................5-22
Changed Bit .............,.................................................................................5-22
Scenarios
for Referenced and Changed Bit Recording ............................. 5-23
Page Memory Protection ...............................................................................5-24
TLB Description ............................................................................................5-24
TLB Organization......................................................................................5-24
TLB Invalidation .......................................................................................5-26
Page Address Translation Summary ..............................................................5-27
Page Table Search Operation.........................................................................5-29
Page Table Updates .......................................................................................5-33
Segment Register
Updates .............................................................................5-34
Direct-Store Interface
Address Translation ....................................................... 5-35
Direct-Store Interface Accesses..................................................................... 5-35
Direct-Store Segment Protection ................................................................... 5-35
Instructions Not Supported in Direct-Store Segments ...................................5-36
Instructions
with No Effect in Direct-Store Segments ..................................5-36
Direct-Store Segment Translation
Summary Flow ........................................5-36
PowerPC 604 RISC Microprocessor User's Manual

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6.4.1
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6.4.7.3
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6.4.7.5
Contents
CONTENTS
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Chapter 6
Instruction Timing
Page
Number
Tenninology and Conventions.....••...........•.....•...............................................••.•. 6-1
Instruction Timing Overview.........................................................................••.•.. 6-3
Pipeline Structures ................•.......................................................................... 6-5
Description ofPipeline Stages.......•...................•.........................................6-7
Fetch Stage ..............................................................................................6-8
Decode Stage ...........................................................................................6-9
Dispatch Stage .........................................................................................6-9
Execute Stage ........................................................................................6-10
Complete Stage........................•...................................................•......... 6-11
Write-Back Stage......•............................................................................6-12
Memory Perfonnance Considerations ...............................................................6-12
MMU Overview..................••.....•.........••........•..••.........•........••..............•••..•... 6-13
Cache Overview....................................•...................................••................... 6-13
Bus Interface Overview ..........................................................................•......6-15
Memory Operations .......................................................................................6-15
Write-Back Mode •.........................................................................•.........••6-15
Write-Through Mode....•..•..................••.••...........•..•..................•...............• 6-16
Cache-Inhibited Mode .........•.....................................................................6-16
Timing Considerations......................................................................................•6-17
General Instruction Flow ...............................................................................6-17
Instruction Fetch Timing ...............................................................................6-18
Cache Hit Timing Exaillple ......................................................................•6-18
Cache Miss Timing Example............................................................•........6-22
Cache Arbitration.........................................................................•.............•... 6-24
Branch Prediction ...............................•...............•.................................••.......6-24
Branch Timing Examples ..........................................................................6-25
Timing Example-Branch Timing for a
BT AC Hit.........••..••........•.....• 6-25
Timing Example-Branch with BT AC Miss/Decode Correction...•..... 6-26
Timing Example-Branch with
BT AC Miss/Dispatch Correction....... 6-28
Timing Example-Branch with BT AC Miss/Execute Correction ........ 6-28
Speculative Execution....................................................................................6-29
Instruction Dispatch
and Completion Considerations ................................... 6-30
Rename Register Operation....................................................................... 6-31
Execution Unit Considerations ..................................................................6-33
Instruction Serialization................................................................................. 6-33
Dispatch Serialization Mode.••...........................................•.......•......••.....•• 6-34
Execution Serialization Mode..................•..........•......................................6-34
Postdispatch Serialization Mode................................................................ 6-34
Serialization of String/Multiple Instructions .............................................
6-35
Serialization ofInput/Output ..................................................................... 6-35
ix

Paragraph
Number
CONTENTS
Title
Page
Number
6.5 Execution Unit Timings..................................................................................... 6-35
6.5.1 Branch Unit Instruction Timings ...................................................................6-35
6.5.2 Integer Unit Instruction Timings ................................................................... 6-35
6.5.3 Floating-Point Unit Instruction Timings........................................................ 6-37
6.5.4 Load/Store Unit Instruction Timings............................................................. 6-39
6.5.5 isync, rfi, and
sc Instruction Timings............................................................6-41
6.6 Instruction Scheduling Guidelines..................................................................... 6-42
6.6.1 Instruction Dispatch Rules.............................................................................6-42
6.6.2 Additional Programming Tips for the PowerPC 604 Processor.................... 6-43
6.7 Instruction Latency Summary............................................................................6-45
7.1
7.2
7.2.1
7.2.1.1
7.2.1.2
7.2.1.3
7.2.1.3.1
7.2.1.3.2
7.2.2
7.2.2.1
7.2.2.1.1
7.2.2.1.2
7.2.2.2
7.2.2.2.1
7.2.2.2.2
7.2.3
7.2.3.1
7.2.3.1.1
7.2.3.1.2
7.2.3.1.3
7.2.3.1.4
7.2.3.2
7.2.3.2.1
7.2.3.2.2
7.2.3.3
7.2.4
7.2.4.1
7.2.4.1.1
7.2.4.1.2
x
Chapter 7
Signal Descriptions
Signal Configuration............................................................................................7-2
Signal Descriptions..............................................................................................7-3
Address Bus Arbitration Signals......................................................................7-3
Bus Request (BR)--Output......................................................................... 7-4
Bus Grant
(BG)-lnput ...............................................................................7-4
Address Bus Busy (ABB) ............................................................................7-5
Address Bus Busy (ABB)--Output.........................................................7-5
Address Bus Busy
(ABB)-Input ...........................................................7-5
Address Transfer Start Signals ........................................................................7-6
Transfer Start (TS).......................................................................................7-6
Transfer Start (TS)--Output.................................................................... 7-6
Transfer Start
(TS)-Input ......................................................................7-6
Extended Address Transfer Start (XATS) ...................................................7-6
Extended Address Transfer Start (XATS)--Output................................7-6
Extended Address Transfer Start (XA
TS)-Input ..................................7-7
Address Transfer Signals.................................................................................7-7
Address Bus (AO-A31)................................................................................ 7-7
Address Bus
(AO-A31}-0utput (Memory Operations) ........................7-7
Address Bus
(AO-A31)-lnput (Memory Operations) ........................... 7-7
Address Bus
(AO-A31}-0utput (Direct-Store Operations) .................. 7-8
Address Bus
(AO-A31)-lnput (Direct-Store Operations) .....................7-8
Address Bus Parity (APO-AP3)...................................................................7-8
Address Bus Parity (APO-AP3)--0utput ...............................................7-8
Address Bus Parity (APO-AP3)-Input..................................................7-9
Address Parity Error
(APE}-Output.. ........................................................7-9
Address Transfer Attribute Signals..................................................................7-9
Transfer Type (TTO-TT4) .........................................................................7-10
Transfer Type (TTO-TT4}-0utput......................................................7-10
Transfer Type (TTO-TT4)-Input.........................................................7-10
PowerPC 604 RISC Microprocessor User's Manual

Paragraph
Number
7.2.4.2
7.2.4.2.1
7.2.4.2.2
7.2.4.3
7.2.4.3.1
7.2.4.3.2
7.2.4.4
7.2.4.5
7.2.4.6
7.2.4.7
7.2.4.7.1
7.2.4.7.2
7.2.4.8
7.2.5
7.2.5.1
7.2.5.2
7.2.5.2.1
7.2.5.2.2
7.2.5.3
7.2.5.3.1
7.2.5.3.2
7.2.6
7.2.6.1
7.2.6.2
7.2.6.3
7.2.6.3.1
7.2.6.3.2
7.2.7
7.2.7.1
7.2.7.1.1
7.2.7.1.2
7.2.7.2
7.2.7.2.1
7.2.7.2.2
7.2.7.3
7.2.7.4
7.2.8
7.2.8.1
7.2.8.2
7.2.8.3
7.2.9
7.2.9.1
7.2.9.2
Contents
CONTENTS
Title
Page
Number
Transfer Size (TSIZO--TSIZ2) ...................................................................7-11
Transfer Size (TSIZO--TSIZ2)-0utput................................................ 7-12
Transfer Size (TSIZO--TSIZ2}-Input...................................................7-12
Transfer Burst (TBST)...............................................................................7-13
Transfer Burst
(TBST)-Output. ...........................................................7-13
Transfer Burst (TBST}-lnput ..............................................................7-13
Transfer Code (TCO--TC2)-0utput .........................................................7-13
Cache Inhibit (Cl)--Output.......................................................................7-14
Write-Through
(WT)-Output ..................................................................7-15
Global (GBL).............................................................................................7-15
Global
(GBL)-Output ..........................................................................7-15
Global
(GBL}-lnput ............................................................................7-15
Cache Set Element
(CSEO-CSEl)-Output .............................................7-15
Address TransferTermination Signals ..........................................................7-16
Address Acknowledge (AACK}-Input. ...................................................7-16
Address Retry (ARTRY) ...........................................................................7-16
Address Retry
(ARTRY)-Output ........................................................7-16
Address Retry (ARTRY}-lnput ...........................................................7-17
Shared (SHD)............................................................................................. 7-17
Shared (SHD)-Output .........................................................................7-17
Shared (SHD}-Input ............................................................................7-18
DataBus Arbitration Signals .........................................................................7-18
DataBus Grant
(DBG}-Input ..................................................................7-18
DataBus Write Only (DBWO}-lnput .....................................................7-18
DataBus Busy (DBB) ...............................................................................7-19
DataBus Busy (DBB)-Output ............................................................7-19
DataBus Busy
(DBB}-Input ...............................................................7-19
Data Transfer Signals.....................................................................................7-20
DataBus (DHO--DH31, DLO--DL31).........................................................7-20
DataBus (DHO--DH31, DLO--DL31)-0utput......................................7-20
Data Bus (DHO--DH31, DLO--DL31}-lnput........................................7-21
DataBus Parity
(DPO--DP7) ......................................................................7-21
DataBus Parity (DPO--DP7)-0utput................................................... 7-21
DataBus Parity (DPO--DP7}-Input......................................................7-21
Data Parity Error
(DPE)-Output .............................................................7-22
DataBus Disable
(DBDIS}-lnput ...........................................................7-22
DataTransfer Termination Signals................................................................7-22
Transfer Acknowledge (T
A}-lnput .........................................................7-23
Data Retry (DRTRY}--Input ....................................................................7-23
Transfer Error Acknowledge
(TEA}-Input .............................................7-24
System Interrupt, Checkstop, and Reset Signals ...........................................7-24
Interrupt (INT)--Input...............................................................................7-25
System Management Interrupt (SMI}-Input ...........................................7-25
xi

Paragraph
Number
7.2.9.3
7.2.9.4
7.2.9.5
7.2.9.6
7.2.9.6.l
7.2.9.6.2
7.2.10
7.2.10.1
7.2.10.2
7.2.10.3
7.2.10.4
7.2.10.5
7.2.11
7.2.12
7.2.12.1
7.2.12.2
7.2.12.3
7.2.12.4
8.1
8.1.1
8.1.2
8.1.3
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.3.2.1
8.3.2.2
8.3.2.2.1
8.3.2.2.2
8.3.2.3
8.3.2.4
8.3.2.4.1
8.3.2.5
8.3.3
8.4
8.4.1
xii
CONTENTS
Page
Number
Tltle
Machine Check Interrupt (MCP}-lnput.................................................... 7-25
Checkstop Input(CKSTP_IN}-lnput....................................................... 7-26
Checkstop Output (CKSTP_OUT)-Output............................................. 7-26
Reset Signals....................................•.....•..••...............................................7-27
Hard Reset (HRESET}-Input..............................................................7-27
Soft
Reset (SRESET}-lnput................................................................ 7-27
Processor Configuration Signals....................................................................7-28
Timebase Enable (TBEN}-lnput.............................................................
7-28
Reservation (RSRV}-Output...................................................................7-28
L2 Intervention (L2_1NT}-Input...............•.............................................7-28
Run (RUN}-lnput....................................................................................7-29
Halted (HALTED)---Output..................................................................... 7-29
COP/Scan Interface..................................................................•.....................7-29
Clock Signals.................................................................................................7-30
System Clock (SYSCLK}-lnput..............................................................7-30
Test Clock (CLK_OUT)-Output............................................................. 7-31
Analog VDD (A VDD}-lnput.........................................•........................ 7-31
PLL Configuration (PLL_CFGO-PLL_CFG3}-Input.•.•.•......................• 7-31
Chapter 8
System Interface Operation
PowerPC 604 Microprocessor System Interface Overview.........•....................... 8-1
Operation ofthe Instruction and Data Caches ................................................. 8-2
Operation of the System Interface.......................•••.•............••......................... 8-4
Direct-Store Accesses ...................................................................................... 8-5
Memory Access Protocol.....................................................................................8-6
Arbitration Signals...........................................................................................
8- 7
Address Pipelining and Split-Bus Transactions............................................... 8-9
Address Bus Tenure...........................................................................................8-10
Address Bus Arbitration .........................••.•...................................................8-10
Address Transfer............................................................................................8-12
Address Bus Parity ............•.••••........................................••........................ 8-13
Address Transfer Attribute Signals ........................................................... 8-13
Transfer Type (TTO-TT4) Signals ........................................................ 8-13
Transfer Size (TSIZO-TSIZ2) Signals................................................... 8-13
Burst Ordering During Data Transfers ...................................................... 8-14
Effect ofAlignment
in Data Transfers ...................................................... 8-14
Alignment of External Control Instructions ..........................................
8-16
Transfer Code (TCO-TC2) Signals............................................................8-17
Address Transfer Termination......................................................................8-18
Data
Bus Tenure ................................................................................................8-20
Data Bus Arbitration......................................................................................8-20
PowerPC 604 Rl~IC Microproceasor User'• Manual

Paragraph
Number
8.4.1.1
8.4.1.2
8.4.2
8.4.3
8.4.4
8.4.4.1
8.4.4.2
8.4.5
8.5
8.6
8.6.1
8.6.1.1
8.6.1.2
8.6.2
8.6.2.1
8.6.2.2
8.6.3
8.6.4
8.7
8.7.1
8.7.1.1
8.7.1.2
8.7.1.3
8.8
8.8.1
8.8.2
8.8.3
8.8.4
8.9
8.9.1
8.10
8.10.1
8.11
9.1
9.1.1
9.1.1.1
9.1.1.1.1
9.1.1.1.2
Contents
CONTENTS
Title
Page
Number
Effect of ARTRY Assertion on Data Transfer and Arbitration................. 8-21
Using the DBB Signal ...............................................................................8-22
Data
Bus Write Only ...................................................................................... 8-23
Data Transfer ................................................................................................. 8-23
Data Transfer Termination.............................................................................8-24
Normal Single-Beat Termination .............................................................. 8-25
Data Transfer Termination Due to a Bus Error ......................................... 8-28
Memory Coherency-MESIProtocol ...........................................................8-29
Timing Examples ...............................................................................................8-32
Direct-Store Operation..............••.•.....................................................................
8-38
Direct-Store Transactions ..............................................................................8-40
Store Operations ........................................................................................
8-41
Load Operations......................................................................................... 8-41
Direct-Store Transaction Protocol Details ..................................................... 8-42
Packet 0...................................................................................................... 8-43
Packet 1...................................................................................................... 8-44
1/0 Reply Operations..................................................................................... 8-44
Direct-Store Operation
Timing ......................................................................8-46
Optional
Bus Configuration............................................................................... 8-48
Fast-L2/Data Streaming Mode ....................................................................... 8-48
Fast-L2/DataStreaming Mode Design Considerations ............................. 8-49
Data Streaming in the Fast-L2/Data Streaming Mode .............................. 8-49
Data Valid Window in the Fast-L2/Data Streaming Mode ....................... 8-50
Interrupt, Checkstop, and Reset Signals ............................................................ 8-50
External Interrupts .........................................................................................8-50
Checkstops.....................................................................................................
8-51
Reset Inputs.................................................................................................... 8-51
PowerPC 604 Microprocessor Configuration during HRESET .................... 8-51
Processor State Signals ......................................................................................8-52
Support for the lwarx/stwcx. Instruction Pair............................................... 8-52
IEEE 1149.1-Compliant Interface .....................................................................8-52
IEEE
1149.1 Interface Description ................................................................ 8~52
Using Data Bus Write Only ............................................................................... 8-53
Chapter 9
Performance Monitor
Performance Monitor Interrupt............................................................................ 9-2
Special-Purpose Registers Used by Performance Monitor.............................. 9-2
Performance Monitor Counter Registers (PMCl and PMC2) ..................... 9-3
PMCl Selectable Events ......................................................................... 9-3
PMC2 Selectable Events ......................................................................... 9-5
xiii

Paragraph
Number
9.1.1.2
9.1.1.2.1
9.1.1.2.2
9.1.1.2.3
9.1.1.3
9.1.2
9.1.2.1
9.1.2.2
9.1.2.2.1
9.1.2.2.2
9.1.2.2.3
9.1.2.3
CONTENTS
Tltle
Page
Number
SIA and SDA Registers ...............................................................................9-6
Sampled Instruction Address Register (SIA) .......................................... 9-6
Sampled Data Address Register (SDA)...................................................9-6
Updating SIA and SDA :...........................................................................9-6
Monitor Mode Control Register 0
(MMCRO) ............................................. 9-6
Event Counting ................................................................................................ 9-8
Event Selection .............................................................................................9-9
Threshold Events ........................................................................................ 9-10
Threshold Conditions ............................................................................9-10
Lateral L2 Cache Intervention...............................................................9-10
Warnings.................................................................................................9-11
Nonthreshold Events..................................................................................9-11
Appendix A
PowerPC Instruction Set Listings
A.1 Instructions Sorted by Mnemonic............•..........•............................................... A-1
A.2 Instructions Sorted by Opcode.......................................................................... A-10
A.3 Instructions Grouped by Functional Categories ............................................... A-18
A.4 Instructions Sorted by Form................................••.......................•.................... A-28
A.5 Instruction Set Legend...................................................................................... A-39
Appendix B
Invalid Instruction Forms
B.1 Invalid Forms Excluding Reserved Fields........................................................... B-1
B.2 Invalid Forms with Reserved Fields (Bit 31 Exclusive)......................................B-2
B.3 Invalid Form with Only Bit 31 Set ......................................................................B-5
B.4 Invalid Forms from Invalid BO Field Encodings ............................................•...B-6
Glossary of Terms and Abbreviations
Index
xiv
PowerPC 604 RISC Microprocessor User's Manual

Figure
Number
1-1
1-2
1-3
14
1-5
1-6
1-7
2-1
2-2
2-3
3-1
3-2
3-3
34
3-5
3-6
4-1
4-2
4-3
5-1
5-2
5-3
54
5-5
5-6
5-7
5-8
5-9
5-10
5-11
6-1
6-2
6-3
64
6-5
6-6
6-7
Illustrations
ILLUSTRATIONS
Title
Page
Number
Block Diagram ....................................................................................................... 1-3
Block Diagram-Internal Data Paths ..................................................................... 1-7
Cache Unit Organization...................................................................................... 1-14
System Interface................................................................................................... 1-15
PowerPC 604 Microprocessor Signal Groups ...................................................... 1-18
Programming Model-PowerPC 604 Microprocessor Registers ........................ 1-21
Pipeline Diagram .................................................................................................. 1-33
Programming Model-PowerPC 604 Microprocessor Registers .......................... 2-3
Instruction Address Breakpoint Register ............................................................... 2-9
Processor Identification Register ........................................................................... 2-9
Cache Organization................................................................................................3-2
Cache Integration ................................................................................................... 3-3
Bus Interface Unit and MMU ................................................................................. 3-6
Memory Queue Organization.................................................................................3-7
MESI States..........................................................................................................3-12
MESI Cache Coherency Protocol-State Diagram (WIM = 001) ....................... 3-14
Machine Status Save/Restore Register 0................................................................ 4-6
Machine Status Save/Restore Register 1................................................................ 4-6
Machine State Register (MSR) .............................................................................. 4- 7
MMU Conceptual Block Diagram-32-BitImplementations ............................... 5-6
PowerPC 604 Microprocessor IMMU Block Diagram .......................................... 5-7
PowerPC 604 Microprocessor DMMU Block Diagram ........................................5-8
Address Translation Types ...................................................................................5-10
General Flow of Address Translation (Real Addressing Mode and Block) ........ 5-13
General Flow of Page and Direct-Store Interface Address Translation............... 5-15
Segment Register and DTLB Organization ......................................................... 5-25
Page Address Translation Flow-TLB Hit .......................................................... 5-28
Primary Page Table Search .................................................................................. 5-31
Secondary Page Table Search Flow .....................................................................5-32
Direct-Store
Segment Translation Flow ............................................................... 5-37
PowerPC 604 Microprocessor Block Diagram Showing Data Paths ..................... 64
GPR Reservation Stations and Result Buses .......................................................... 6-5
Pipeline Diagram .................................................................................................... 6-6
PowerPC 604 Microprocessor Pipeline Stages ...................................................... 6- 7
Instruction
Fetch Address Generation.................................................................... 6-8
Data Caches and Memory Queues ....................................................................... 6-14
Instruction Timing--Cache Hit ............................................................................ 6-19
xv

Figure
Number
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
7-1
7-2
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
8-20
8-21
8-22
8-23
8-24
8-25
8-26
8-27
8-28
8-29
xvi
ILLUSTRATIONS
Title Page
Number
Instruction Timing-Instruction Cache Miss (BT AC Hit) .................................. 6-22
Instruction Timing-Branch with BT AC Hit ...................................................... 6-25
Instruction Timing-Branch with BT AC Miss/Decode Correction .................... 6-27
Instruction Timing-Branch with BT AC Miss/Dispatch Correction .................. 6-28
Instruction Timing-Branch with BT AC Miss/Execute Correction.................... 6-29
GPR Rename Register................................................................................••........ 6-32
SCIU Block Diagram ........................................................................................... 6-36
MCIU Block Diagram.......................................................................................... 6-37
FPU Block Diagram ............................................................................................. 6-38
LSU Block Diagram.............................................................................................6-40
Store Queue Structure ..........................................................................................
6-41
PowerPC 604 Microprocessor Signal Groups ........................................................ 7-3
IEEE 1149.1-Compliant Boundary Scan Interface .............................................. 7-30
PowerPC 604 Microprocessor Block Diagram ...................................................... 8-3
Timing Diagram Legend ........................................................................................ 8-5
Overlapping Tenures on the PowerPC 604 Microprocessor Bus for a Single-Beat
Transfer..•.......................................................................•...................................
8-6
Address Bus Arbitration.............................•.........................................•...............8-10
Address Bus Arbitration Showing Bus Parking ................................................... 8-11
Address Bus Transfer..•........................................................................................ 8-12
Snooped
Address Cycle with ARTRY ................................................................. 8-19
Data Bus Arbitration ............................................................................................8-20
Qualified
DBG Generation Following ARTRY ...................................................8-22
Normal Single-Beat Read Termination................................................................ 8-25
Normal Single-Beat Write Termination ............................................................... 8-26
Normal Burst Transaction .................................................................................... 8-26
Termination with DRTRY •..................................................................................8-27
Read Burst with TA Wait States and DRTRY ..................................................... 8-28
MESI Cache Coherency Protocol-State Diagram (WIM = 001) ....................... 8-31
Fastest Single-Beat Reads .................................................................................... 8-32
Fastest Single-Beat Writes ...................................................................................
8-33
Single-Beat Reads Showing Data-Delay Controls............................................... 8-34
Single-Beat Writes
Showing Data Delay Controls .............................................. 8-35
Burst Transfers with Data Delay Controls ...................................................•....... 8-36
Use ofTransfer Error Acknowledge (TEA) ..............................................•.•........8-37
Direct-Store Tenures ........•................................................................................... 8-40
Direct-Store Operation-Packet 0 ........................................................................ 8-43
Direct-Store Operation-Packet 1........................................................................ 8-44
1/0 Reply Operation............................................................................................. 8-45
Direct-Store Interface Load Access Example ...................................................... 8-47
Direct-Store Interface Store Access Example ...................................................... 8-48
Data Transfer in Fast-L2/Data Streaming Mode ................................................... 8-50
Data
Bus Write Only Transaction ......................................................................... 8-53
PowerPC 604 RISC Microprocessor User's Manual

Table
Number
ii
iii
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-31
Tables
TABLES
Title
Page
Number
Acronyms and Abbreviated Terms ..........................•.............................................. xxv
Terminology Conventions .................................................................................. xx viii
Instruction Field Conventions ••..........•...............................................................
xx viii
Exception Classifications .........••..............•..........•................................................ 1-30
Overview of Exceptions and Conditions.............................................................. 1-30
MSR[PM] Bit •.........................................................................................•.............. 2-6
Instruction Address Breakpoint Register Bit Settings............................................ 2-9
Hardware Implementation-Dependent Register 0 Bit Settings ............................ 2-10
MMCRO Bit Settings•........................................................................................... 2-12
Selectable Events-PMCl ................................................................................... 2-14
Selectable Events-PMC2 ................................................................................... 2-15
Floating-Point Operand Data Type Behavior.............................................•......... 2-18
Floating-Point Result Data Type Behavior .......................................•...........•...... 2-19
Integer Arithmetic Instructions....•........................................................................ 2-26
Integer Compare Instructions ......................•..................•..................................... 2-28
Integer Logical Instructions.............................................................•.................... 2-28
Integer Rotate Instructions .......••.•••...................................................................... 2-29
Integer Shift Instructions ...............•................................................•...•................. 2-30
Floating-Point Arithmetic Instructions................................................................. 2-30
Floating-Point Multiply-Add Instructions ............................................................ 2-31
Floating-Point Rounding and Conversion Instructions .........................•.............. 2-32
Floating-Point Compare Instructions .............................•.•..................••............... 2-32
Floating-Point Status and Control Register Instructions .......................•.............• 2-32
Floating-Point Move Instructions......................................................................... 2-33
Integer Load Instructions............••.....•...•......•.•...................•••............................... 2-35
Integer Store Instructions ..................................................................................... 2-37
Integer Load and Store with Byte Reverse Instructions••..................................... 2-38
Integer Load and Store Multiple Instructions....................................................... 2-39
Integer Load and Store String Instructions........................................................... 2-39
Floating-Point Load Instructions.......................................................................... 2-41
Floating-Point Store Instructions.......................................................................... 2-41
Store Floating-Point Single Behavior................................................................... 2-42
Store Floating-Point Double Behavior................................................................. 2-43
Branch Instructions.••..............................................•....................••....................... 2-44
Condition Register Logical Instructions..•............................•............................... 2-45
Trap Instructions....•.............................................................................................. 2-45
xvii