IBM PowerPC 604 User manual

Overview
PowerPC 604 Processor Programming Model -
Cache and Bus Interface Unit Operation
Exceptions
Memory Management
Instruction Timing
Signal Descriptions
System Interface Operation
Performance Monitor
PowerPC Instruction Set Listings -
Invalid Instruction Forms -
Glossary of Terms and Abbreviations i!el
Index 111111

Overview
-PowerPC 604 Processor Programming Model
Cache and Bus Interface Unit Operation
-Exceptions
Memory Management
Instruction Timing
Signal Descriptions
System Interface Operation
Performance Monitor
-PowerPC Instruction Set Listings
B Invalid Instruction Forms
-Glossary of Terms and Abbreviations
Index

MPR604UMU-01 MPC604UM/AD
11/94
PowerPC™ 604
RISC Microprocessor User's Manual
IBM Microelectronics

e Motorola Inc. 1994
Portions hereof e International Business Machines corp. 1991-1994. All rights reserved.
This document oontalns lnfonnatlon on a now product under development Motorola reserves tho right to change or discontinue this proooct without
notice. Information In this document Is provided solely to enable system and software Implementers to use PoworPC microprocessors. There are no
express or Implied copyright licenses granted hereunder to design or fabricate PowerPC Integrated circuits or integrated clrcubs based on the Information
In this document.
The PoworPC 604 microprocessor embodies the Intellectual property of I BM and of Motorola. However. neither party assumes any rosponsl:llllty or
llabillty as to any aspects of tho performance, operation, or other attributes of the microprocessor as malketed by tho other party. Neither party Is lo be
considered an agent or representative of tho other party, and neither has granted any right or authority to tho other to assume or create any express or
Implied Obligations on bs bohatt. Information such as data sheets, as well as sales terms and conditions such as prices, schaooles, and support, for tho
microprocessor may vary as between IBM and Motorola. Accordingly, customers wishing to leam more Information about tho products as marketed by a
given party should oontact that party.
Both IBM and Motorola reserve the right to modtty this manual and/or any of the products as described heroin without further notice. Nothing in !his
manual, nor In any ol tho errata sheets, data sheets, and other supporting documentation, shall be Interpreted as conveying an express or Implied
warranty, representation, or guarantee regarding the suitability ol the products for any particular purpose. The parties do not assume any llablllty or
Obligation for damages olany kind arising out olthe application or use ol these materials. Any warranty or other Obligations as to the products described
herein shall be undertaken solely by Iha marketing party to the customer, undera separate sale agreement between tho malkoting party and tho customer.
In tho absence ol such an agreomon~ no llablllty Is assumed by tho malketing party for any damages, actual or otherwise.
"Typical" parameters can and do vary In dlllerent applications. All operating parameters, lncuding "Typlcals," must be validated for each customer
application by customer's technical experts. Neither IBM nor Motorola oonvey any license undertheir respective Intellectual property rights nor tho rights
of others. Tho prooocts described In this manual are not designed, Intended, or authorized for use as components In systems Intended for surgical Implant
Into tho bocly, or other applications Intended to support or sustain Itta, orforanyother application In which tho faluro cl the proooct could create a situation
where personal Injury or death may occur. Should customer purchase or use the products forany such unintended or unauthorized application, customer
shall lndemntty and hold IBM and Motorola and their respective officers, employees, subsidiaries, affiliates, and dlstrllutors harmless against all claims,
costs, damages, and expenses, and reasonable attorney lees arising out of, directly or lndlrectiy, any claim of personal Injury or death associated with
such unintended or unauthorized use, even tt such claim alleges that Motorola or IBM was negligent regarding tho design or manufacture of the part.
Motorola and @ are registered trademalks of Motorola. Inc. Motorola, Inc. Is an E<1Jal Opportunity/Affirmative Action Employer.
IBM Is a registered trademark, and IBM MD-oelectronics Is a trademark of IBM Corp.
PowerPC, PowerPC Architecture, POWER Architecture, PowerPC 601. PowerPC 603, PowerPC 604, and /ltlllVK are trademalks of IBM Corp.
used by Motorola under license from IBM Corp.

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Contents
CONTENTS
Tltle
About This Book
Page
Number
Audience .............................................................................................................xxii
Organization........................................................................................................xxii
Suggested
Reading .............................................................................................xxiii
Conventions .......................................................................................................
xxiv
Acronyms and Abbreviations .............................................................................. xxv
Tenninology Conventions •.....•.•••..................•••••••.•..•..............•••••..•.•...•..•.•..•.. xxviii
Chapter 1
Overview
Overview .............................................................................................................. 1-1
PowerPC 604 Microprocessor Features ••••...............•...•.••.•••..•.....•...•••..........•.• 1-2
PowerPC 604 Microprocessor Hardware Implementation ............•......•••.•••.••..•.. 1-7
Instruction Flow ........................................................................ .' ...................... 1-8
Fetch Unit .................................................................................................... 1-8
Decode/Dispatch Unit .................................................................................. 1-9
Branch Processing Unit (BPU) .................................................................... 1-9
Completion Unit .......................................................................................... 1-9
Rename Buffers ......................................................................................... 1-10
Execution Units .............................................................................................. 1-10
Integer Units (IUs) ..................................................................................... 1-10
Floating-Point Unit (FPU) ......................................................................... 1-11
Load/Store Unit (LSU) .............................................................................. 1-11
Memory Management Units (MMUs) .•••••••....•..•.••..................••.••.•............... 1-12
Cache Implementation ..........•..•.••••••.••••••••••••••••••• ,••.......•.....................•......... 1-12
Instruction Cache ....................................................................................... 1-13
Data Cache •••.••.................••••••••.••••••..••..•.•.......................••...•••••••..••••••••••••• 1-13
System Interface/Bus Interface Unit (BIU) .........•.••..•••••••......•••.•...•..•.••••••.••. 1-14
Memory Accesses ..•..••••••..•............•..........•••..•••••••.•••••••••••••••••••••••••••••••••••• 1-16
Signals........................................................................................................ 1-16
Signal Coofiguration.................................................................................. 1-17
Clocking......................................................................................................... 1-18
PowerPC 604 Microprocessor Execution Model............................................... 1-19
iii

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1.3.3.1
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1.5
2.1
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2.2.1
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2.3.1
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iv
CONTENTS
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Page
Number
Levels of the PowerPC Architecture .............................................................. 1-19
Registers and Programming Model ................................................................ 1-20
General-Purpose Registers (GPRs) ............................................................ 1-22
Floating-Point Registers (FPRs) ................................................................ 1-22
Condition Register (CR) ••.•.•.•.............•..........•..............................••....••....• 1-22
Floating-Point Status and Control Register (FPSCR) ..................••.•.•....... 1-23
Machine State Register (MSR) ...........•••......••..............................•.•.••........ 1-23
Segment Registers (SRs) ••••.•..............•••........•..........................•..•.••...•...... 1-23
Special-Purpose Registers (SPRs) ••.•.....................................••..•............... 1-23
User-Level SPRs •••..•.....•......••.....•••...............................••••...•.•............... 1-23
Supervisor-Level SPRs ....•••••....••••.....................................••••••.............. 1-23
Instruction Set and Addressing Modes .......................................................... 1-25
PowerPC Instruction Set and Addressing Modles ....................•....••.••........ 1-25
Instruction Set ........................................................................................ 1-25
Calculating Effective Addresses ............................................................ 1-27
Exception Model .................•.•.••......................•......•...........•.....•.••••.••............. 1-28
Instruction Timing ......................................................................................... 1-33
Power Management-Nap Mode ...................................................................... 1-35
Performance Monitor •........••••.•...........................•............................••••••••.......... 1-35
Chapter 2
PowerPC 604
Processor Programming Model
The PowerPC 604 Processor Register Set ........................................................... 2-1
Register Set ...................................................................................................... 2-2
604-Specific Registers ..................................................................................... 2-8
Instruction Address Breakpoint Register (IABR) ....................•.•.............•.•. 2-8
Processor Identification Register (PIR) ....................................................... 2-9
Hardware Implementation-Dependent Register 0 .................••.................• 2-10
Performance Monitor Registers ......•••••.••..•••.............•.••••.••.............•...•..•... 2-11
Monitor Mode Control Register 0 (MMCRO) ....................................... 2-11
Performance Monitor Counter Registers (PMCl and PMC2) ..........•••.• 2-13
Sampled Instruction Address Register (SIA) ............•.•.••••..................•. 2-15
Sampled Data Address Register (SDA) ................................................. 2-16
Operand Conventions ......................................................................................... 2-16
Floating-Point Execution Models-UISA ............•••••••.....................•••.......... 2-16
Da~ Organization in Memory and Data Transfers ..•••••••••••.•.••............•••••..... 2-17
Alignment and Misaligned Accesses .......................•..••••••••.•................••••..... 2-17
Floating-Point Operand ...........••••.••.............................•.•••••••.••••..................... 2-17
Effect of Operand Placement on Performance •••..............•..••••••...........••••.•••. 2-19
Instruction Set Summary .................................................................................... 2-19
Classes of Instructions ................................................................................... 2-21
Definition of Boundedly Undefined .......................................................... 2-21
PowerPC 604 RISC Microprocessor User'sManual

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2.3.4.4.3
2.3.4.4.4
2.3.4.5
2.3.4.6
2.3.4.6.1
Contents
CONTENTS
Title
Page
Number
Defined Instruction Class .......................................................................... 2-21
Illegal Instruction Class ....................................................................•........ 2-22
Reserved Instruction Class .......................................................................• 2-23
Addressing Modes ......................................................................................... 2-23
Memory Addressing .................................................................................. 2-23
Memory Operands ..........•......................•...................•............................... 2-23
Effective Address Calculation ...................................................................2-24
Synchronization ...........................•.............................................................2-24
Context Synchronization .......................................................................2-24
Execution Synchronization.................................................................... 2-25
Instruction-Related Exceptions.............................................................. 2-25
Instruction Set Overview ............................................................................... 2-26
PowerPC UISA Instructions .......................................................................... 2-26
Integer Instructions .................................................................................... 2-26
Integer Arithmetic Instructions.............................................................. 2-26
Integer Compare Instructions ................................................................ 2-28
Integer Logical Instructions................................................................... 2-28
Integer Rotate and Shift Instructions..•.................................................. 2-29
Floating-Point Instructions ........................................................................2-30
Floating-Point Arithmetic Instructions.................................................. 2-30
Floating-Point Multiply-Add Instructions............................................. 2-31
Floating-Point Rounding and Conversion Instructions ......................... 2-31
Floating-Point Compare Instructions..................................................•.. 2-32
Floating-Point Status and Control Register Instructions ....................... 2-32
Floating-Point Move Instructions.......................................................... 2-33
Load and Store Instructions....................................................................... 2-33
Self-Modifying Code............................................................................. 2-34
Integer Load and Store Address Generation.......................................... 2-35
Register Indirect Integer Load Instructions ........................................... 2-35
Integer Store Instructions....................................................................... 2-36
Integer Load and Store with Byte Reverse Instructions........................ 2-37
Integer Load and Store Multiple Instructions........................................ 2-38
Integer Load and Store String Instructions............................................ 2-39
Floating-Point Load and Store Address Generation .............................. 240
Floating-Point Store Instructions........................................................... 2-41
Branch and Flow Control Instructions....................................................... 2-43
Branch Instruction Address Calculation................................................ 2-44
Branch Instructions................................................................................2-44
Condition Register Logical Instructions................................................ 2-45
Trap Instructions.................................................................................... 2-45
System Link:age Instruction-VISA..........................................................2-46
Processor Control Instructions-VISA ..................................................... 2-46
Move to/from Condition Register Instructions...................................... 2-46
v

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Number
Move to/from Special-Purpose Register Instructions (UISA)............... 2-47
Memory Synchronization Instructions-VISA......................................... 2-47
PowerPC VEA Instructions ...........................................................................2-48
Processor Control Instructions-VEA ......................................................2-48
Memory Synchronization Instructions-VEA ..........................................2-49
Memory Control Instructions-VEA ........................................................2-50
User-Level Cache Instructions-VEA..................................................2-50
Optional External Control Instructions...................................................... 2-52
PowerPC OEA Instructions ...........................................................................2-52
System Linkage Instructions-DEA .........................................................2-52
Processor Control Instructions-OBA ......................................................2-52
Memory Control Instructions-DEA ........................................................2-54
Supervisor-Level Cache Management Instruction-(OEA) .................2-54
Segment Register Manipulation Instructions (OEA).............................2-55
Translation Lookaside BufferManagement lnstructions-(OEA) ....... 2-55
Recommended Simplified Mnemonics..........................................................2-57
Chapter 3
Cache and Bus Interface UnitOperation
3.1 Data Cache Organization.....................................................................................3-3
3.2 Instruction Cache Organization ...........................................................................3-4
3.3 MMUs/Bus Interface Unit ...................................................................................3-5
3.4 Memory Coherency Actions................................................................................3-8
3.4.1 604-Initiated Load and Store Operations.........................................................3-8
3.5 Sequential Consistency........................................................................................3-9
3.5.1 Sequential Consistency Within a Single Processor .........................................3-9
3.5.2 Weak Consistency between Multiple Processors ............................................3-9
3.5.3 Sequential Consistency Within Multiprocessor Systems ..............................3-10
3.6 Memory and Cache Coherency..........................................................................3-10
3.6.1 Data Cache Coherency Protocol....................................................................3-11
3.6.2 Coherency and Secondary Caches.................................................................3-13
3.6.3 Page Table Control Bits.................................................................................3-13
3.6.4 MESI State Diagram......................................................................................3-13
3.6.5 Coherency Paradoxes in Single-Processor Systems ...................................... 3-14
3.6.6 Coherency Paradoxes
in Multiple-Processor Systems...................................3-15
3.7 CacheConfiguration..........................................................................................3-15
3.8 Cache Control Instructions ................................................................................3-16
3.8.1 Instruction Cache Block Invalidate (icbi)......................................................3-16
3.8.2 Instruction Synchronize (isync).....................................................................3-17
3.8.3 DataCache Block Touch (debt) and
Data Cache Block Touch for Store (dcbtst)..............................................3-17
3.8.4 Data Cache BlockSet
to Zero (dcbz)............................................................3-17
vi PowerPC 604 RISC Microprocessor User'sManual

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3.8.5 DataCache Block Store (dcbst) ....................................................................3-17
3.8.6 Data Cache BlockFlush (dcbf) .....................................................................3-18
3.8.7 DataCache Block Invalidate (dcbi) ........................•.............................•...••..3-18
3
.9 Basic Cache Operations .....................................................................................3-18
3.9.1 Cache Reloads................................................................................................3-18
3.9.2 CacheCast-Out Operation.............................................................................3-18
3.9.3 Cache Block Push Operation .........................................................................3-18
3.9.4 Atomic Memory References..........................................................................3-19
3.9.5 Snoop Response to Bus Operations...............................................................3-19
3.9.6 Cache Reaction to Specific Bus Operations ..................................................3-19
3.9.7 Enveloped High-Priority Cache Block Push Operation ................................ 3-22
3.9.8 Bus Operations Caused by Cache Control Instructions................................. 3-22
3.9.9 CacheControl Instructions ............................................................................3-23
3.10 Cache Actions...................................................................................................•3-23
3.11 Access to Direct-Store Segments............................................................•.....•....3-44
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.5
4.5.1
4.5.2
4.5.2.1
4.5.2.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
4.5.9
4.5.10
4.5.11
4.5.12
Contents
Chapter 4
Exceptions
PowerPC 604 Microprocessor Exceptions...........................................................4-2
Exception Recognition and Priorities ...............................................................•..4-5
Exception Processing...........................................................................................4-6
Enabling and Disabling Exceptions..........................•......................................4-9
Steps for Exception Processing......................................................................4-10
Setting MSR[RI] ............................................................................................4-10
Returning from an Exception Handler...........................................................4-11
Process Switching ..............................................................................................4-11
Exception Definitions ........................................................................................4-12
System Reset Exception (OxOOl00) ...............................................................4-13
Machine Check Exception (Ox00200) .......................................•.••................4-13
Machine Check Exception Enabled (MSR[ME] =
1) ................................4-14
Checkstop State (MSR[ME] =0) ..............................................................4-15
DSI Exception (Ox00300) ..............................................................................4-16
ISi Exception (Ox00400)................................................................................4-16
External Interrupt Exception (Ox00500) ........................................................4-16
Alignment Exception (Ox00600) ...............................•.......................•...........4-17
Program Exception (Ox00700).......................................................................4-17
Floating-Point Unavailable Exception (Ox00800) .........................................4-18
Decrementer Exception (Ox00900) ................................................................4-19
System Call Exception (OxOOCOO) ................................................................4-19
Trace Exception (OxOOD00) ..........................•................................................4-19
Floating-Point Assist Exception (OxOOEOO) ..........................••................••....4-19
vii