Infineon XMC4000 series User manual

Microcontroller
Hexagon Application Kit
For XMC4000 Family
Board User‘s Manual
Revision 1.0, 2013-02-20
CPU_45B-V1
CPU Board XMC4500 SDRAM

Edition 2013-02-20
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2013 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all
warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual
property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the
failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life
support devices or systems are intended to be implanted in the human body or to support and/or maintain and
sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other
persons may be endangered.

CPU_45B-V1
CPU Board XMC4500 SDRAM
Template: IFX_Template_2011-02-24.dot
Revision History
Page or Item
Subjects (major changes since previous revision)
Revision 1.0
2013-02-20
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™,
EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™,
ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™,
PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™,
SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by
AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum.
COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™
of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium.
HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™
of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR
STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc.
MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE
OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc.
Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of
Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd.
Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc.
TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company
Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments
Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex
Limited.
Last Trademarks Update 2011-02-24

CPU_45B-V1
CPU Board XMC4500 SDRAM
Table of Contents
Board User's Manual 4 Revision 1.0, 2013-02-20
Table of Contents
Introduction............................................................................................................................................................7
1Overview .............................................................................................................................................7
1.1 Key Features........................................................................................................................................7
1.2 Block Diagram......................................................................................................................................8
2Hardware Description........................................................................................................................9
2.1 Power Supply.......................................................................................................................................9
2.2 Reset..................................................................................................................................................12
2.3 Clock Generation................................................................................................................................13
2.4 Boot Option ........................................................................................................................................13
2.5 Debug Interface..................................................................................................................................14
2.5.1 On-board USB Debugger...................................................................................................................15
2.5.2 Cortex Debug Connector (10-pin)......................................................................................................16
2.5.3 Cortex Debug+ETM Connector (20-pin)............................................................................................17
2.6 Serial Flash Memory..........................................................................................................................19
2.7 SDRAM ..............................................................................................................................................20
2.8 USB....................................................................................................................................................20
2.9 RTC....................................................................................................................................................22
2.10 User LEDs and User Button...............................................................................................................23
2.11 Potentiometer.....................................................................................................................................23
2.12 Satellite Connectors...........................................................................................................................24
2.12.1 COM Connector .................................................................................................................................25
2.12.2 HMI Connector...................................................................................................................................26
2.12.3 ACT Satellite Connector.....................................................................................................................27
3Production Data................................................................................................................................27
3.1 Schematics.........................................................................................................................................27
3.2 Component Placement and Geometry...............................................................................................32
3.3 Bill of Material (BOM).........................................................................................................................33

CPU_45B-V1
CPU Board XMC4500 SDRAM
List of Figures
Board User's Manual 5 Revision 1.0, 2013-02-20
List of Figures
Figure 1 CPU_45B-V1 Board Block Diagram.....................................................................................................8
Figure 2 CPU Board XMC4500 SDRAM (CPU_45B-V1)...................................................................................9
Figure 3 Powering option..................................................................................................................................10
Figure 4 Block Diagram Of Power Supply........................................................................................................10
Figure 5 Reset Circuit.......................................................................................................................................12
Figure 6 Reset LED and Reset Button.............................................................................................................12
Figure 7 Clock Generation Circuit ....................................................................................................................13
Figure 8 Boot Options Switch...........................................................................................................................13
Figure 9 Installation of Serial Port Driver..........................................................................................................15
Figure 10 On-Board USB Debugger ..................................................................................................................15
Figure 11 Cortex Debug Connector (10-pin)......................................................................................................16
Figure 12 Cortex Debug Connector (10-pin) Layout..........................................................................................17
Figure 13 Cortex Debug+ETM Connector (20-pin)............................................................................................17
Figure 14 Cortex Debug+ETM Connector (20-pin) Layout ................................................................................18
Figure 15 Quad SPI Flash Interface...................................................................................................................19
Figure 16 SDRAM Interface ...............................................................................................................................20
Figure 17 USB Connector ..................................................................................................................................20
Figure 18 USB power generation - Host/OTG mode .........................................................................................21
Figure 19 Battery Holder for Coin Cells..............................................................................................................22
Figure 20 XMC4500 Power Domains and Real Time Clock ..............................................................................22
Figure 21 User LEDs and User Buttons.............................................................................................................23
Figure 22 Satellite Connectors...........................................................................................................................24
Figure 23 Satellite Connector Type COM ..........................................................................................................25
Figure 24 Satellite Connector Type HMI ............................................................................................................26
Figure 25 Satellite Connector Type ACT............................................................................................................27
Figure 26 Satellite Connectors, USB-OTG.........................................................................................................28
Figure 27 XMC4500 ...........................................................................................................................................29
Figure 28 Power, Debug Connector, Reset, SDRAM ........................................................................................30
Figure 29 On-board Debugger ...........................................................................................................................31
Figure 30 Component Placement and Geometry...............................................................................................32

CPU_45B-V1
CPU Board XMC4500 SDRAM
List of Figures
Board User's Manual 6 Revision 1.0, 2013-02-20
List of Tables
Table 1 Power status LEDs.............................................................................................................................10
Table 2 Power Measurement..........................................................................................................................11
Table 3 Boot Options Settings ........................................................................................................................13
Table 4 Cortex Debug Connector (10 Pin)......................................................................................................16
Table 5 Cortex Debug+ETM Connector (20 Pin)............................................................................................18
Table 6 Quad SPI Signals...............................................................................................................................19
Table 7 USB micro AB connector Pinout........................................................................................................21
Table 8 User LEDs..........................................................................................................................................23
Table 9 User Buttons.......................................................................................................................................23
Table 10 Potentiometer.....................................................................................................................................23
Table 11 BOM of CPU_45B-V1 Board..............................................................................................................33

CPU_45B-V1
CPU Board XMC4500 SDRAM
Overview
Board User's Manual 7 Revision 1.0, 2013-02-20
Introduction
This document describes the features and hardware details of the CPU board “CPU Board XMC4500 SDRAM”
(CPU_45B-V1) designed to work with Infineon’s XMC4500 Microcontroller. This board is part of Infineon’s
Hexagon Application Kits. Please visit www.infineon.com/xmc-dev for more information about the Hexagon
Application Kit family.
1 Overview
The CPU board CPU_45B-V1 houses the XMC4500 Microcontroller and three satellite connectors (HMI, COM,
ACT) for application expansion. The board along with satellite cards (e.g. HMI_OLED-V1, COM_ETH-V1,
AUT_ISO-V1 boards) demonstrates the capabilities of XMC4500.
The main use case of this board is to demonstrate the external bus unit (EBU) of the XMC4500 device including
the tool chain. For this purpose a 64 Mbit SDRAM is connected to the XMC4500 and for external bus extension
an asynchronous 16-bit wide bus interface is available at the COM satellite connector.
Attention: This board (CPU_45B) has not been designed to work with the “General Purpose Motor Drive
Card” (MOT_GPDLV). For this purpose please use the CPU boards CPU_45A, CPU_44A or
CPU_42A.
The focus is safe operation under evaluation conditions. The board is neither cost nor size optimized and does
not serve as a reference design.
1.1 Key Features
The CPU_45B-V1 board is equipped with the following features
XMC4500 (ARM®Cortex™-M4-based) Microcontroller, 1 MByte Flash, 160 kByte SRAM, LFBGA-144
8 MByte On-board SDRAM, 1 Mbit x 16 bits x 4 banks
Connection to satellite cards via satellite connectors COM, HMI and ACT
USB OTG Host/Device support via micro USB connector
Debug options
−On-board Debugger via the Debug USB connector
−Cortex Debug connector 10-pin (0.05”)
−Cortex Debug+ETM connector 20-pin (0.05”)
Reset push button
32 MBit quad SPI flash memory
Boot option switch
PowerScale Connector: Ready for power consumption analysis
Two User Buttons connected to P5.10 and P0.10
7 LED’s
3 Power indicating LED’s
2 User LEDs (P5.2 and P1.1)
1 RESET LED
1 Debug LED
Potentiometer, connected to analog input P14.1
Power supply
−Via Debug USB connector
−Via Micro-USB connector in USB device mode
−Via satellite connector pins (COM/ACT satellites cards can supply power to CPU board)
−RTC backup battery

CPU_45B-V1
CPU Board XMC4500 SDRAM
Overview
Board User's Manual 8 Revision 1.0, 2013-02-20
1.2 Block Diagram
Figure 1 shows the functional block diagram of the CPU_45B-V1 board. For more information about the power
supply please refer to chapter 2.1.
The CPU board has got the following building blocks:
- 3 Satellite Connectors (COM, HMI ACT)
- 2 User LEDs connected to GPIOs P5.2 and P1.1
- 2 User Buttons connected to GPIOs P5.10 and P0.10.
- Quad SPI flash memory (32 Mbit)
- Synchronous Dynamic RAM (SDRAM, 64Mbit)
- 2 Cortex Debug Connectors
- Variable resistor (POTI) connected to GPIO P14.1
- USB On-The-Go Connector (Micro-USB)
- On-board Debugger via USB connector (Micro-USB)
Figure 1 CPU_45B-V1 Board Block Diagram
Block_Diag.emf
EE
XMC4500
LFBGA144
EE
2xISOFACE
QSPI
I2C
I2C
CAN CAN1
CAPCOM
ENCODER
DSMOD
SENSOR
OPAMP
TOUCH
U2C1
CPU Board XMC4500
SDRAM
CPU_45B-V1
U1C1
2xCS
ETH ETHRMII
USB
OTG
USB CCU
4/8
POSIF
DSD
DAC
ADC
GPIO reset
QSPI
RS485
CAN
CAN
I2C_IOEX
Debug+ETM
20pin
I2C_IOEX
ACT
GPIO
GPIO
GPIO
GPIO GPIO GPIO
CAN
UART
I2S
SDCARD
GPIO cmd
OLED
I2C_IOEX
JTAG
HEADSET
U0C0
CAN1
BSL
POTI
SPI
I2C
GPIO
GPIO
GPIO
2xLED
2xButton
U2C0
2xCS
SPI
GPIO
SPI
HMI
SWD
SWV
Debug
10pin
SWD
SWV
Debug
USB
On-board
Debugger
XMC4200
EBU
EXTBUS
SDRAM
COM
EBU

CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Board User's Manual 9 Revision 1.0, 2013-02-20
2 Hardware Description
The following sections give a detailed description of the hardware and how it can be used.
Figure 2 CPU Board XMC4500 SDRAM (CPU_45B-V1)
2.1 Power Supply
The CPU_45B-V1 board can be powered via either of the USB plugs (5 V); however, there is a current limit that
can be drawn from the host PC through USB. If the CPU_45B-V1 board is used to drive other satellite cards
(e.g. AUT_ISO-V1 or MOT_GPDLV-V2) and the total current required exceeds 500 mA, then the board needs to
be powered by a satellite card, which supports external power supply like e.g. AUT_ISO-V1, MOT_GPDLV-V2,
COM_ETH-V1.
The typical current drawn by the CPU board without any satellite cards connected is about 220 mA (@5V).
For powering the board through an USB interface, connect the USB cable provided with the kit to either of the
Micro-USB connector on board as shown in Figure 3.
Board_Interfaces.emf
Debug
Connectors
Boot
Option
Switch
COM
Satellite
ConnEctor
qSPI
Flash
USB OTG
Connector Debug USB
Connector
ACT
Satellite
Connector
Power
indicating
LEDs
Reset
Circuit
Battery
Holder
HMI Satellite
Connector
Potentiometer
User LEDs
and User
Buttons On-board
Debugger
SDRAM
Debug
Connectors

CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Board User's Manual 10 Revision 1.0, 2013-02-20
Figure 3 Powering option
To indicate the power status of CPU_45B-V1 board three power indicating LED’s are provided on board (see
Figure 3). The LED will be “ON” when the corresponding power rail is powered.
Table 1 Power status LEDs
LED Reference
Power Rail
Voltage
Note
V401
VDD5
5 V
Must always be “ON”
V402
VDD5USB
5 V
“ON” if powered by USB OTG connector X203
“OFF” in all other supply cases
V403
VDD3.3
3.3 V
Must always be “ON”
Figure 4 Block Diagram Of Power Supply
Power.emf
USB OTG Debug USB
Power
indicating
LEDs
IFX1763
3.3V Linear
Voltage
Regulator PowerScale
Probe
CPU Board XMC4500 SDRAM
CPU_45B-V1
ACT Sat.
Connector
COM Sat.
Connector
HMI Sat.
Connector
Debug
USB
VDD5USB Lin. Voltage Regulator
IFX1763 VDDP
U200 U401 JP300 U300
EN
Power
LED
HIB_IO_1
P0.1
VDD5 VDD5 VBAT
XMC4400
LFBGA144
BATTERY
VDD3.3 On Board Devices
VDD3.3
Power_Block.emf
USB
OTG Power
LED Power
LED
VDD5USB +5V VDD5 +5V VDD3.3 +3.3V

CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Board User's Manual 11 Revision 1.0, 2013-02-20
Hitex PowerScale probe is provided on the CPU_45B-V1 board to measure the power consumption of the
XMC4500 device.
Table 2 Power Measurement
Jumper
Function
Description
JP300
PowerScale
A Hitex PowerScale probe can be connected for current sensing the
VDD3.3 (CPU power source). Default: pos. 1-2 (closed)
Note: On the PCB there is a shorting trace between pin 1-2. This trace has
to be cut first, before using PowerScale. Pin 3 is GND.

CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Board User's Manual 12 Revision 1.0, 2013-02-20
2.2 Reset
A reset signal connected to the low-active PORST# pin of the target CPU (U300) can be issued by
an on-board Reset Button (SW400, RESET)
an on-board debug device (U500)
an external debugger connected to either Cortex Debug connector X400 or X401
The RESET signal is routed to all satellite connectors. The reset circuit includes a red LED (V407) to indicate
the reset status: The Reset LED (V407) will be “ON” during active reset state and will be “OFF” if reset is not
active.
Be aware that PORST# is a bidirectional reset pin of the XMC4000 family which can also be pulled low by the
XMC4000 device itself.
Figure 5 Reset Circuit
Figure 6 Reset LED and Reset Button
Reset
Button
Reset
LED
RST.emf

CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Board User's Manual 13 Revision 1.0, 2013-02-20
2.3 Clock Generation
An external 12 MHz crystal provides the clock signal to the XMC4500 microcontroller. The drive strength of the
oscillator is set to maximum by software, in order to ensure a safe start-up of the oscillator even under worst
case conditions. A serial 510 Ohm resistor will attenuate the oscillations during operations.
For the RTC clock a separate external 32.768 kHz crystal is used on board.
Figure 7 Clock Generation Circuit
2.4 Boot Option
During power-on-reset the XMC4500 latches the dip switch SW300 settings via the TCK and the TMS pin.
Based on the values latched different boot options are possible.
Table 3 Boot Options Settings
BSL (TMS)
CAN/UART (TCK)
Boot Option
OFF (1)
UART (0)
Normal Mode (Boot from flash)
ON (0)
UART (0)
ASC BSL Enabled (Boot from UART)
OFF (1)
CAN (1)
BMI Customized Boot Enabled
ON (0)
CAN (1)
CAN BSL Enabled (Boot from CAN)
Figure 8 Boot Options Switch
Boot_Switch.emf
Boot
Option
Switch

CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Board User's Manual 14 Revision 1.0, 2013-02-20
2.5 Debug Interface
The CPU_45B-V1 board supports debugging via 3 different channels:
On-board Debugger
Cortex Debug Connector (10-pin)
Cortex Debug+ETM Connector (20-pin)
The Hexagon Application Boards are designed to use “Serial Wire Debug” as debug interface. JTAG debug is
not supported by default because the GPIO P0.7, where the required TDI function is mapped to also, is used by
the on-board SDRAM device and various Actuator boards connected to the ACT satellite connector.
Attention: It is strongly recommended not to use JTAG debug mode, especially if satellites boards are
connected, which uses the GPIO 0.7. For the same reason also do not use the on-board
debugger in JTAG mode.
If you want to use the JTAG debug mode through the cortex debug connectors (X400, X401) anyway, enable
the JTAG interface of the XMC device by assembling the pull-up resistor R427 (4k7 Ohm) and the resistor R410
(0 - 33 Ohm).

CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Board User's Manual 15 Revision 1.0, 2013-02-20
2.5.1 On-board USB Debugger
The on-board debugger [1] supports
Serial Wire Debug
Serial Wire Viewer [2]
Full Duplex UART communication via a USB Virtual COM
[1] Newer firmware versions of the on-board debugger require the latest J-Link driver (V4.62 or higher) and a
Serial Port Driver (CDC driver) installed on your computer. Please check “Install J-Link Serial Port Driver”
when installing the latest J-Link driver (see Figure 9)
[2] Serial Wire Viewer operation does not work during use of the on-board SDRAM.
Figure 9 Installation of Serial Port Driver
The on-board debugger can be accessed through the Debug USB connector shown in Figure 10. The Debug
LED V502 shows the status during debugging.
Figure 10 On-Board USB Debugger
When using an external debugger connected to the 10pin/20pin Cortex Debug Connector, the on-board
debugger is switched off.
When using the USB virtual COM port function of the on-board debugger (connected to P1.4 and P1.5 of the
XMC4500) the UART interface to the COM satellite is disabled through the switches U301 and U306.
Debug.emf
Debug USB
On-board
Debugger
Debug LED

CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Board User's Manual 16 Revision 1.0, 2013-02-20
2.5.2 Cortex Debug Connector (10-pin)
The CPU_45B-V1 board supports Serial Wire Debug operation through the 10-pin Cortex Debug Connector.
By default the board does not support Serial Wire Viewer operation through the 10-pin Cortex Debug
Connector, because the required SWO pin mapped to P2.1 is used for the connection to the on-board SDRAM.
If Serial Wire Viewer operation is required anyway the resistor R404 needs to be assembled.
JTAG operation additionally would require the TDI (P0.7) signal. By default the TDI signal is disconnected from
the Cortex Debug Connectors by a not assembled resistor R410, because the pin P0.7 can be used by the on-
board SDRAM, by Actuator boards connected to the ACT satellite connector and by boards connected to the
COM satellite connector.
Figure 11 Cortex Debug Connector (10-pin)
Table 4 Cortex Debug Connector (10 Pin)
Pin No.
Signal Name
Serial Wire Debug
JTAG Debug
1
VCC
+3.3 V
+3.3 V
2
SWDIO / TMS
Serial Wire Data I/O
Test Mode Select
3
GND
Ground
Ground
4
SWDCLK / TCK
Serial Wire Clock
Test Clock
5
GND
Ground
Ground
6
SWO / TDO
Trace Data OUT
Test Data OUT
7
KEY
KEY
KEY
8
NC / TDI
Not connected
Test Data IN
9
GNDDetect
Ground Detect
Ground Detect
10
nRESET
Reset (Active Low)
Reset (Active Low)
Cortex Debug
Connector (10-pin)
GNDDetect
SWDIO / TMS
SWDCLK / TCK
1 2
3 4
5 6
7 8
9 10
VCC
GND
GND
KEY
SWO / TDO
NC / TDI
nRESET
cortex-10pin.emf

CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Board User's Manual 17 Revision 1.0, 2013-02-20
Figure 12 Cortex Debug Connector (10-pin) Layout
2.5.3 Cortex Debug+ETM Connector (20-pin)
The CPU_45B-V1 board supports Serial Wire Debug operation and Instruction Trace operation through the 20-
pin Cortex Debug+ETM Connector.
The board does not support Serial Wire Viewer operation through the Cortex Debug Connectors by default,
because the required SWO pin mapped to P2.1 is used for the connection to the on-board SDRAM. If Serial
Wire Viewer operation is required anyway the resistor R404 needs to be assembled.
JTAG operation additionally would require the TDI (P0.7) signal. By default the TDI signal is disconnected from
the Cortex Debug Connectors by a not assembled resistor R410, because the pin P0.7 can be used by the on-
board SDRAM, by Actuator boards connected to the ACT satellite connector and by boards connected to the
COM satellite connector.
Figure 13 Cortex Debug+ETM Connector (20-pin)
10Pin_Conn.emf
Cortex Debug
Connector (10 Pin)
cortex-20pin.emf
SWO / TDO / EXTa / TRACECTL (NC)
Cortex Debug+ETM
Connector (20-pin)
GNDDetect
SWDIO / TMS
SWDCLK / TCK
1 2
3 4
5 6
7 8
910
VCC
GND
GND
KEY
nRESET
11 12
13 14
15 16
17 18
19 20
NC/EXTb/TDI (NC)
TRACECLK
TRACEDATA[0]
TRACEDATA[1]
TRACEDATA[2]
TRACEDATA[3]
GND/TgtPwr+Cap
GND/TgtPwr+Cap
GND
GND
GND

CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Board User's Manual 18 Revision 1.0, 2013-02-20
Table 5 Cortex Debug+ETM Connector (20 Pin)
Pin No.
Signal Name
Serial Wire Debug
JTAG Debug
1
VCC
+3.3 V
+3.3 V
2
SWDIO / TMS
Serial Wire Data I/O
Test Mode Select
3
GND
Ground
Ground
4
SWDCLK / TCK
Serial Wire Clock
Test Clock
5
GND
Ground
Ground
6
SWO / TDO
Trace Data OUT
Test Data OUT
7
KEY
KEY
KEY
8
NC / TDI
Not connected
Test Data IN
9
GNDDetect
Ground Detect
Ground Detect
10
nRESET
Reset (Active Low)
Reset (Active Low)
11
GND/TgtPwr+Cap
Ground
Ground
12
TRACECLK
Trace Clock
Trace Clock
13
GND/TgtPwr+Cap
Ground
Ground
14
TRACEDATA[0]
Trace Data 0
Trace Data 0
15
GND
Ground
Ground
16
TRACEDATA[1]
Trace Data 1
Trace Data 1
17
GND
Ground
Ground
18
TRACEDATA[2]
Trace Data 2
Trace Data 2
19
GND
Ground
Ground
20
TRACEDATA[3]
Trace Data 3
Trace Data 3
Figure 14 Cortex Debug+ETM Connector (20-pin) Layout
20 Pin_Conn.emf
Cortex Debug+ETM
Connector (20 Pin)

CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Board User's Manual 19 Revision 1.0, 2013-02-20
2.6 Serial Flash Memory
The CPU_45B-V1 board has 32Mbit serial flash memory interfaced to XMC4500 through a SPI interface. The
SPI interface can be configured as single, dual or quad SPI.
Table 6 Quad SPI Signals
Pin No.
Signal Name
Signal Description
P0.13
CLK
Clock
P3.3
CS#
Active Low Chip Select
P3.15
DI
Data Input of Flash (MTSR)
P3.14
DO
Data Output of Flash (MRST)
P0.14
Data I/O
Data Input/Output
P0.15
Data I/O
Data Input/Output
Figure 15 Quad SPI Flash Interface

CPU_45B-V1
CPU Board XMC4500 SDRAM
Hardware Description
Board User's Manual 20 Revision 1.0, 2013-02-20
2.7 SDRAM
The CPU_45B-V1 board has a 64 Mbit SDRAM interfaced to the XMC4500. The SDRAM interface is shown in
Figure 16.
Figure 16 SDRAM Interface
2.8 USB
The XMC4500 supports USB interface in host only mode, device only mode or as an OTG Dual Role Device
(DRD). In USB device mode, power is expected through VBUS (pin 1 of X203) from an external host (e.g. PC).
When the current consumption of the application running on the Hexagon Application system is higher than
500 mA, power from an external source through satellite cards shall be used.
Note: Some PCs, notebooks or hubs have a weak USB supply which is not sufficient for proper supply. In this
case use an external 5 Volt power supply or a powered USB hub.
Figure 17 USB Connector
The USB ID pin of the USB connector is connected to the port pin P15.2 of the XMC4500. This pin must be
polled by software, because this pin does not support USB_ID detection.
An OTG device will detect whether a USB 3.0 Micro-A or Micro-B plug is inserted by checking the ID pin. When
the ID = FALSE, Micro-A connector is plugged and when ID = TRUE a Micro-B connector is plugged in. When
ID is true the XMC4500 acts as USB host else as USB device.