Intel VC820 - Desktop Board Motherboard Guide

Intel®820 Chipset
Design Guide
July 2000
Order Number: 290631-004

Intel®820 Chipset Design Guide
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
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intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
The Intel®820 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.
Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and
North American Philips Corporation.
Alert on LAN and Wake on LAN are results of the IBM/Intel Advanced Manageability Alliance and are trademarks of IBM Corporation.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by:
calling 1-800-548-4725 or
by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2000
*Third-party brands and names are the property of their respective owners.

Intel®820 Chipset Design Guide iii
Contents
1 Introduction................................................................................................................1-1
1.1 About This Design Guide..............................................................................1-1
1.2 References....................................................................................................1-2
1.3 System Overview..........................................................................................1-2
1.3.1 Chipset Components .......................................................................1-3
1.3.2 Bandwidth Summary........................................................................1-4
1.3.3 System Configuration.......................................................................1-5
1.4 Platform Initiatives.........................................................................................1-8
1.4.1 Direct Rambus*................................................................................1-8
1.4.2 Streaming SIMD Extensions............................................................1-8
1.4.3 AGP 2.0 ...........................................................................................1-8
1.4.4 Hub Interface ...................................................................................1-8
1.4.5 Manageability...................................................................................1-9
1.4.6 AC’97.............................................................................................1-10
1.4.7 Low Pin Count (LPC) Interface ......................................................1-11
2 Layout/Routing Guidelines.........................................................................................2-1
2.1 General Recommendations..........................................................................2-1
2.2 Component Quadrant Layout........................................................................2-1
2.3 Intel®820 Chipset Component Placement ...................................................2-3
2.4 Core Chipset Routing Recommendations.....................................................2-4
2.5 Source Synchronous Strobing......................................................................2-5
2.6 Direct Rambus* Interface..............................................................................2-7
2.6.1 Stackup............................................................................................2-8
2.6.2 Direct Rambus* Layout Guidelines..................................................2-8
2.6.3 Direct Rambus* Reference Voltage...............................................2-25
2.6.4 High-speed CMOS Routing ...........................................................2-25
2.6.5 Direct Rambus* Clock Routing ......................................................2-28
2.6.6 Direct Rambus* Design Checklist..................................................2-28
2.7 AGP 2.0 ......................................................................................................2-31
2.7.1 AGP Interface Signal Groups.........................................................2-32
2.7.2 1X Timing Domain Routing Guidelines..........................................2-33
2.7.3 2X/4X Timing Domain Routing Guidelines.....................................2-33
2.7.4 AGP 2.0 Routing Summary............................................................2-35
2.7.5 AGP Clock Routing........................................................................2-36
2.7.6 General AGP Routing Guidelines ..................................................2-36
2.7.7 VDDQ Generation and TYPEDET# ...............................................2-37
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)....................................2-39
2.7.9 Compensation................................................................................2-41
2.7.10 AGP Pull-ups .................................................................................2-41
2.7.11 Motherboard / Add-in Card Interoperability....................................2-42
2.8 Hub Interface ..............................................................................................2-43
2.8.1 Data Signals...................................................................................2-44
2.8.2 Strobe Signals................................................................................2-44
2.8.3 HREF Generation/Distribution .......................................................2-44
2.8.4 Compensation................................................................................2-45

iv Intel®820 Chipset Design Guide
2.9 System Bus Design ....................................................................................2-46
2.9.1 100/133 MHz System Bus .............................................................2-46
2.9.2 System Bus Ground Plane Reference...........................................2-47
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM) .................................2-47
2.11 Processor CMOS Pullup Values.................................................................2-49
2.12 Additional Host Bus Guidelines ..................................................................2-52
2.13 Ultra ATA/66...............................................................................................2-56
2.13.1 Ultra ATA/66 Detection..................................................................2-56
2.13.2 Ultra ATA/66 Cable Detection........................................................2-57
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements ................................2-60
2.14 AC’97..........................................................................................................2-61
2.14.1 AC’97 Signal Quality Requirements...............................................2-63
2.14.2 AC’97 Motherboard Implementation..............................................2-63
2.15 USB ............................................................................................................2-65
2.16 ISA (82380AB)............................................................................................2-66
2.16.1 ICH GPIO connected to 82380AB .................................................2-66
2.16.2 Sub Class Code.............................................................................2-66
2.17 IOAPIC Design Recommendation ..............................................................2-66
2.18 SMBus/Alert Bus.........................................................................................2-67
2.19 PCI..............................................................................................................2-67
2.20 RTC ............................................................................................................2-67
2.20.1 RTC Crystal ...................................................................................2-68
2.20.2 External Capacitors .......................................................................2-68
2.20.3 RTC Layout Considerations...........................................................2-69
2.20.4 RTC External Battery Connection..................................................2-69
2.20.5 RTC External RTCRST Circuit.......................................................2-70
2.20.6 RTC Routing Guidelines................................................................2-70
2.20.7 VBIAS DC Voltage and Noise Measurements...............................2-71
3 Advanced System Bus Design ..................................................................................3-1
3.1 Terminology and Definitions .........................................................................3-1
3.2 AGTL+ Design Guidelines............................................................................3-4
3.2.1 Initial Timing Analysis ......................................................................3-5
3.2.2 Determine General Topology, Layout, and Routing Desired...........3-8
3.2.3 Pre-Layout Simulation .....................................................................3-8
3.2.4 Place and Route Board..................................................................3-10
3.2.5 Post-Layout Simulation..................................................................3-13
3.2.6 Validation.......................................................................................3-14
3.3 Theory.........................................................................................................3-15
3.3.1 AGTL+ ...........................................................................................3-15
3.3.2 Timing Requirements.....................................................................3-16
3.3.3 Cross-talk Theory ..........................................................................3-16
3.4 More Details and Insight.............................................................................3-19
3.4.1 Textbook Timing Equations ...........................................................3-19
3.4.2 Effective Impedance and Tolerance/Variation...............................3-20
3.4.3 Power/Reference Planes, PCB Stackup, and High
Frequency Decoupling...................................................................3-20
3.4.4 Clock Routing ................................................................................3-23

Intel®820 Chipset Design Guide v
3.5 Definitions of Flight Time Measurements/Corrections and Signal Quality..3-24
3.5.1 VREF Guardband............................................................................3-24
3.5.2 Ringback Levels.............................................................................3-24
3.5.3 Overdrive Region...........................................................................3-24
3.5.4 Flight Time Definition and Measurement .......................................3-25
3.6 Conclusion..................................................................................................3-26
4 Clocking.....................................................................................................................4-1
4.1 Clock Generation..........................................................................................4-1
4.2 Component Placement and Interconnection Layout Requirements..............4-6
4.2.1 14.318 MHz Crystal to CK133 .........................................................4-6
4.2.2 CK133 to DRCG ..............................................................................4-6
4.2.3 MCH to DRCG .................................................................................4-7
4.2.4 DRCG to RDRAM Channel..............................................................4-8
4.2.5 Trace Length....................................................................................4-8
4.3 DRCG Impedance Matching Circuit............................................................4-10
4.3.1 DRCG Layout Example..................................................................4-11
4.4 AGP Clock Routing Guidelines...................................................................4-11
4.5 Series Termination Resistors for CK133 Clock Outputs.............................4-11
4.6 Unused Outputs..........................................................................................4-12
4.7 Decoupling Recommendation for CK133 and DRCG.................................4-12
4.8 DRCG Frequency Selection and the DRCG+.............................................4-12
4.8.1 DRCG Frequency Selection Table and Jitter Specification ...........4-12
4.8.2 DRCG+ Frequency Selection Schematic.......................................4-13
5 System Manufacturing...............................................................................................5-1
5.1 In Circuit LPC Flash BIOS Programming......................................................5-1
5.2 LPC Flash BIOS Vpp Design Guidelines......................................................5-1
5.3 Stackup Requirement ...................................................................................5-1
5.3.1 Overview..........................................................................................5-1
5.3.2 PCB Materials..................................................................................5-2
5.3.3 Design Process................................................................................5-2
5.3.4 Test Coupon Design Guidelines......................................................5-3
5.3.5 Recommended Stackup...................................................................5-3
5.3.6 Inner Layer Routing .........................................................................5-3
5.3.7 Impedance Calculation Tools...........................................................5-4
5.3.8 Testing Board Impedance................................................................5-4
5.3.9 Board Impedance/Stackup Summary ..............................................5-5
6 System Design Considerations..................................................................................6-1
6.1 Power Delivery..............................................................................................6-1
6.1.1 Terminology and Definitions ............................................................6-1
6.1.2 Intel®820 Chipset Customer Reference Board Power Delivery......6-2
6.1.3 64/72Mbit RDRAM Excessive Power Consumption ........................6-5
6.2 Power Plane Splits........................................................................................6-7
6.3 Thermal Design Power .................................................................................6-7
6.4 Glue Chip 3 (Intel®820 Chipset Glue Chip) .................................................6-8
A Reference Design Schematics: Uni-Processor......................................................... A-1
A.1 Reference Design Feature Set .................................................................... A-1
B Reference Design Schematics: Dual-Processor.......................................................B-1
B.1 Reference Design Feature Set .................................................................... B-1

vi Intel®820 Chipset Design Guide
Figures
1-1 Intel®820 Chipset Platform Performance Desktop Block Diagram..............1-5
1-2 Intel®820 Chipset Platform Performance Desktop Block Diagram
(with ISA Bridge)...........................................................................................1-6
1-3 Intel®820 Chipset Platform Dual-Processor Performance Desktop
Block Diagram ..............................................................................................1-7
1-4 AC’97 Connections.....................................................................................1-11
2-1 MCH 324-uBGA Quadrant Layout (Top View)..............................................2-2
2-2 ICH 241-uBGA Quadrant Layout (Top View)................................................2-2
2-3 Sample ATX MCH/ICH Component Placement............................................2-3
2-4 Primary Side MCH Core Routing Example (ATX) ........................................2-4
2-5 Secondary Side MCH Core Routing Example (ATX)....................................2-5
2-6 Data Strobing Example.................................................................................2-6
2-7 Effect of Crosstalk on Strobe Signal.............................................................2-6
2-8 RIMM Diagram..............................................................................................2-7
2-9 RSL Routing Dimensions..............................................................................2-9
2-10 RSL Routing Diagram...................................................................................2-9
2-11 Primary Side RSL Breakout Example.........................................................2-10
2-12 Secondary Side RSL Breakout Example....................................................2-11
2-13 Direct RDRAM Termination ........................................................................2-11
2-14 Direct Rambus* Termination Example........................................................2-12
2-15 Incorrect Direct Rambus* Ground Plane Referencing................................2-13
2-16 Direct Rambus Ground Plane Reference ...................................................2-13
2-17 Connector Compensation Example............................................................2-16
2-18 Section A1, Top Layer.................................................................................2-17
2-19 Section A1, Bottom Layer ...........................................................................2-18
2-20 Section B1, Top Layer.................................................................................2-19
2-21 Section B1, Bottom Layer ...........................................................................2-20
2-22 RSL Signal Layer Alternation .....................................................................2-21
2-23 RDRAM Trace Length Matching Example..................................................2-22
2-24 "Dummy" Via vs. Real "Via"........................................................................2-23
2-25 RAMRef Generation Example Circuit ........................................................2-25
2-26 High-Speed CMOS Termination.................................................................2-26
2-27 SIO Routing Example.................................................................................2-26
2-28 RDRAM CMOS Shunt Transistor ..............................................................2-27
2-29 AGP 2X/4X Routing Example for Interfaces < 6”........................................2-34
2-30 Top Signal Layer.........................................................................................2-37
2-31 AGP VDDQ Generation Example Circuit....................................................2-39
2-32 AGP 2.0 VREF Generation & Distribution ..................................................2-40
2-33 Hub Interface Signal Routing Example.......................................................2-43
2-34 Single Hub Interface Reference Divider Circuit..........................................2-44
2-35 Locally generated Hub Interface Reference Dividers.................................2-45
2-36 Intel®Pentium®III Processor Dual Processor Configuration .....................2-46
2-37 Intel®Pentium®III Processor Uni-Processor Configuration .......................2-46
2-38 Ground Plane Reference (Four Layer Motherboard)..................................2-47
2-39 Hole Locations and Keepout Zones For Support Components ..................2-48
2-40 Grounding Pad Dimensions for the SECC2 GRM ......................................2-48
2-41 TCK/TMS Implementation Example for DP Designs ..................................2-52
2-42 Single Processor BREQ Strapping Requirements......................................2-52
2-43 Dual-Processor BREQ Strapping Requirements........................................2-53

Intel®820 Chipset Design Guide vii
2-44 BREQ0# Circuitry for DP Systems..............................................................2-53
2-45 HA7# Strapping Option Example Circuit (For Debug Purposes Only)........2-54
2-46 Host-Side IDE Cable Detection...................................................................2-57
2-47 Drive-Side IDE Cable Detection..................................................................2-58
2-48 Layout for Host- or Drive-Side IDE Cable Detection...................................2-59
2-49 Ultra ATA/66 Cable.....................................................................................2-59
2-50 Resistor Requirements for Primary IDE Connector ....................................2-60
2-51 Resistor Requirements for Secondary IDE Connector ...............................2-61
2-52 Tee Topology AC'97 Trace Length Requirements......................................2-62
2-53 Daisy-Chain Topology AC'97 Trace Length Requirements ........................2-62
2-54 USB Data Signals.......................................................................................2-65
2-55 PCI Bus Layout Example............................................................................2-67
2-56 External Circuitry for the ICH RTC..............................................................2-68
2-57 Diode Circuit Connecting RTC External Battery.........................................2-69
2-58 RTCRST External Circuit for the ICH RTC.................................................2-70
3-1 PICD[1,0] Uni-Processor Topology.............................................................3-12
3-2 PICD[1,0] Dual-Processor Topology...........................................................3-12
3-3 Test Load vs. Actual System Load .............................................................3-14
3-4 Aggressor and Victim Networks..................................................................3-17
3-5 Transmission Line Geometry: (A) Microstrip (B) Stripline...........................3-17
3-6 One Signal Layer and One Reference Plane..............................................3-21
3-7 Layer Switch with One Reference Plane ....................................................3-21
3-8 Layer Switch with Multiple Reference Planes (same type).........................3-21
3-9 Layer Switch with Multiple Reference Planes.............................................3-22
3-10 One Layer with Multiple Reference Planes.................................................3-22
3-11 Overdrive Region and VREF Guardband.....................................................3-25
3-12 Rising Edge Flight Time Measurement.......................................................3-25
4-1 Intel®820 Chipset Platform Clock Distribution .............................................4-2
4-2 Intel®820 Chipset Clock Routing Guidelines ...............................................4-4
4-3 CK133 to DRCG Routing Diagram ...............................................................4-6
4-4 MCH to DRCG Routing Diagram ..................................................................4-7
4-5 Direct Rambus* Clock Routing Dimensions..................................................4-7
4-6 Differential Clock Routing Diagram (Section ‘A’, ‘C’, & ‘D’)...........................4-9
4-7 Non-Differential Clock Routing Diagram (Section ‘B’)...................................4-9
4-8 Termination for Direct Rambus* Clocking Signals CFM/CFM# ....................4-9
4-9 DRCG Impedance Matching Network.........................................................4-10
4-10 DRCG Layout Example...............................................................................4-11
4-11 DRCG+ Frequency Selection .....................................................................4-13
5-1 28ΩTrace Geometry....................................................................................5-2
5-2 Microstrip and Stripline Cross-section for 28 ΩTrace ..................................5-4
5-3 7 mil Stackup (Not Routable)........................................................................5-5
5-4 4.5 mil Stackup .............................................................................................5-5
6-1 Intel®820 Chipset Power Delivery Example.................................................6-2
6-2 1.8V and 2.5V Power Sequencing (Schottky Diode) ....................................6-4
6-3 Use a GPO to Reduce DRCG Frequency.....................................................6-6
6-4 Power Plane Split Example...........................................................................6-7

viii Intel®820 Chipset Design Guide
Tables
1-1 Intel®820 Chipset Platform Bandwidth Summary........................................1-4
2-1 AGP 2X Data/Strobe Association .................................................................2-6
2-2 Placement Guidelines for Motherboard Routing Lengths.............................2-9
2-3 Copper Tab Area Calculation .....................................................................2-15
2-4 RSL Routing Layer Requirements..............................................................2-21
2-5 Line Matching and Via Compensation Example.........................................2-24
2-6 Signal List...................................................................................................2-28
2-7 AGP 2.0 Data/Strobe Associations.............................................................2-33
2-8 AGP 2.0 Routing Summary ........................................................................2-35
2-9 TYPDET#/VDDQ Relationship ...................................................................2-38
2-10 Connector/Add-in Card Interoperability ......................................................2-42
2-11 Voltage/Data Rate Interoperability..............................................................2-42
2-12 Segment Descriptions and Lengths for Figure 2-36 ...................................2-46
2-13 Processor and 82820 MCH Connection Checklist......................................2-49
2-14 Bus Request Connection Scheme for DP Intel®820 Chipset Designs.......2-52
2-15 ICH Codec Options.....................................................................................2-61
2-16 AC'97 SDIN Pulldown Resistors.................................................................2-63
3-1 AGTL+ Parameters for Example Calculations..............................................3-6
3-2 Example TFLT_MAX Calculations for 133 MHz Bus .......................................3-7
3-3 Example TFLT_MIN Calculations (Frequency Independent)...........................3-8
3-4 Trace Width Space Guidelines...................................................................3-11
3-5 Host Clock Routing.....................................................................................3-12
4-1 Intel®820 Chipset Platform System Clocks..................................................4-1
4-2 Intel®820 Chipset Platform Clock Skews.....................................................4-3
4-3 Intel®820 Chipset Platform System Clock Cross-Reference.......................4-5
4-4 Placement Guidelines for Motherboard Routing Lengths.............................4-8
4-5 External DRCG Component Values ...........................................................4-10
4-6 Unused Output Termination........................................................................4-12
4-7 DRCG Ratio................................................................................................4-12
5-1 28ΩStackup Examples ................................................................................5-3
5-2 3D Field Solver vs ZCALC............................................................................5-4
6-1 Intel®820 Chipset Component Thermal Design Power................................6-7
6-2 Glue Chip 3 Vendors ....................................................................................6-8

Intel®820 Chipset Design Guide ix
Revision History
Revision Description Date
-001 Initial Release. November 1999
-002
• Added dual-processor schematics (Appendix B).
• Uni-processor schematics have been updated (Appendix A). See the
schematic revision history page at the end of Appendix A for details.
- The following update is not in the schematic revision history.
Cap C249 (schematic page 9) has been changed from 0.022 uF to
0.047 uF.
December 1999
-003
• Updated the text descriptions in the two paragraphs in Section 4.2.3,
“MCH to DRCG”.
• Updated the first paragraph in Section 2.6.2.5, “RSL Signal Layer
Alternation“.
January 2000
-004 • Minor edits for clarity July 2000

xIntel®820 Chipset Design Guide
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1
Introduction

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Intel®820 Chipset Design Guide 1-1
Introduction
Introduction 1
The Intel®820 Chipset Design Guide provides design recommendations for systems using the
Intel®820 chipset. This includes motherboard layout and routing guidelines, system design issues
and requirements, debug recommendations, and board schematics. The design recommendations
should be used during system design. The guidelines have been developed to ensure maximum
flexibility for board designers while reducing the risk of board-related issues.
The Intel board schematics in Appendix A (uni-processor) and Appendix B (dual-processor) can be
used as references for board designers. A feature list is provided at the beginning of each appendix.
Although these schematics cover specific designs, the core schematics for each chipset component
remains the same for most Intel®820 chipset platforms. The appendices provides a set of reference
schematics for each chipset component, in addition to common motherboard options. Additional
flexibility is possible through other permutations of these options and components.
1.1 About This Design Guide
This design guide is intended for hardware designers who are experienced with PC architectures
and board design. The design guide assumes that the designer has a working knowledge of the
vocabulary and practices of PC hardware design.
•This chapter introduces the designer to the purpose and organization of this design guide, and
provides a list of references of related documents. This chapter also provides an overview of
the Intel®820 chipset.
•Chapter 2, "Layout/Routing Guidelines"—This chapter provides a detailed set of motherboard
layout and routing guidelines for designing an Intel®820 chipset based platform. The
motherboard functional units are covered (e.g., chipset component placement, system bus
routing, system memory layout, display cache interface, hub interface, IDE, AC’97, USB,
interrupts, SMBUS, PCD, LPC/FWH Flash BIOS, and RTC).
•Chapter 3, "Advanced System Bus Design"—AGTL+ guidelines and theory of operation are
discussed. This chapter also provides more detail about the methodologies used to develop the
guidelines.
•Chapter 4, "Clocking"— This chapter provides motherboard clocking guidelines (e.g., clock
architecture, routing, capacitor sites, clock power decoupling, and clock skew).
•Chapter 5, "System Manufacturing"— This chapter includes board stackup requirements.
•Chapter 6, "System Design Considerations"— This chapter includes guidelines regarding
power delivery, decoupling, thermal, and power sequencing.
•Appendix A, "Reference Board Schematics: Uni-Processor "— This appendix provides a set
of schematics for Uni-processor designs. A feature list for the board design is also provided.
•Appendix B, "Reference Board Schematics: Dual-Processor "— This appendix provides a set
of schematics for dual-processor designs. A feature list for the board design is also provided.

Introduction
1-2 Intel®820 Chipset Design Guide
1.2 References
•Intel®820 Chipset: Intel®82820 Memory Controller Hub (MCH) Datasheet
(Order Number: 290630)
•Intel®82801AA (ICH) and Intel®82801AB (ICH0) I/O Controller Hub Datasheet
(Order Number: 290655)
•Intel®82802AB/82802AC FirmWare Hub (FWH) Datasheet (Order Number: 290658)
•Pentium®II Processor AGTL+ Guidelines (Order Number: 243330)
•Pentium®II Processor Power Distribution Guideline (Order Number: 243332)
•Pentium®II Processor Developer's Manual (Order Number: 243341)
•Pentium®III Processor Specification Update (latest off of website)
•AP 907 Pentium III processor Power Distribution Guidelines (Order Number 245085)
•AP-585 Pentium II Processor AGTL+ Guidelines (Order Number: 243330)
•AP-587 Pentium II Processor Power Distribution Guidelines (Order Number: 243332)
•CK97 Clock Synthesizer Design Guidelines (Order Number 243867)
•PCI Local Bus Specification, Revision 2.2
•Universal Serial Bus Specification, Revision 1.0
•VRM 8.4 DC-DC Converter Design Guidelines (when available)
1.3 System Overview
The Intel®820 chipset is the third generation desktop chipset designed for Intel’s SC242
architecture and the first chipset to support the 4X capability of the AGP 2.0 Interface Specification
and 400 MHz Direct RDRAM. The 400 MHz, 16 bit, double clocked Direct RDRAM interface
provides 1.6 GB/s access to main memory. A new chipset component interconnect, the hub
interface, is designed into the Intel®820 chipset to provide more efficient communication between
chipset components.
Support of AGP 4X, 400 MHz Direct RDRAM and the hub interface provides a balanced system
architecture for the Pentium III processor, minimizing bottlenecks and increasing system
performance. By increasing memory bandwidth to 1.6 GB/s through the use of 400 MHz Direct
RDRAM and increasing graphics bandwidth to 1 GB/s through the use of AGP 4X, the Intel®820
chipset delivers the data throughput necessary to take advantage of the high performance provided
by the powerful Pentium III processor.
In addition, the Intel®820 chipset architecture enables a new security and manageability
infrastructure through the Firmware Hub component.
The ACPI compliant Intel®820 chipset platform can support the Full-on, Stop Grant, Suspend to
RAM, Suspend to Disk, and Soft-off power management states. Through the use of an appropriate
LAN device, Intel®820 chipset also supports Wake on LAN*for remote administration and
troubleshooting.
The Intel®820 chipset architecture removes the requirement for the ISA expansion bus that was
traditionally integrated into the I/O subsystem of Intel chipsets. This removes many of the conflicts
experienced when installing hardware and drivers into legacy ISA systems. The elimination of ISA
provides true plug-and-play for the Intel®820 chipset platform. Traditionally, the ISA interface
was used for audio and modem devices. The addition of AC’97 allows the OEM to use software

Intel®820 Chipset Design Guide 1-3
Introduction
configurable AC’97 audio and modem coder/decoders (codecs) instead of the traditional ISA
devices. The ISA bus can be implemented through the use of the optional 82380AB PCI-ISA
bridge.
The Intel®820 chipset contains two core components: the Memory Controller Hub (MCH) and the
I/O Controller Hub (ICH). The MCH integrates the 133 MHz processor system bus controller,
AGP 2.0 controller, 400 MHz Direct RDRAM controller and a high-speed hub interface for
communication with the ICH. The ICH integrates an UltraATA/66 controller, USB host controller,
LPC interface controller, FWH Flash BIOS interface controller, PCI interface controller, AC’97
digital controller and a hub interface for communication with the MCH. The Intel®820 chipset
provides the data buffering and interface arbitration required to ensure that system interfaces
operate efficiently and provide the system bandwidth necessary to obtain peak performance with
the Pentium III processor.
1.3.1 Chipset Components
This section provides an overview of the 82820 Memory Controller Hub (MCH) and the 82801AA
I/O Controller Hub (ICH). Additional functionality can be provided using the 82380AB PCI-ISA
bridge.
Memory Controller Hub (MCH)
The MCH provides the interconnect between the Direct RDRAM and the system logic. It integrates
the following functions:
•Support for single or dual SC242 processors with 100 MHz or 133 MHz System Bus
•256 MHz, 300 MHz, 356 MHz or 400 MHz Direct RDRAM interface supporting 1 GB of
Direct RDRAM
•4X, 1.5V AGP interface (3.3V 1X, 2X and 1.5V 1X, 2X devices also supported)
•Downstream hub interface for access to the ICH
In addition, the MCH provides arbitration, buffering and coherency management for each of these
interfaces. Refer to Chapter 2, “Layout/Routing Guidelines” for more information regarding these
interfaces.

Introduction
1-4 Intel®820 Chipset Design Guide
I/O Controller Hub (ICH)
The I/O Controller Hub provides the I/O subsystem with access to the rest of the system.
Additionally, it integrates many I/O functions. The ICH integrates the following functions:
•Upstream hub interface for access to the MCH
•2 channel Ultra ATA/66 Bus Master IDE controller
•USB controller
•I/O APIC
•SMBus controller
•FWH interface (FWH Flash BIOS)
•LPC interface
•AC’97 2.1 interface
•PCI 2.2 interface
•Integrated System Management Controller
•Alert on LAN*
The ICH also contains the arbitration and buffering necessary to ensure efficient utilization of these
interfaces. Refer to Chapter 2, “Layout/Routing Guidelines” for more information on these
interfaces.
ISA Bridge (82380AB)
For legacy needs, ISA support is an optional feature of the Intel®820 chipset. Implementations that
require ISA support can benefit from the enhancements of the Intel®820 chipset while “ISA-less”
designs are not burdened with the complexity and cost of the ISA subsystem.
The Intel®820 chipset platform with optional ISA support takes advantage of the 82380AB ISA
bridge. The bridge is a PCI to ISA bridge and resides on the PCI bus of the ICH.
1.3.2 Bandwidth Summary
Table 1-1 provides a summary of the bandwidth requirements for the Intel®820 chipset.
Table 1-1. Intel®820 Chipset Platform Bandwidth Summary
Interface Clock Speed
(MHz) Samples Per Clock Data Rate (Mega-samples/s) Data Width (Bytes) Bandwidth (MB/s)
Processor Bus 133 1 133 8 1066
RDRAM 266/300/356/400 2 533/600/711/800 2 1066/1200/1422/1600
AGP 2.0 66 4 266 4 1066
Hub Interface 66 4 266 1 266
PCI 2.2 33 1 33 4 133

Intel®820 Chipset Design Guide 1-5
Introduction
1.3.3 System Configuration
The following figures show typical platform configurations using the Intel®820 chipset.
Figure 1-1. Intel®820 Chipset Platform Performance Desktop Block Diagram
Main
Memory
Processor
PCI Bus
PCI Slot
s
82820
Memory
Controller Hub
(MCH)
82801AA
I/O Controller Hub
(ICH)
4X AGP
Graphics
Controller
Hub Interface
2 USB Ports
4 IDE Drives
AC'97 Codec(s)
(optional) AC'97 2.1
LPC I/F
Super I/O
Keyboard,
Mouse, FD,
PP, SP, IR
AGP 2.0
GPIO
FWH Flash
BIOS

Introduction
1-6 Intel®820 Chipset Design Guide
Figure 1-2. Intel®820 Chipset Platform Performance Desktop Block Diagram (with ISA Bridge)
Main
Memory
Processor
PCI Bus
82820
Memory
Controller Hub
(MCH)
ISA Bridge
(optional)
4X AGP
Graphics
Controller
Hub Interface
2 USB Ports
4 IDE Drives
AC'97 Codec(s)
(optional) AC'97 2.1
LPC I/F
Super I/O
Keyboard,
Mouse, FD,
PP, SP, IR
PCI Slot
s
ISA Slot
s
AGP 2.0
82801AA
I/O Controller Hub
(ICH)
GPIO
FWH Flash
BIOS

Intel®820 Chipset Design Guide 1-7
Introduction
Figure 1-3. Intel®820 Chipset Platform Dual-Processor Performance Desktop Block Diagram
Main
Memory
blk3
PCI Bus
82820
Memory
Controller Hub
(MCH)
ISA Bridge
(optional)
4X AGP
Graphics
Controller
Hub Interface
2 USB Ports
4 IDE Drives
AC'97 Codec(s)
(optional) AC'97 2.1
LPC I/F
Super I/O
Keyboard,
Mouse, FD,
PP, SP, IR
PCI Slot
s
ISA Slot
s
AGP 2.0
Processor Processor
Optional 2-Way/MP
82801AA
I/O Controller Hub
(ICH)
GPIO
FWH Flash
BIOS

Introduction
1-8 Intel®820 Chipset Design Guide
1.4 Platform Initiatives
1.4.1 Direct Rambus*
The Direct Rambus*(RDRAM) initiative provides the memory bandwidth necessary to obtain
optimal performance from the Pentium III processor as well as a high-performance AGP graphics
controller. The MCH RDRAM interface supports 266 MHz, 300 MHz, 356 MHz, and 400 MHz
operation; the latter delivers 1.6 GB/s of theoretical memory bandwidth; twice the memory
bandwidth of 100 MHz SDRAM systems. Coupled with the greater bandwidth, the RDRAM
protocol, which is heavily pipelined, provides substantially more efficient data transfer. The
RDRAM memory interface can achieve greater than 95% utilization of the 1.6 GB/s theoretical
maximum bandwidth.
In addition to RDRAM’s performance features, the new memory architecture provides enhanced
power management capabilities. The powerdown mode of operation enables Intel®820 chipset
based systems to cost-effectively support suspend-to-RAM.
1.4.2 Streaming SIMD Extensions
The Pentium III processor provides 70 new Streaming SIMD (single instruction, multiple data)
Extensions. The Pentium III new extensions are floating point SIMD extensions. Intel MMX™
technology provides integer SIMD extensions. The Pentium III processor new extensions
complement the Intel MMX™ technology SIMD extensions and provide a performance boost to
floating-point intensive 3D applications.
1.4.3 AGP 2.0
The AGP 2.0 interface, along with Direct Rambus*memory technology, allows graphics
controllers to access main memory at over 1 GB/s; twice the AGP bandwidth of previous AGP
platforms. AGP 2.0 provides the infrastructure necessary for photorealistic 3D. In conjunction with
Direct Rambus*and the Pentium III processor new Streaming SIMD Extensions, AGP 2.0 delivers
the next level of 3D graphics performance.
1.4.4 Hub Interface
As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become
significant. With the addition of AC’97 and ATA/66, coupled with the existing USB, I/O
requirements will begin to impact PCI bus performance. The Intel®820 chipset’s hub interface
architecture ensures that the I/O subsystem, both PCI and the integrated I/O features (IDE, AC’97,
USB, etc.), receives adequate bandwidth. By placing the I/O bridge on the hub interface instead of
PCI, the hub architecture ensures that both the I/O functions integrated into the ICH and the PCI
peripherals obtain the bandwidth necessary for peak performance. In addition, the hub interface’s
lower pin count allows a smaller package for the MCH and ICH.