Intel 80386 User manual

u.s. LITERATURE ORDER FORM
NAME: ____________________________________________________ ___
COMPANY:
ADDRESS:
__________________________________________________ _
CITY: _______________________________ STATE: ____ ZiP: ___ _
COUNTRY:
PHONE NO.: ( __ '-- ____________________ ___
ORDER NO.
~~~I-~~
~~~~~I-~~~
~~~~~I-~~~
~~~~~-I~~~
'----L--'----'----'---'---.J - I~~~
'----'----L-~'----'--.J - ,-I --'---'----J
Add appropriate postage
and handling to subtotal
10% U.S.
20% Canada
~--------~
Allow 2-4 weeks for delivery
TITLE
QTY. PRICE TOTAL
__ x __
__ x __
__ x __
__ x __
__ x __
__ x __
__ x __
Subtotal _____ _
Your Local Sales Tax
________ _
--------I.~ Postage & Handling ________ _
Total
________ _
Pay by Visa, MasterCard, Check or Money Order, payable to Intel Books. Purchase Orders
have a $50.00 minimum
o Visa 0 MasterCard Expiration Date _______ _
Account No.
Signature:
__________________________ _
Mail To: Intel Literature Sales
P.O. Box 58130
Santa Clara, CA
95052-8130
Customers outside the U.S. and Canada should con-
tact the local Intel Sales Office or Distributor listed
in the back of most Intel literature.
Call Toll Free: [phone] for phone orders
Prices good until 12131/86.
Source HB

Mail To: Intel Literature Sales
P.O. Box 58130
Santa Clara, CA 95052-8130

80386
HARDWARE REFERENCE MANUAL
1986

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may
appear
in this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks
of Intel Corporation and may only be used to identify Intel Products:
Above, BITBUS, COMMputer, CREDIT, Data Pipeline, FASTPATH, Genius,
i, t.
ICE, iCEL, iCS, iDBP, iDIS, I"ICE, iLBX, im, iMDDX, iMMX, Insite, Intel, intel,
intelBOS, Intelevision, inteligent Identifier, inteligent Programming, Intellec,
Intellink, iOSP, iPDS, iPSC, iRMX, iSBC, iSBX, iSDM, iSXM, KEPROM, Library
Manager, MAP-NET, MCS, Megachassis, MICROMAINFRAME, MULTIBUS,
MULTICHANNEL, MULTIMODULE, MultiSERVER,
ONCE, OpenNET, OTP,
PC-BUBBLE, Plug-A-Bubble, PROMPT, Promware, QUEST, QueX,
Quick-Pulse Programming, Ripplemode, RMX/BO, RUPI, Seamless, SLD, UPI,
and VLSiCEL, and the combination of ICE, iCS, iRMX, iSBC, iSBX, MCS, or UPI
and a numerical suffix, 4-SITE.
MDS is
an ordering code only and is not used as a product name or trademark. MDS" is a registered trademark of Mohawk
Data Sciences Corporation.
'MULTIBUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Distribution
Mail Stop SC6-59
3065 Bowers Avenue
Santa Clara, CA 95051
@INTEl CORPORATION 1986
ii
CG-6/86

PREFACE
The Intel 80386 is a high-performance 32-bit microprocessor. This manual provides complete
hardware reference information for 80386 system designs.
It is written for system engineers
and hardware designers
who understand the operating principles of microprocessors and
microcomputer systems. Readers of this manual should be familiar with the information
in
the Introduction to the 80386 (Intel publication Order Number 231252).
RELATED PUBLICATIONS
In this manual, the 80386 is presented from a hardware perspective. Information on the
software architecture, instruction set, and programming of the 80386 can be found in these
related Intel publications:
• 80386 Programmer's Reference Manual, Order Number 230985
• 80386 System Software Writer's Guide, Order Number 231499
• 80386 Data Sheet, Order Number 231630
The 80386 Data Sheet contains device specifications for the 80386. Always consult the most
recent version of this publication for specific 80386 parameter values.
Together with the 80386 Hardware Reference Manual, these publications provide a complete
description of the 80386 system for hardware designers, software engineers, and all users of
80386 systems.
ORGANIZATION OF THIS MANUAL
The information in this manual is divided into 12 chapters and three appendices. The material
begins with a description of the 80386 microprocessor and continues with discussions of
hardware design information needed to implement 80386 system designs.
• Chapter 1, "System Overview." This chapter provides an overview of the 80386 and its
supporting devices.
• Chapter 2, "Internal Architecture." This chapter describes the internal architecture of
the 80386.
• Chapter
3, "Local Bus Interface." This chapter discusses the 80386 local bus interface.
This chapter includes 80386 signal descriptions, memory and
I/O organization, and local
bus interface guidelines.
• Chapter 4, "Performance Considerations." This chapter explores the factors that affect
the performance of an 80386 system.
• Chapter 5, "Coprocessor Hardware Interface." This chapter describes the interface
between the 80386 and the 80287 and 80387 Numeric Coprocessors. Each of these copro-
cessors expands the floating-point numerical processing capabilities of the 80386.
iii

PREFACE
• Chapter 6, "Memory Interfacing." This chapter discusses techniques for designing memory
subsystems for the 80386.
• Chapter 7, "Cache Subsystems." This chapter describes cache memory subsystems, which
provide higher performance
at lower relative cost.
• Chapter 8, "I/O Interfacing." This chapter discusses techniques for connecting I/O devices
to
an 80386 system.
• Chapter 9, "MULTIBUS® I and 80386." This chapter describes the interface between
an 80386 system and the Intel
MUL TIBUS I multi-master system bus.
• Chapter 10, "MULTIBUS® II and 80386." This chapter describes the interface between
an 80386 system and the Intel MULTIBUS II multi-master system bus.
• Chapter 11, "Physical Design and Debugging." This chapter contains recommendations
for constructing and debugging 80386 systems.
• Chapter 12, "Test Capabilities." This chapter describes 80386 test procedures.
• Appendix A contains descriptions of the components of the basic memory interface
described in Chapter
6.
• Appendix B contains descriptions of the components of the 80387 emulator described in
Chapter
5.
• Appendix C contains descriptions of the components of the dynamic RAM subsystem
.described in Chapter 6.
iv

TABLE OF CONTENTS
CHAPTER 1 Page
SYSTEM OVERVIEW
1.1 Microprocessor ............................................................................................. 1-1
1.2 Coprocessors. ... .. ....... .. ... .. ... ...... ... .... . .. ... . .. . ... . ... .. . .. ... .. ...... .. ... .. .. ... .. ... .. ... .... ... 1-3
1.3 Interrupt Controller ........................................................................................ 1-4
1.4 Clock Generator ............................................................................................ 1-4
1.5 DMA Controller ......................................
... .... ... ............................................. 1-4
CHAPTER 2
INTERNAL ARCHITECTURE
2.1 Bus Interface Unit ...................................... ... ................................................. 2-2
2.2 Code Prefetch
Unit ........................................................................................ 2-3
2.3
Instruction Decode Unit ................................................................................. 2-3
2.4 Execution
Unit ............................................................................................... 2-3
2.5 Segmentation
Unit ......................................................................................... 2-4
2.6
Paging Unit .................................................................................................... 2-4
CHAPTER 3
LOCAL
BUS INTERFACE
3.1 Bus Operations .................................... ... ................................ ...... ................ 3-2
3.1.1
Bus States .............................................................................. ...... ............. 3-4
3.1.2 Address
Pipelining ......................... ...... ....................................................... 3-5
3.1.3 32-Bit Data
Bus Transfers and Operand Alignment ................ ...... ............. 3-5
3.1.4 Read
Cycle ... ........................................................................... ... ................ 3-10
3.1.5 Write Cycle .... ... ................................... ... ....... ... .......................................... 3-13
3.1.6
Pipelined Address Cycle ............................................................................. 3-14
3.1.7 Interrupt Acknowledge Cycle ..................................................................... 3-17
3.1.8 Halt/Shutdown Cycle ..........................
... .... ... ............ ... .............................. 3-18
3.1.9 BS16 Cycle ................................................................................................ 3-19
3.1.10 16-Bit Byte Enables and Operand Alignment ........................................... 3-20
3.2 Bus Timing .......................................... ... .... ... ............................ ... ................. 3-22
3.2.1 Read Cycle
Timing ..................................................................................... 3-24
3.2.2 Write Cycle
Timing ... ... ...................... ... .... ... ............................................... 3-24
3.2.3
READY# Signal Timing .............................................................................. 3-25
3.3 Clock Generation ...............................................
... ..... ... .............................. ... 3-26
3.3.1 82384 Clock Generator ..................
...... .... ... ............................................... 3-26
3.3.2 Clock
Timing .............................................................................................. 3-26
3.4 Interrupts .......................................
... ..... ... ..................................................... 3-27
3.4.1 Non-Maskable Interrupt (NMI) .................................................................... 3-29
3.4.2 Maskable Interrupt (INTR) ....................
...... ......... ... ................................. ... 3-29
3.4.3 Interrupt Latency........................
... ..... ... ..................................................... 3-30
3.5 Bus Lock ............................................... ... ....... ...... ........................................ 3-30
3.5.1 Locked Cycle Activators ................................. ... ......................................... 3-31
v

inter
TABLE OF CONTENTS
Page
3.5.2 Locked Cycle Timing .................................................................................. 3-32
3.5.3
LOCK# Signal Duration ............................................................................. 3-32
3.6 HOLDIHLDA (Hold Acknowledge) .........................................:....................... 3-33
3.6.1 HOLDIHLDA Timing .. ,................................................................................ 3-33
3.6.2 HOLD Signal Latency ................................................................................. 3-35
3.6.3 HOLD State Pin Conditions ........................................................................ 3-35
3.7 Reset ............................................................................................................. 3-35
3.7.1 RESET Timing ............................................................................................ 3-35
3.7.2 80386 Internal States ...................'.............................................................. 3-36
3.7.3 80386 External States ............................................................................... 3-38
CHAPTER 4
PERFORMANCE CONSIDERATIONS
4.1 Wait States and Pipelining ............................................................................. 4-1
CHAPTER 5
COPROCESSOR HARDWARE INTERFACE
5.1 80287 Numeric Coprocessor Interface .......................................................... 5-2
5.1.1 80287 Connections .................................................................................... 5-2
5.1.2 80287 Bus Cycles .. .................................................................................... 5-2
5.1.3 80287 Clock Input ...................................................................................... 5-4
5.2 80387 Numeric Coprocessor Interface
.. ........................................................ 5-4
5.2.1 80387 Connections . ...... ............................................................................. 5-4
5.2.2 80387 Bus Cycles ...................................................................................... 5-6
5.2.3 80387 Clock Input ...................................................................................... 5-6
5.3 Local Bus Activity with the 80287/80387 ...................................................... 5-6
5.4 Designing an Upgradable 80386 System ...................................................... 5-7
5.4.1 80287/80387 Recognition .......................................................................... 5-8
5.4.2 80387 Emulator .......................................................................................... 5-9
CHAPTER 6
MEMORY INTERFACING
6.1 Memory Speed versus Performance and Cost .............................................. 6-1
6.2 Basic Memory Interface ................................................................................. 6-1
6.2.1 PAL Devices ............................................................................................... 6-2
6.2.2 Address Latch ............................................................................................ 6-3
6.2.3 Address Decoder ....................................................................................... 6-4
6.2.4 Data Transceiver ........................................................................................ 6-5
6.2.5 Bus Control Logic .. .................................................................................... 6-6
6.2.6 EPROM Interface ....................................................................................... 6-9
6.2.7 SRAMlnterface .......................................................................................... 6-11
6.2.8 16-Bit Interface ........................................................................................... 6-14
6.3 Dynamic RAM (DRAM) Interface ................................................................... 6-15
vi

TABLE OF CONTENTS
Page
6.3.1 Interleaved Memory .................................................................................... 6-15
6.3.2
DRAM Memory Performance ..................................................................... 6-15
6.3.3 DRAM Controller ........................................................................................ 6-16
6.3.3.1 3-CLK DRAM Controller .......................................................................... 6-17
6.3.3.2
2-CLK DRAM Controller .. ........................................................................ 6-21
6.3.4 DRAM Design Variations .. .......................................................................... 6-23
6.3.5
Refresh Cycles ........................................................................................... 6-25
6.3.5.1 Distributed Refresh ................................................................................. 6-25
6.3.5.2
Burst Refresh ... ....................................................................................... 6-26
6.3.5.3
DMA Refresh ........................................................................................... 6-26
6.3.6
Initialization ................................................................................................. 6-27
6.3.7
Timing Analysis .......................................................................................... 6-27
CHAPTER 7
CACHE SUBSYSTEMS
7.1 Introduction to Caches .................................................................................. 7-2
7.1.1 Program Locality ........................................................................................ 7-2
7;1.2 Block Fetch ................................................................................................ 7-2
7.2 Cache Organizations ..................................................................................... 7-3
7.2.1 Fully Associative Cache .............................................................................. 7-3
7.2.2 Direct Mapped Cache ................................................................................. 7-4
7.2.3
Set Associative Cache ............................................................................... 7-6
7.3 Cache Updating ............................................................................................. 7-8
7.3.1 Write-Through System ............................................................................... 7-8
7.3.2
Buffered Write-Through System ................................................................. 7-8
7.3.3
Write-Back System .................................................................................... 7-9
7.3.4
Cache Coherency ....................................................................................... 7-10
7.4 System Structure and Performance .............................................................. 7-11
7.5 DMA Through Cache ..................................................................................... 7-12
7.6
Cache Example ............................................................................................. 7-13
7.6.1 Example Design .......................................................................................... 7-13
7.6.2
Example Cache Memory Organization ....................................................... 7-13
7.6.3
Example Cache Implementation ................................................................. 7-15
CHAPTER 8
I/O INTERFACING
8.1 I/O Mapping versus Memory Mapping ...................................................... .... 8-1
8.2 8-Bit, 16-Bit, and 32-Bit I/O Interfaces .......................................................... 8-1
8.2.1 Address Decoding ...................................................................................... 8-1
8.2.2 8-Bit I/O ..................................................................................................... 8-2
8.2.3 16-Bit I/O ................................................................................................... 8-4
8.2.4 32-Bit I/O ................................................................................................... 8-4
8.2.5 Linear Chip Selects .................................................................................... 8-4
vii