Intel 80386 User manual

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80386
HARDWARE REFERENCE MANUAL
1986

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may
appear
in this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks
of Intel Corporation and may only be used to identify Intel Products:
Above, BITBUS, COMMputer, CREDIT, Data Pipeline, FASTPATH, Genius,
i, t.
ICE, iCEL, iCS, iDBP, iDIS, I"ICE, iLBX, im, iMDDX, iMMX, Insite, Intel, intel,
intelBOS, Intelevision, inteligent Identifier, inteligent Programming, Intellec,
Intellink, iOSP, iPDS, iPSC, iRMX, iSBC, iSBX, iSDM, iSXM, KEPROM, Library
Manager, MAP-NET, MCS, Megachassis, MICROMAINFRAME, MULTIBUS,
MULTICHANNEL, MULTIMODULE, MultiSERVER,
ONCE, OpenNET, OTP,
PC-BUBBLE, Plug-A-Bubble, PROMPT, Promware, QUEST, QueX,
Quick-Pulse Programming, Ripplemode, RMX/BO, RUPI, Seamless, SLD, UPI,
and VLSiCEL, and the combination of ICE, iCS, iRMX, iSBC, iSBX, MCS, or UPI
and a numerical suffix, 4-SITE.
MDS is
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Data Sciences Corporation.
'MULTIBUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
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3065 Bowers Avenue
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@INTEl CORPORATION 1986
ii
CG-6/86

PREFACE
The Intel 80386 is a high-performance 32-bit microprocessor. This manual provides complete
hardware reference information for 80386 system designs.
It is written for system engineers
and hardware designers
who understand the operating principles of microprocessors and
microcomputer systems. Readers of this manual should be familiar with the information
in
the Introduction to the 80386 (Intel publication Order Number 231252).
RELATED PUBLICATIONS
In this manual, the 80386 is presented from a hardware perspective. Information on the
software architecture, instruction set, and programming of the 80386 can be found in these
related Intel publications:
• 80386 Programmer's Reference Manual, Order Number 230985
• 80386 System Software Writer's Guide, Order Number 231499
• 80386 Data Sheet, Order Number 231630
The 80386 Data Sheet contains device specifications for the 80386. Always consult the most
recent version of this publication for specific 80386 parameter values.
Together with the 80386 Hardware Reference Manual, these publications provide a complete
description of the 80386 system for hardware designers, software engineers, and all users of
80386 systems.
ORGANIZATION OF THIS MANUAL
The information in this manual is divided into 12 chapters and three appendices. The material
begins with a description of the 80386 microprocessor and continues with discussions of
hardware design information needed to implement 80386 system designs.
• Chapter 1, "System Overview." This chapter provides an overview of the 80386 and its
supporting devices.
• Chapter 2, "Internal Architecture." This chapter describes the internal architecture of
the 80386.
• Chapter
3, "Local Bus Interface." This chapter discusses the 80386 local bus interface.
This chapter includes 80386 signal descriptions, memory and
I/O organization, and local
bus interface guidelines.
• Chapter 4, "Performance Considerations." This chapter explores the factors that affect
the performance of an 80386 system.
• Chapter 5, "Coprocessor Hardware Interface." This chapter describes the interface
between the 80386 and the 80287 and 80387 Numeric Coprocessors. Each of these copro-
cessors expands the floating-point numerical processing capabilities of the 80386.
iii

PREFACE
• Chapter 6, "Memory Interfacing." This chapter discusses techniques for designing memory
subsystems for the 80386.
• Chapter 7, "Cache Subsystems." This chapter describes cache memory subsystems, which
provide higher performance
at lower relative cost.
• Chapter 8, "I/O Interfacing." This chapter discusses techniques for connecting I/O devices
to
an 80386 system.
• Chapter 9, "MULTIBUS® I and 80386." This chapter describes the interface between
an 80386 system and the Intel
MUL TIBUS I multi-master system bus.
• Chapter 10, "MULTIBUS® II and 80386." This chapter describes the interface between
an 80386 system and the Intel MULTIBUS II multi-master system bus.
• Chapter 11, "Physical Design and Debugging." This chapter contains recommendations
for constructing and debugging 80386 systems.
• Chapter 12, "Test Capabilities." This chapter describes 80386 test procedures.
• Appendix A contains descriptions of the components of the basic memory interface
described in Chapter
6.
• Appendix B contains descriptions of the components of the 80387 emulator described in
Chapter
5.
• Appendix C contains descriptions of the components of the dynamic RAM subsystem
.described in Chapter 6.
iv

TABLE OF CONTENTS
CHAPTER 1 Page
SYSTEM OVERVIEW
1.1 Microprocessor ............................................................................................. 1-1
1.2 Coprocessors. ... .. ....... .. ... .. ... ...... ... .... . .. ... . .. . ... . ... .. . .. ... .. ...... .. ... .. .. ... .. ... .. ... .... ... 1-3
1.3 Interrupt Controller ........................................................................................ 1-4
1.4 Clock Generator ............................................................................................ 1-4
1.5 DMA Controller ......................................
... .... ... ............................................. 1-4
CHAPTER 2
INTERNAL ARCHITECTURE
2.1 Bus Interface Unit ...................................... ... ................................................. 2-2
2.2 Code Prefetch
Unit ........................................................................................ 2-3
2.3
Instruction Decode Unit ................................................................................. 2-3
2.4 Execution
Unit ............................................................................................... 2-3
2.5 Segmentation
Unit ......................................................................................... 2-4
2.6
Paging Unit .................................................................................................... 2-4
CHAPTER 3
LOCAL
BUS INTERFACE
3.1 Bus Operations .................................... ... ................................ ...... ................ 3-2
3.1.1
Bus States .............................................................................. ...... ............. 3-4
3.1.2 Address
Pipelining ......................... ...... ....................................................... 3-5
3.1.3 32-Bit Data
Bus Transfers and Operand Alignment ................ ...... ............. 3-5
3.1.4 Read
Cycle ... ........................................................................... ... ................ 3-10
3.1.5 Write Cycle .... ... ................................... ... ....... ... .......................................... 3-13
3.1.6
Pipelined Address Cycle ............................................................................. 3-14
3.1.7 Interrupt Acknowledge Cycle ..................................................................... 3-17
3.1.8 Halt/Shutdown Cycle ..........................
... .... ... ............ ... .............................. 3-18
3.1.9 BS16 Cycle ................................................................................................ 3-19
3.1.10 16-Bit Byte Enables and Operand Alignment ........................................... 3-20
3.2 Bus Timing .......................................... ... .... ... ............................ ... ................. 3-22
3.2.1 Read Cycle
Timing ..................................................................................... 3-24
3.2.2 Write Cycle
Timing ... ... ...................... ... .... ... ............................................... 3-24
3.2.3
READY# Signal Timing .............................................................................. 3-25
3.3 Clock Generation ...............................................
... ..... ... .............................. ... 3-26
3.3.1 82384 Clock Generator ..................
...... .... ... ............................................... 3-26
3.3.2 Clock
Timing .............................................................................................. 3-26
3.4 Interrupts .......................................
... ..... ... ..................................................... 3-27
3.4.1 Non-Maskable Interrupt (NMI) .................................................................... 3-29
3.4.2 Maskable Interrupt (INTR) ....................
...... ......... ... ................................. ... 3-29
3.4.3 Interrupt Latency........................
... ..... ... ..................................................... 3-30
3.5 Bus Lock ............................................... ... ....... ...... ........................................ 3-30
3.5.1 Locked Cycle Activators ................................. ... ......................................... 3-31
v

inter
TABLE OF CONTENTS
Page
3.5.2 Locked Cycle Timing .................................................................................. 3-32
3.5.3
LOCK# Signal Duration ............................................................................. 3-32
3.6 HOLDIHLDA (Hold Acknowledge) .........................................:....................... 3-33
3.6.1 HOLDIHLDA Timing .. ,................................................................................ 3-33
3.6.2 HOLD Signal Latency ................................................................................. 3-35
3.6.3 HOLD State Pin Conditions ........................................................................ 3-35
3.7 Reset ............................................................................................................. 3-35
3.7.1 RESET Timing ............................................................................................ 3-35
3.7.2 80386 Internal States ...................'.............................................................. 3-36
3.7.3 80386 External States ............................................................................... 3-38
CHAPTER 4
PERFORMANCE CONSIDERATIONS
4.1 Wait States and Pipelining ............................................................................. 4-1
CHAPTER 5
COPROCESSOR HARDWARE INTERFACE
5.1 80287 Numeric Coprocessor Interface .......................................................... 5-2
5.1.1 80287 Connections .................................................................................... 5-2
5.1.2 80287 Bus Cycles .. .................................................................................... 5-2
5.1.3 80287 Clock Input ...................................................................................... 5-4
5.2 80387 Numeric Coprocessor Interface
.. ........................................................ 5-4
5.2.1 80387 Connections . ...... ............................................................................. 5-4
5.2.2 80387 Bus Cycles ...................................................................................... 5-6
5.2.3 80387 Clock Input ...................................................................................... 5-6
5.3 Local Bus Activity with the 80287/80387 ...................................................... 5-6
5.4 Designing an Upgradable 80386 System ...................................................... 5-7
5.4.1 80287/80387 Recognition .......................................................................... 5-8
5.4.2 80387 Emulator .......................................................................................... 5-9
CHAPTER 6
MEMORY INTERFACING
6.1 Memory Speed versus Performance and Cost .............................................. 6-1
6.2 Basic Memory Interface ................................................................................. 6-1
6.2.1 PAL Devices ............................................................................................... 6-2
6.2.2 Address Latch ............................................................................................ 6-3
6.2.3 Address Decoder ....................................................................................... 6-4
6.2.4 Data Transceiver ........................................................................................ 6-5
6.2.5 Bus Control Logic .. .................................................................................... 6-6
6.2.6 EPROM Interface ....................................................................................... 6-9
6.2.7 SRAMlnterface .......................................................................................... 6-11
6.2.8 16-Bit Interface ........................................................................................... 6-14
6.3 Dynamic RAM (DRAM) Interface ................................................................... 6-15
vi

TABLE OF CONTENTS
Page
6.3.1 Interleaved Memory .................................................................................... 6-15
6.3.2
DRAM Memory Performance ..................................................................... 6-15
6.3.3 DRAM Controller ........................................................................................ 6-16
6.3.3.1 3-CLK DRAM Controller .......................................................................... 6-17
6.3.3.2
2-CLK DRAM Controller .. ........................................................................ 6-21
6.3.4 DRAM Design Variations .. .......................................................................... 6-23
6.3.5
Refresh Cycles ........................................................................................... 6-25
6.3.5.1 Distributed Refresh ................................................................................. 6-25
6.3.5.2
Burst Refresh ... ....................................................................................... 6-26
6.3.5.3
DMA Refresh ........................................................................................... 6-26
6.3.6
Initialization ................................................................................................. 6-27
6.3.7
Timing Analysis .......................................................................................... 6-27
CHAPTER 7
CACHE SUBSYSTEMS
7.1 Introduction to Caches .................................................................................. 7-2
7.1.1 Program Locality ........................................................................................ 7-2
7;1.2 Block Fetch ................................................................................................ 7-2
7.2 Cache Organizations ..................................................................................... 7-3
7.2.1 Fully Associative Cache .............................................................................. 7-3
7.2.2 Direct Mapped Cache ................................................................................. 7-4
7.2.3
Set Associative Cache ............................................................................... 7-6
7.3 Cache Updating ............................................................................................. 7-8
7.3.1 Write-Through System ............................................................................... 7-8
7.3.2
Buffered Write-Through System ................................................................. 7-8
7.3.3
Write-Back System .................................................................................... 7-9
7.3.4
Cache Coherency ....................................................................................... 7-10
7.4 System Structure and Performance .............................................................. 7-11
7.5 DMA Through Cache ..................................................................................... 7-12
7.6
Cache Example ............................................................................................. 7-13
7.6.1 Example Design .......................................................................................... 7-13
7.6.2
Example Cache Memory Organization ....................................................... 7-13
7.6.3
Example Cache Implementation ................................................................. 7-15
CHAPTER 8
I/O INTERFACING
8.1 I/O Mapping versus Memory Mapping ...................................................... .... 8-1
8.2 8-Bit, 16-Bit, and 32-Bit I/O Interfaces .......................................................... 8-1
8.2.1 Address Decoding ...................................................................................... 8-1
8.2.2 8-Bit I/O ..................................................................................................... 8-2
8.2.3 16-Bit I/O ................................................................................................... 8-4
8.2.4 32-Bit I/O ................................................................................................... 8-4
8.2.5 Linear Chip Selects .................................................................................... 8-4
vii

TABLE OF CONTENTS
Page
8.3 Basic I/O Interface ......................................................................................... 8-4
8.3.1 Address Latch ............................................................................................ 8-5
8.3.2 Address Decoder ....................................................................................... 8-6
8.3.3 Data Transceiver ........................................................................................ 8-8
8.3.4 Bus Control Logic ...................................................................................... .8-8
8.4 Timing Analysis for I/O Operations ................................................................ 8-9
8.5 Basic I/O Examples ....................................................................................... 8-13
8.5.1 8274 Serial Controller .................................................................................. 8-14
8.5.2 8259A Interrupt Controller .......................................................................... 8-14
8.5.2.1 Single Interrupt Controller ....................................................................... 8-15
8.5.2.2 Cascaded Interrupt Controllers ............................................................... 8-16
8.5.2.3 Handling More Than 64 Interrupts ........................................................... 8-16
8.6 80286-Compatible Bus Cycles ...................................................................... 8-16
8.6.1
AO/A1 Generator ........................................................................................ 8-17
8.6.2
SO#/S1# Generator .................................................................................. 8-17
8.6.3 Wait-State Generator ................................................................................. 8-18
8.6.4 Bus Controller and Bus Arbiter .................................................................. 8-19
8.6.5 82258 ADMA Controller ..........................................................................•., 8-20
8.6.5.1 82258 as Bus Master .............................................................................. 8-22
8.6.5.2 82258 as Peripheral ................................................................................ 8-24
8.6.6 82586 LAN Coprocessor ............................................................................ 8-25
8.6.6.1 Dedicated CPU ........................................
... ............................................. 8-26
8.6.6.2 Decqupled Dual-Port Memory ................................................................. 8-26
8.6.6.3 Coupled Dual-Port Memory ..................................................................... 8-27
8.6.6.4 Shared Bus ............................................................................................. 8-28
CHAPTER 9
MUL TIBUS® I AND 80386
9.1 MUL TIBUS® I (IEEE 796) ............................................................................... 9-1
9.2 MUL TIBUS® I Interface Example ................................................................... 9-2
9.2.1 Address Latches and Data Transceivers .................................................... 9-2
9.2.2 Address Decoder ....................................................................................... 9-5
9.2.3 Wait-State Generator ................................................................................. 9-5
9.2.4 Bus Controller and Bus Arbiter .................................................................. 9-7
9.3 Timing Analysis
of MUL TIBUS® I Interface .................................................... 9-10
9.4 82289 Bus Arbiter ......................................................................................... 9-10
9.4.1 Priority Resolution .....•................................................................................ 9-11
9.4.2 82289 Operating Modes ............................................................................ 9-11
9.4.3 MULTIBUS® I Locked Cycles ............................................................\........ 9-14
9.5 Other MULTIBUS® I Design Considerations ...............................,.................. 9-14
9.5.1 Interrupt-Acknowledge on MUL
TIBUS® I .................................................... 9-14
9.5.2 Byte Swapping during MUL
TIBUS® I Byte Transfers ................................. 9-16
9.5.3 Bus Timeout Function for MULTIBUS® I Accesses .................................... 9-17
viii

TABLE OF CONTENTS
9.5.4 MUL TIBUS® I Power Failure Handling ........................................................
9.6
iLBX™ Bus Expansion ...................................................................................
9.7 Dual-Port RAM with MUL
TIBUS® I ................................................................
9.7.1 Avoiding Deadlock with Dual-Port RAM
CHAPTER 10
MULTIBUS® II AND 80386
10.1 MUL TIBUS® II Standard
10.2 Parallel System Bus (iPSB) ..........................................................................
10.2.1 iPSB Interface ..........................................................................................
10.2.1.1 BAC Signals ..........................................................................................
10.2.1.2 MIC Signals ...........................................................................................
10.3 Local Bus Extension (iLBXTM II) ....................................................................
10.4 Serial System Bus (iSSB) ............................................................................
CHAPTER 11
PHYSICAL DESIGN AND DEBUGGING
Page
9-17
9-18
9-19
9-20
10-1
10-1
10-2
10-4
10-6
10-7
10-7
11.1 Power and Ground Requirements ............................................................... 11-1
11 .1.1 Power and Ground Planes ....................................................................... 11-1
11 .1.2 Decoupling Capacitors ............................................................................. 11-2
11.2 High-Frequency Design Considerations ...................................................... 11-3
11 .2.1 Line Termination ....................................................................................... 11-4
11.2.2 Interference .............................................................................................. 11-5
11.2.3 Latchup .................................................................................................... 11-7
11.3 Clock Distribution and Termination ............................................................. 11-7
11.4 Thermal Characteristics ............................................................................... 11-7
11.5 Debugging Considerations .......................................................................... 11-10
11.5.1 Hardware Debugging Features ................................................................ 11-10
11.5.2 Bus Interface ............................................................................................ 11-11
11.5.3 Simplest Diagnostic Program ................................................................... 11-11
11.5.4 Building and Debugging a System Incrementally...................................... 11-12
11.5.5 Other Simple Diagnostic Software ........................................................... 11-14
11.5.6 Debugging Hints ....................................................................................... 11-14
CHAPTER 12
TEST CAPABILITIES
12.1 Internal Tests ..............................................................................................
12.1.1 Automatic Self-Test ................................................................................
..
12.1.2 Translation Lookaside Buffer Tests ........................................................ ..
12.2 Board-Level Tests
ix
12-1
12-1
12-2
12-5

.TABLE OF CONTENTS
APPENDIX A
LOCAL BUS CONTROL PAL DESCRIPTIONS
PAl-1 Functions ...................................................................................................
PAl-2
Functions ...................................................................................................
~Al Equations ..........................................................:..........................................
APPENDIX B
80387 EMULATOR PAL DESCRIPTION
APPENDIX C
DRAM PAL DESCRIPTIONS
Page
A-1
A-2
A-2
DRAM State
PAL ................................................................:................................ C-1
DRAM Control PAL ............................................................................................... C-13
Refresh Interval Counter PAL ............................................................................... C-13
Refresh Address Counter PAL ............................................................................. C-13
Timing Parameters ............................................................................................... C-25
Figures
Figure Title Page
1-1 80386 System Block Diagram ................................................................ 1-2
2-1 Instruction Pipelining ............................................................................... 2-1
2-2 80386 Functional Units ....................................:...................................... .2-2
3-1 ClK2 and ClK Relationship ................................................................... 3-5
3-2 80386
Bus States Timing Example ........................................................ 3-6
3-3 Bus State
Diagram (Does Not Include Address Pipelining) ..................... 3-7
3-4
Non-Pipelined Address and Pipelined Address Differences .................... 3-8
3-5 Consecutive Bytes
in Hardware Implementation .................................... 3-9
3-6
Address, Data Bus, and Byte Enables for 32-Bit Bus ............................ 3-9
3-7 MisalignedTransfer ........................................................................
;....... 3-11
3-8 Non-Pipelined Address Read Cycles ...................................................... 3-12
3-9
Non-Pipelined Address Write Cycles ...................................................... 3-15
3-10 Pipelined Address Cycles ....................................................,.................. 3-16
3-:.11 Interrupt Acknowledge Bus Cycles ......................................................... 3-18
3-12
Internal NA# and BS16# logic ............................................................. 3-20
3-13 32-Bit and 16-Bit Bus Cycle Timing ........................................................ 3-21
3-14 32-Bit and 16-Bit Data Addressing .................................:....................... 3-22
3-15
Connecting 82384 to 80386 ................................................................... 3-27
3-16
Using ClK to Determine Bus Cycle Start ............................................... 3-28
3-17 Error
Condition Caused by Unlocked Cycles .......................................... 3-31
3-18 lOCK# Signal during Address Pipelining ............................................... 3-32
3-19
Bus State Diagram with HOLD State ..................................................... 3-34
3-20 Typical RC.RESET Timing Circuit ........................................................... 3-36
3-21 RESET,
ClK, and ClK2 Timing .......,..................................................... 3-37
5-1 80386 System with 80287 Coprocessor ................................................ 5-3
x

TABLE OF CONTENTS
Figure Title Page
5-2 80386 System with 80387 Coprocessor ................................................ 5-5
5-3 Pseudo-Synchronous Interface ............................................................... 5-7
5-4 Routine to Detect 80287 Presence ........................................................ 5-8
5-5 80386 Machine Control Register
(CRO) .. ...................................... .... ...... 5-9
5-6 80387 Emulator Schematic .................................................................... 5-10
6-1 Basic Memory Interface Block Diagram ..... ... ............................. ... ..... ..... 6-2
6-2
PAL Equation and Implementation ......................................................... 6-4
6-3
PAL Naming Conventions ....................................................................... 6-5
6-4 Bus Control Logic ................................................................................... 6-7
6-5 Bus Control
Signal Timing ...................................................................... 6-8
6-6 150-Nanosecond
EPROM Timing Diagram ... ...... ... .................... ... ..... ..... 6-10
6-7 1 OO-Nanosecond SRAM Timing Diagram ............................................... 6-12
6-8 3-CLK
DRAM Controller Schematic ....... .... ......... ...................... .... .......... 6-18
6-9 3-CLK DRAM Controller Cycles ............. ...... ...... ...... ............................... 6-20
6-10 2-CLK
DRAM Controller Schematic .............. ...... ...................... ... ........... 6-22
6-11 2-CLK DRAM Controller Cycles ....... ...... .... ... ...... ... ................. ...... .......... 6-24
7
-1 Cache Memory System .......................................................................... 7-1
7 -2 Fully Associative Cache Organization ..................................................... 7-4
7
-3 Direct Mapped Cache Organization ........................................................ 7-5
7-4 Two-Way Set Associative
Cache Organization ...................................... 7-7
7
-5 Stale Data Problem ................................................................................. 7-9
7
-6 Hardware Transparency......... ... ........ ...... .... ... ....................... ... .............. 7-10
7-7 Non-Cacheable Memory ......................................................................... 7 -11
7 -8 Example of Cache Memory Organization .... ... ......................... ...... ......... 7-14
7-9 Cache Memory System Implementation
.... ... ...... ... ................................. 7-16
8-1 32-Bit to 8-Bit Bus Conversion ............................................................... 8-3
8-2 Linear
Chip Selects ................................................................................. 8-5
8-3 Basic I/O Interface Block Diagram
.... .... .................................................. 8-6
8-4 Basic I/O Interface Circuit ....................................................................... 8-7
8-5 Basic I/O Timing
Diagram ....................................................................... 8-11
8-6 8274 Interface .......................................... ... ....... ... .................. ...... ......... 8-14
8-7 Single 8259A Interface ........................................................................... 8-15
8-8 80286-Compatible Interface ................................................................... 8-18
8-9
AO, A1, and BHE# Logic ........................................................................ 8-20
8-10 SO#/S1# Generator Logic .....................................................................
8-21
8-11
Wait-State Generator Logic .. ............................. ... ............... .... ..... ..... ..... 8-21
8-12 82288 and 82289 Connections .............................................................. 8-22
8-13
HOLD and HLDA Logic for 80386-82258 Interface ... .......................... ... 8-23
8-14 82258
Slave Mode Interface ................................................................... 8-24
8-15
LAN Station ............................................................................................ 8-25
8-16 Decoupled Dual-Port Memory Interface
.... .............................................. 8-27
8-17 Coupled Dual-Port Memory Interface .....
........ ..... ... .................. ... ..... ...... 8-28
xi

Figure
8-18
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
10-1
10-2
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
12-1
12-2
A-1
A-2
A-3
A-4
B-1
C-1
C-2
C-3
C-4
C-5
C-6
C-7
C-8
TABLE OF CONTENTS
Title
Shared Bus Interface ............................................................................ ..
80386-MUl TIBUS® I Interface ............................................................. ..
MUl TIBUS® I Address latches and Data Transceivers ....................... ..
Wait-State Generator logic .................................................................. ..
MUl TIBUS® Arbiter and Bus Controller ............................................... ..
MUl TIBUS® I Read Cycle Timing ..........................................................
MUl TIBUS® I Write Cycle Timing ..........................................................
Bus Priority Resolution .....................:.....................................................
Operating Mode Configurations ..............................................................
Bus-Select logic for Interrupt Acknowledge ........................................ ..
Byte-Swapping logic .............................................................................
Bus-Timeout Protection Circuit ...............................................................
ilBX™ Signal Generation ........................................................................
iPSB Bus Cycle Timing ...........................................................................
iPSB Bus Interface .................................................................................
Reducing Characteristic Impedance .......................................................
Circuit without Decoupling ......................................................................
Decoupling Chip Capacitors ...................................................................
Decoupling leaded Capacitors ...............................................................
Series Termination ..................................................................................
Split Termination ........,............................................................................
Avoid Closed-loop Signal Paths ..........................................................
..
ClK2 Series Termination ........................................................................
ClK2 loading .........................................................................................
ClK2 Waveforms ...................................................................................
4-Byte Diagnostic Program ...................................................................
..
More Complex Diagnostic Program ........................................................
Object Code for Diagnostic Program ......................................................
80386 Self-Test ......................................................................................
TlB Test Registers .............................................................................. ..
PAl-1 State Listings .............................................................................. ..
PAl-2 State Listings ...............................................................................
PAl-1 Equations .....................................................................................
PAl-2 Equations .....................................................................................
80387 Emulator PAL Equations ........................................................... ..
PAL Sampling Edges ..............................................................................
3-ClK DRAM State PAL Equations ...................................................... ..
2-ClK DRAM State PAL Equations ........................................................
3-ClK DRAM Control PAL Equations ....................................................
2-ClK DRAM Control PAL Equations .................................................. ..
Refresh Interval Counter PAL Equations .............................................. ..
Refresh Address Counter PAL Equations ............................................ ..
DRAM Circuit Timing Diagram .............................................:................ ..
xii
Page
8-28
9-3
9-4
9-6
9-7
9-8
9-9
9-12
9-13
9-16
9-18
9-19
9-20
10-3
10-4
11-2
11-2
11-3
11-4
11-5
11-5
11-6
11-8
11-9
11-9
11-12
11-15
11-16
12-2
12-3
A-3
A-9
A-14
A-15
B-1
C-1
C-3
C-8
C-15
C-17
C-20
C-23
C-26

TABLE OF CONTENTS
Tables
Table Title Page
1-1 80386 System Components ................................................................... 1-1
3-1 Summary of 80386 Signal Pins .............................................................. 3-3
3-2 Bus Cycle Definitions .. .... .............. .. ........................................................ 3-4
3-3 Possible Data Transfers on 32-Bit Bus ................................................... 3-10
3-4 Misaligned Data Transfers on 32-Bit Bus ............................................... 3-13
3-5 Generation of BHE#, BLE#,
and A1 from Byte Enables ....................... 3-23
3-6 Byte
Enables during BS16 Cycles .......................................................... 3-23
3-7 Output Pin States during RESET ........................................................... 3-38
4-1 80386 Performance with Wait States and Pipelining .. ............................ 4-1
4-2 Wait States versus Operating Frequency ............................................... 4-3
6-1 Bus Cycles Generated by Bus Controller ............................................... 6-6
6-2 DRAM Memory Performance .................................................................. 6-16
6-3 Designs for
Six DRAM Types ................................................................. 6-28
7-1 Cache System Performance .............................................. .. ...... .. ........... 7 -12
8-1 Data Lines for 8-Bit I/O Addresses ......................................................... 8-2
8-2
Timings for Peripherals Using Basic I/O Interface ................................... 8-13
8-3 AO,A1,andBHE#TruthTable .............................................................. 8-19
9-1 MUL TIBUS® I Timing Parameters .......................................................... 9-10
C-1 DRAM State PAL Pin Description ........................................................... C-2
C-2 DRAM Control PAL Pin Description ........................................................ C-14
C-3 Refresh Interval Counter PAL Pin Description ........................................ C-19
C-4 Refresh Address Counter PAL Pin Description ....................................... C-22
C-5 DRAM Circuit Timing Parameters ........................................................... C-27
xiii

CUSTOMER SUPPORT
CUSTOMER SUPPORT
Customer Support is Intel's complete support service that provides Intel customers with Customer
Training, Software Support and Hardware Support.
After a customer purchases any system hardware or software product, service and support become
major factors in determining whether that product
will continue to meet a customer's expectations.
Such support requires an international support organization and a breadth of programs to meet a
variety
of customer needs. Intel's extensive customer support includes factory repair services as well as
worldwide field service offices providing hardware repair services, software support services and
customer training classes.
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Hardware Support Services provides maintenance on Intel supported products at board and system
level. Both field and factory services are offered. Services include several types of field maintenance
agreements, installationand warrantyservices, hourlycontracted'services (factoryreturnfor repair) and
specially negotiated support agreements for system integrators and large volume end-users having
unique service requirements. For more information contact your local Intel Sales Office.
SOFTWARE SUPPORT
Software Support Service provides maintenance on software packages via software support contracts '
which include subscription services, information phone support, and updates. Consulting services can
be arranged for on-site assistance at the customer's location for both short-term and long-term needs.
For complex products such as
NDS II or FICE, orientation/installation packages are available
through membership in Insite User's Library, where customer-submitted programs are catalogued and
made available for a minimum
fee to members. For more information contact your 10cal'lntel Sales
Office.
CUSTOMER TRAINING
Customer Training provides workshops at customer sites (by agreement) and on a regularly scheduled
basis at Intel's facilities. Intel offers a breadth
of workshops on microprocessors, operatingsystemsand
programming languages, etc.
For more information on these classes contactthe Training Center nearest
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5-215311-7

System Overview 1

CHAPTER 1
SYSTEM OVERVIEW
The 80386 is a new 32-bit microprocessor that forms the basis for a high-performance
32-bit system. The 80386 incorporates multitasking support, memory management, pipelined
architecture, address translation caches, and a high-speed bus interface all
on one chip. The
integration of these features speeds the execution of instructions and reduces overall chip
count for a system. Paging and dynamic data bus sizing can each be invoked selectively,
making the 80386 suitable for a wide variety of system designs and user applications.
While the 80386 represents a significant improvement over previous generations of micro-
processors, substantial ties to the earlier processors are preserved. Software compatibility at
the object-code level is provided, so that an existing investment in 8086 and 80286 software
can be maintained. New software can be built upon existing routines, reducing the time to
market for new products. Hardware compatibility
is preserved through the dynamic bus-
sizing feature.
The major components of an 80386 system and their functions are shown in Figure
I-I.
Table 1-1 describes these components.
1.1 MICROPROCESSOR
The 80386 provides unprecedented performance. At 16 MHz, the 80386 is capable of
executing
at sustained rates of three to four million instructions per second, a speed compa-
rable to that of most super minicomputers. This achievement is made possible through a
state-of-the-art design that includes a pipelined internal architecture, address translation
caches, and a high-performance bus.
The 80386 features 32-bit wide internal and external data paths and eight general-purpose
32-bit registers. The instruction set offers
8-, 16-, and 32-bit data types, and the processor
outputs 32-bit physical addresses directly, for a physical memory capacity of four gigabytes.
Table 1-1. 80386 System Components
Component Description
80386 Microprocessor 32-bit high-performance microprocessor with on-
chip memory management and protection
80287 or 80387 Numeric Coprocessor Performs numeric instruction in parallel with
80386; expands instruction set
82384 Clock Generator Generates system clock and
RESET signal
8259A Programmable Interrupt Controller Provides interrupt control and management
82258 Advanced DMA Performs direct memory controller access (DMA)
1-1