Intel X3350 - Xeon 2.66 Ghz 12M L2 Cache 1333MHz FSB LGA775 Quad-Core... User manual

Reference Number: 309007-011
Intel® Xeon® Processor 3300
Series
Specification Update
- on 45 nm Process in the 775-land LGA Package
January 2012

2Intel® Xeon® Processor 3300 Series
Specifcation Update January 2012
Legal Lines and Disclaimers
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BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
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LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY
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life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor
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processor numbers will increment based on changes in clock, speed, cache, or other features, and increments are not intended to
represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not
necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.
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processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible measured launched environment (MLE). The
MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT requires the system to contain a TPM
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technology/turboboost
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*Other names and brands may be claimed as the property of others.
Copyright © 2012, Intel Corporation. All Rights Reserved.

Intel® Xeon® Processor 3300 Series 3
Specifcation Update January 2012
Contents
Revision History .................................................................................................................5
Preface...............................................................................................................................6
Summary Tables of Changes.............................................................................................8
Identification Information..................................................................................................14
Component Identification Information...............................................................................15
Errata................................................................................................................................17
Specification Changes......................................................................................................40
Specification Clarifications ...............................................................................................41
Documentation Changes..................................................................................................42

4Intel® Xeon® Processor 3300 Series
Specifcation Update January 2012

Intel® Xeon® Processor 3300 Series 5
Specification Update January 2012
Revision History
Version Description Date
-001 Initial release January 2008
-002 Added Erratum AAA52 February 1, 2008
-003 Added Errata AAA53-AAA54
Updated Erratum AAA18 February 13, 2008
-004 Added Errata AAA55-AAA57
Added Spec Clarification AAA1 May 2008
-005 Added Errata AAA58-AAA60 July 2008
-006 Added Errata AAA61-AAA62 August 2008
-007 Added Errata AAA63-AAA75 Updated Erratum table with M0/R0/E0 info
Updated Component Information Table January 2009
-008 Updated Component Identification section with L3360 processor info February 2009
-009 Updated Component Identification section with X3380 processor info March 2, 2009
-010 Updated Erratum AAA1 March 11, 2009
-011 Added Erratum AAA76
Added Erratum AAA77 January 2012

6Intel® Xeon® Processor 3300 Series
Specification Update January 2012
Preface
This document is an update to the specifications contained in the documents listed in
the following Affected Documents/Related Documents table. It is a compilation of
device and document errata and specification clarifications and changes, and is
intended for hardware system manufacturers and for software developers of
applications, operating system, and tools.
Information types defined in the Nomenclature section of this document are
consolidated into this update document and are no longer published in other
documents. This document may also contain information that has not been previously
published.
Affected Documents
Related Documents
Nomenclature
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics (for example, core speed, L2 cache size,
package type, and so forth) as described in the processor identification information
table. Care should be taken to read all notes associated with each S-Spec number
Errata are design defects or errors. Errata may cause the processor’s behavior to
deviate from published specifications. Hardware and software designed to be used with
any given stepping must assume that all errata documented for that stepping are
present on all devices.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications will
be incorporated in the next release of the specifications.
Document Title Document Number
Intel®Xeon® Processor 3300 Series Datasheet 319005
Document Title Document Location
Intel®64 and IA-32 Architectures Software Developer’s Manual Volume 1:
Basic Architecture
http://www.intel.com/products/
processor/manuals/index.htm
Intel®64 and IA-32 Architectures Software Developer’s Manual Volume 2A:
Instruction Set Reference Manual A–M
Intel®64 and IA-32 Architectures Software Developer’s Manual Volume 2B:
Instruction Set Reference Manual, N–Z
Intel®64 and IA-32 Architectures Software Developer’s Manual Volume 3A:
System Programming Guide
Intel®64 and IA-32 Architectures Software Developer’s Manual Volume 3B:
System Programming Guide

Intel® Xeon® Processor 3300 Series 7
Specification Update January 2012
Documentation Changes include typos, errors, or omissions from the current
published specifications. These changes will be incorporated in the next release of the
specifications.
Note: Errata remain in the specification update throughout the product’s life cycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, and so
forth).

8Intel® Xeon® Processor 3300 Series
Specification Update January 2012
Summary Tables of Changes
The following table indicates the Specification Changes, Errata, Specification
Clarifications or Documentation Changes, which apply to the listed MCH steppings.
Intel intends to fix some of the errata in a future stepping of the component, and to
account for the other outstanding issues through documentation or Specification
Changes as noted. This table uses the following notations:
Codes Used in Summary Table
Stepping
X: Erratum, Specification Change or Clarification that
applies to this stepping.
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification
change does not apply to listed stepping.
Status
Doc: Document change or update that will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the
product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Row
Shaded: This item is either new or modified from the previous version of the
document.
Item Numbering
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
specification updates:
A = Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor
D = Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D
processor
I = Intel® Xeon® processor 5000 series
J = 64-bit Intel® Xeon® processor MP with 1 MB L2 cache
K = Mobile Intel® Pentium® III processor

Intel® Xeon® Processor 3300 Series 9
Specification Update January 2012
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel® Pentium® 4 processor
O = Intel® Xeon® processor MP
P = Intel ® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology
on 90-nm process technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2
cache versions)
T = Mobile Intel® Pentium® 4 processor-M
U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache
V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA
package
W= Intel® Celeron® M processor
X = Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and
Intel® processor A100 and A110 with 512-KB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus
AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor
Extreme Edition 955, 965
AB = Intel® Pentium® 4 processor 6x1 sequence
AC = Intel® Celeron® processor in 478 pin package
AD = Intel® Celeron® D processor on 65 nm processor
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65 nm
process
AF = Intel® Xeon® processor LV
AG = Intel® Xeon® processor 5100 series
AH = Intel® Core™ 2 Duo/Solo processor for Intel® Centrino® Duo processor
technology
AI = Intel® Core™ 2 Extreme processor X6800 and Intel® Core™ 2 Duo desktop
processor E6000 and E4000 sequence
AJ = Intel® Xeon® processor 5300 series
AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel®
Core™ 2 Quad processor Q6000 sequence
AL = Intel® Xeon® processor 7100 series
AM= Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® dual-core processor
AO = Intel® Xeon® processor 3200 series
AP = Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® dual-core desktop processor E2000 sequence

10 Intel® Xeon® Processor 3300 Series
Specification Update January 2012
The Specification Updates for the Pentium®processor, Pentium®Pro processor, and
other Intel products do not use this convention.
AR = Intel® Celeron® processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AT = Intel® Celeron® processor 200 series
AV = Intel® Core™ 2 Extreme Processor QX9650 Intel® Core™ 2 Extreme
Processor QX9650 and Intel® Core™ 2 Quad Processor Q9000 Series
AW = Intel® Core™ 2 Duo desktop processor E8000 and E7000 series
AX = Intel® Xeon® processor 5400 series
AY = Intel® Xeon® processor 5200 series
AAA = Intel® Xeon® processor 3300 series
AAB = Intel® Xeon® processor 3100 series
AAC= Intel® Celeron® dual-core processor E1000 series
Table 1. Errata (Sheet 1 of 4)
NO C0 M0 C1 M1 E0 R0 Plan ERRATA
AAA1 XX X X X X NoFix
EFLAGS Discrepancy on a Page Fault After a Multiprocessor TLB
Shootdown
EFLAGS Discrepancy on Page Fault After a Translation Change
AAA2 X X X X X X No Fix INVLPG Operation for Large (2M/4M) Pages May be Incomplete
Under Certain Conditions
AAA3 X X X X X X No Fix Store to WT Memory Data May be Seen in Wrong Order by Two
Subsequent Loads
AAA4 X X X X X X No Fix Non-Temporal Data Store May be Observed in Wrong Program Order
AAA5 X X X X X X No Fix Page Access Bit May be Set Prior to Signaling a Code Segment Limit
Fault
AAA6 X X X X X X No Fix Updating Code Page Directory Attributes without TLB Invalidation
May Result in Improper Handling of Code #PF
AAA7 X X X X X X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or
STI
AAA8 X X X X X X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
AAA9 X X X X X X No Fix A REP STOS/MOVS to a MONITOR/MWAIT Address Range May
Prevent Triggering of the Monitoring Hardware
AAA10XXX XXXNoFixPerformance Monitoring Event MISALIGN_MEM_REF May Over Count
AAA11XXX XXXNoFixThe Processor May Report a #TS Instead of a #GP Fault
AAA12XXX XXXNoFixCode Segment limit violation may occur on 4 Gigabyte limit check
AAA13XXX XXXNoFix
A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
AAA14XXX XXXNoFix
Last Branch Records (LBR) Updates May be Incorrect after a Task
Switch
AAA15XXX XXXNoFix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations.
AAA16XXX XXXNoFix
Upper 32 bits of ‘From’ Address Reported through BTMs or BTSs May
be Incorrect