Intel X3350 - Xeon 2.66 Ghz 12M L2 Cache 1333MHz FSB LGA775 Quad-Core... User manual

Reference Number: 309007-011
Intel® Xeon® Processor 3300
Series
Specification Update
- on 45 nm Process in the 775-land LGA Package
January 2012

2Intel® Xeon® Processor 3300 Series
Specifcation Update January 2012
Legal Lines and Disclaimers
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Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
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The processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
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Copyright © 2012, Intel Corporation. All Rights Reserved.

Intel® Xeon® Processor 3300 Series 3
Specifcation Update January 2012
Contents
Revision History .................................................................................................................5
Preface...............................................................................................................................6
Summary Tables of Changes.............................................................................................8
Identification Information..................................................................................................14
Component Identification Information...............................................................................15
Errata................................................................................................................................17
Specification Changes......................................................................................................40
Specification Clarifications ...............................................................................................41
Documentation Changes..................................................................................................42

4Intel® Xeon® Processor 3300 Series
Specifcation Update January 2012

Intel® Xeon® Processor 3300 Series 5
Specification Update January 2012
Revision History
Version Description Date
-001 Initial release January 2008
-002 Added Erratum AAA52 February 1, 2008
-003 Added Errata AAA53-AAA54
Updated Erratum AAA18 February 13, 2008
-004 Added Errata AAA55-AAA57
Added Spec Clarification AAA1 May 2008
-005 Added Errata AAA58-AAA60 July 2008
-006 Added Errata AAA61-AAA62 August 2008
-007 Added Errata AAA63-AAA75 Updated Erratum table with M0/R0/E0 info
Updated Component Information Table January 2009
-008 Updated Component Identification section with L3360 processor info February 2009
-009 Updated Component Identification section with X3380 processor info March 2, 2009
-010 Updated Erratum AAA1 March 11, 2009
-011 Added Erratum AAA76
Added Erratum AAA77 January 2012

6Intel® Xeon® Processor 3300 Series
Specification Update January 2012
Preface
This document is an update to the specifications contained in the documents listed in
the following Affected Documents/Related Documents table. It is a compilation of
device and document errata and specification clarifications and changes, and is
intended for hardware system manufacturers and for software developers of
applications, operating system, and tools.
Information types defined in the Nomenclature section of this document are
consolidated into this update document and are no longer published in other
documents. This document may also contain information that has not been previously
published.
Affected Documents
Related Documents
Nomenclature
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics (for example, core speed, L2 cache size,
package type, and so forth) as described in the processor identification information
table. Care should be taken to read all notes associated with each S-Spec number
Errata are design defects or errors. Errata may cause the processor’s behavior to
deviate from published specifications. Hardware and software designed to be used with
any given stepping must assume that all errata documented for that stepping are
present on all devices.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications will
be incorporated in the next release of the specifications.
Document Title Document Number
Intel®Xeon® Processor 3300 Series Datasheet 319005
Document Title Document Location
Intel®64 and IA-32 Architectures Software Developer’s Manual Volume 1:
Basic Architecture
http://www.intel.com/products/
processor/manuals/index.htm
Intel®64 and IA-32 Architectures Software Developer’s Manual Volume 2A:
Instruction Set Reference Manual A–M
Intel®64 and IA-32 Architectures Software Developer’s Manual Volume 2B:
Instruction Set Reference Manual, N–Z
Intel®64 and IA-32 Architectures Software Developer’s Manual Volume 3A:
System Programming Guide
Intel®64 and IA-32 Architectures Software Developer’s Manual Volume 3B:
System Programming Guide

Intel® Xeon® Processor 3300 Series 7
Specification Update January 2012
Documentation Changes include typos, errors, or omissions from the current
published specifications. These changes will be incorporated in the next release of the
specifications.
Note: Errata remain in the specification update throughout the product’s life cycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, and so
forth).

8Intel® Xeon® Processor 3300 Series
Specification Update January 2012
Summary Tables of Changes
The following table indicates the Specification Changes, Errata, Specification
Clarifications or Documentation Changes, which apply to the listed MCH steppings.
Intel intends to fix some of the errata in a future stepping of the component, and to
account for the other outstanding issues through documentation or Specification
Changes as noted. This table uses the following notations:
Codes Used in Summary Table
Stepping
X: Erratum, Specification Change or Clarification that
applies to this stepping.
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification
change does not apply to listed stepping.
Status
Doc: Document change or update that will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the
product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Row
Shaded: This item is either new or modified from the previous version of the
document.
Item Numbering
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
specification updates:
A = Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor
D = Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D
processor
I = Intel® Xeon® processor 5000 series
J = 64-bit Intel® Xeon® processor MP with 1 MB L2 cache
K = Mobile Intel® Pentium® III processor

Intel® Xeon® Processor 3300 Series 9
Specification Update January 2012
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel® Pentium® 4 processor
O = Intel® Xeon® processor MP
P = Intel ® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology
on 90-nm process technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2
cache versions)
T = Mobile Intel® Pentium® 4 processor-M
U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache
V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA
package
W= Intel® Celeron® M processor
X = Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and
Intel® processor A100 and A110 with 512-KB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus
AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor
Extreme Edition 955, 965
AB = Intel® Pentium® 4 processor 6x1 sequence
AC = Intel® Celeron® processor in 478 pin package
AD = Intel® Celeron® D processor on 65 nm processor
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65 nm
process
AF = Intel® Xeon® processor LV
AG = Intel® Xeon® processor 5100 series
AH = Intel® Core™ 2 Duo/Solo processor for Intel® Centrino® Duo processor
technology
AI = Intel® Core™ 2 Extreme processor X6800 and Intel® Core™ 2 Duo desktop
processor E6000 and E4000 sequence
AJ = Intel® Xeon® processor 5300 series
AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel®
Core™ 2 Quad processor Q6000 sequence
AL = Intel® Xeon® processor 7100 series
AM= Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® dual-core processor
AO = Intel® Xeon® processor 3200 series
AP = Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® dual-core desktop processor E2000 sequence

10 Intel® Xeon® Processor 3300 Series
Specification Update January 2012
The Specification Updates for the Pentium®processor, Pentium®Pro processor, and
other Intel products do not use this convention.
AR = Intel® Celeron® processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AT = Intel® Celeron® processor 200 series
AV = Intel® Core™ 2 Extreme Processor QX9650 Intel® Core™ 2 Extreme
Processor QX9650 and Intel® Core™ 2 Quad Processor Q9000 Series
AW = Intel® Core™ 2 Duo desktop processor E8000 and E7000 series
AX = Intel® Xeon® processor 5400 series
AY = Intel® Xeon® processor 5200 series
AAA = Intel® Xeon® processor 3300 series
AAB = Intel® Xeon® processor 3100 series
AAC= Intel® Celeron® dual-core processor E1000 series
Table 1. Errata (Sheet 1 of 4)
NO C0 M0 C1 M1 E0 R0 Plan ERRATA
AAA1 XX X X X X NoFix
EFLAGS Discrepancy on a Page Fault After a Multiprocessor TLB
Shootdown
EFLAGS Discrepancy on Page Fault After a Translation Change
AAA2 X X X X X X No Fix INVLPG Operation for Large (2M/4M) Pages May be Incomplete
Under Certain Conditions
AAA3 X X X X X X No Fix Store to WT Memory Data May be Seen in Wrong Order by Two
Subsequent Loads
AAA4 X X X X X X No Fix Non-Temporal Data Store May be Observed in Wrong Program Order
AAA5 X X X X X X No Fix Page Access Bit May be Set Prior to Signaling a Code Segment Limit
Fault
AAA6 X X X X X X No Fix Updating Code Page Directory Attributes without TLB Invalidation
May Result in Improper Handling of Code #PF
AAA7 X X X X X X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or
STI
AAA8 X X X X X X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
AAA9 X X X X X X No Fix A REP STOS/MOVS to a MONITOR/MWAIT Address Range May
Prevent Triggering of the Monitoring Hardware
AAA10XXX XXXNoFixPerformance Monitoring Event MISALIGN_MEM_REF May Over Count
AAA11XXX XXXNoFixThe Processor May Report a #TS Instead of a #GP Fault
AAA12XXX XXXNoFixCode Segment limit violation may occur on 4 Gigabyte limit check
AAA13XXX XXXNoFix
A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
AAA14XXX XXXNoFix
Last Branch Records (LBR) Updates May be Incorrect after a Task
Switch
AAA15XXX XXXNoFix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations.
AAA16XXX XXXNoFix
Upper 32 bits of ‘From’ Address Reported through BTMs or BTSs May
be Incorrect

Intel® Xeon® Processor 3300 Series 11
Specification Update January 2012
AAA17 X X X X X X No Fix Address Reported by Machine-Check Architecture (MCA) on Single-
bit L2 ECC Errors May be Incorrect
AAA18 X X X X X X No Fix Code Segment Limit/Canonical Faults on RSM May be Serviced
before Higher Priority Interrupts/Exceptions
AAA19 X X X X X X No Fix Store Ordering May be Incorrect between WC and WP Memory Types
AAA20 X X X X X X No Fix EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after
Shutdown
AAA21 X X X X X X No Fix Premature Execution of a Load Operation Prior to Exception Handler
Invocation
AAA22 X X X X X X No Fix Performance Monitoring Events for Retired Instructions (C0H) May
Not Be Accurate
AAA23 X X X X X X No Fix Returning to Real Mode from SMM with EFLAGS.VM Set May Result in
Unpredictable System Behavior
AAA24 X X X X X X No Fix CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or
Equal to 248 May Terminate Early
AAA25 X X X X X X No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
AAA26 X X X X X X No Fix Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
Before Higher Priority Interrupts
AAA27 X X X X X X No Fix VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the
Last Exception Record (LER) MSR
AAA28 X X X X X X No Fix INIT Does Not Clear Global Entries in the TLB
AAA29 X X X X X X No Fix Split Locked Stores May not Trigger the Monitoring Hardware
AAA30 X X X X X X No Fix Programming the Digital Thermal Sensor (DTS) Threshold May Cause
Unexpected Thermal Interrupts
AAA31 X X X X X X No Fix Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering Issue
AAA32 X X X X X X No Fix General Protection (#GP) Fault May Not Be Signaled on Data
Segment Limit Violation above 4-G Limit
AAA33 X X X X X X No Fix An Asynchronous MCE During a Far Transfer May Corrupt ESP
AAA34 X X X X X X Plan Fix CPUID Reports Architectural Performance Monitoring Version 2 is
Supported, When Only Version 1 Capabilities are Available
AAA35 X X X X X X No Fix B0-B3 Bits in DR6 May Not be Properly Cleared After Code
Breakpoint
AAA36 X X X X X X No Fix An xTPR Update Transaction Cycle, if Enabled, May be Issued to the
FSB after the Processor has Issued a Stop-Grant Special Cycle
AAA37 X X X X Fixed Performance Monitoring Event IA32_FIXED_CTR2 May Not Function
Properly when Max Ratio is a Non-Integer Core-to-Bus Ratio
AAA38 X X X X X X No Fix Instruction Fetch May Cause a Livelock During Snoops of the L1 Data
Cache
AAA39 X X X X X X No Fix Use of Memory Aliasing with Inconsistent Memory Type may Cause a
System Hang or a Machine Check Exception
AAA40 X X X X X X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to
Memory-Ordering Violations
AAA41 X X X X Fixed VM Exit with Exit Reason “TPR Below Threshold” Can Cause the Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in
the Guest Interruptibility-State Field
AAA42 X X X X X X No Fix Using Memory Type Aliasing with cacheable and WC Memory Types
May Lead to Memory Ordering Violations
Table 1. Errata (Sheet 2 of 4)
NO C0 M0 C1 M1 E0 R0 Plan ERRATA

12 Intel® Xeon® Processor 3300 Series
Specification Update January 2012
AAA43XXX XXXNoFix
VM Exit Caused by a SIPI Results in Zero to be Saved to the Guest
RIP Field in the VMCS
AAA44 X X X X Fixed NMIs May Not Be Blocked by a VM-Entry Failure
AAA45 X X X X Fixed Partial Streaming Load Instruction Sequence May Cause the
Processor to Hang
AAA46 X X X X Fixed Self/Cross Modifying Code May Not be Detected or May Cause a
Machine Check Exception
AAA47 X X X X Fixed Data TLB Eviction Condition in the Middle of a Cacheline Split Load
Operation May Cause the Processor to Hang
AAA48XXX XXXPlanFix
Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P)
Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
AAA49 X X X X Fixed RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
AAA50XXX XXXNoFix
Benign Exception after a Double Fault May Not Cause a Triple Fault
Shutdown
AAA51XXX XXXNoFix
LER MSRs May be Incorrectly UpdatedThe LER (Last Exception
Record) MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_LER_TO_LIP
(1DEH) may contain incorrect values after any of the following:
AAA52XXX XXXPlanFix
Short Nested Loops That Span Multiple 16-Byte Boundaries May
Cause a Machine Check Exception or a System Hang
AAA53XXX XXXNoFix
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after
MOV SS/POP SS Instruction if it is Followed by an Instruction That
Signals a Floating Point Exception
AAA54XXX XXXNoFix
IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check
Error Reporting Enable Correctly
AAA55XXX XXXNoFix
A VM Exit Due to a Fault While Delivering a Software Interrupt May
Save Incorrect Data into the VMCS
AAA56XXX XXXNoFix
A VM Exit Occurring in IA-32e Mode May Not Produce a VMX Abort
When Expected
AAA57XXX XXXNoFix
IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
AAA58XXX XXXPlanFixPSI# Signal Asserted During Reset
AAA59XXX XXXNoFix
Thermal Interrupts are Dropped During and While Exiting Deep
Power Down State
AAA60XXX XXXNoFix
VM Entry May Fail When Attempting to Set
IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN
AAA61XXX XXXNoFix
Corruption of CS Segment Register During RSM While Transitioning
From Real Mode to Protected Mode
AAA62XXX XXXNoFix
LBR, BTS, BTM May Report a Wrong Address when an Exception/
Interrupt Occurs in 64-bit Mode
AAA63XXX XXXNoFix
Memory Ordering Violation With Stores/Loads Crossing a Cacheline
Boundary
AAA64 X X No Fix Processor May Hold-off / Delay a PECI Transaction Longer than
Specified by the PECI Protocol
AAA65 X X No Fix VM Entry May Use Wrong Address to Access Virtual-APIC Page
AAA66 X X No Fix XRSTORE Instruction May Cause Extra Memory Reads
AAA67 X X Plan Fix CPUID Instruction May Return Incorrect Brand String
AAA68 X X No Fix Global Instruction TLB Entries May Not be Invalidated on a VM Exit or
VM Entry
Table 1. Errata (Sheet 3 of 4)
NO C0 M0 C1 M1 E0 R0 Plan ERRATA

Intel® Xeon® Processor 3300 Series 13
Specification Update January 2012
AAA69 X X No Fix When Intel® Deep Power-Down State is Being Used,
IA32_FIXED_CTR2 May Return Incorrect Cycle Counts
AAA70 X X No Fix Enabling PECI via the PECI_CTL MSR Does Not Enable PECI and May
Corrupt the CPUID Feature Flags
AAA71 X X No Fix INIT Incorrectly Resets IA32_LSTAR MSR
AAA72 X X No Fix The XRSTOR Instruction May Fail to Cause a General-Protection
Exception
AAA73 X X No Fix The XSAVE Instruction May Erroneously Set Reserved Bits in the
XSTATE_BV Field
AAA74 X X No Fix Store Ordering Violation When Using XSAVE
AAA75 X X Plan Fix Unsynchronized Cross-Modifying Code Operations Can Cause
Unexpected Instruction Execution Results
AAA76 X X X X X X No Fix A 64-bit Register IP-relative Instruction May Return Unexpected
Results
AAA77 X X X X X X No Fix Intel® Trusted Execution Technology ACM Revocation
Number SPECIFICATION CHANGES
- There are no Specification Changes in this Specification Update revision.
Number SPECIFICATION CLARIFICATIONS
- There are no Specification Clarifications in this Specification Update revision.
Number DOCUMENTATION CHANGES
- There are no Documentation Changes in this Specification Update revision.
Table 1. Errata (Sheet 4 of 4)
NO C0 M0 C1 M1 E0 R0 Plan ERRATA

14 Intel® Xeon® Processor 3300 Series
Specification Update January 2012
Identification Information
Figure 1. Processor Package Example
ATPO
S/N
INTEL ©'06 3300
INTEL® XEON®
SLxxx [COO]
2.83GHZ/2M/1333/05
[FPO]
M
e 4

Intel® Xeon® Processor 3300 Series 15
Specification Update January 2012
Component Identification
Information
The Intel® Xeon® Processor 3300 Series can be identified by the following values:
When EAX is initialized to a value of 1, the CPUID instruction returns the Extended
Family, Extended Model, Type, Family, Model and Stepping value in the EAX register.
Note that the EDX processor signature value after reset is equivalent to the processor
signature output value in the EAX register.
Notes:
1. The Extended Family, bits [27:20] are used in conjunction with the Family Code,
specified in bits [11:8], to indicate whether the processor belongs to the Intel386,
Intel486, Pentium, Pentium Pro, Pentium 4, Intel® CoreTM, or Enhanced Intel®
CoreTM processor family.
2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified
in bits [7:4], are used to identify the model of the processor within the processor’s
family.
3. The Processor Type, specified in bits [13:12] indicates whether the processor is an
original OEM processor or a Dual CPU Socket system.
4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits
[11:8] of the EAX register after the CPUID instruction is executed with a 1 in the
EAX register, and the generation field of the Device ID register accessible through
Boundary Scan.
5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits
[7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX
register, and the model field of the Device ID register accessible through Boundary
Scan.
6. The Stepping ID in bits [3:0] indicates the revision number of that model. See
Table 2, “Intel® Xeon® Processor 3300 Series Identification Information” for the
processor stepping ID number in the CPUID information.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX
registers after the CPUID instruction is executed with a 2 in the EAX register. Refer to
the Intel Processor Identification and the CPUID Instruction Application Note (AP-485)
for further information on the CPUID instruction.
Reserved Extended
Family1Extended
Model2Reserved Processor
Type3Family
Code4Model Number5Stepping ID6
31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0
00000000b 0001b 00b 0110b 0111b XXXXb

16 Intel® Xeon® Processor 3300 Series
Specification Update January 2012
Notes:
1. These processors support the 775_VR_CONFIG_05A specifications.
2. These parts support Intel®64.
3. These parts support Intel®Virtualization Technology (Intel®VT).
4. These parts support Execute Disable Bit Feature.
5. These parts have PROCHOT# enabled.
6. These parts have THERMTRIP# enabled.
7. These parts support Thermal Monitor 2 (TM2) feature.
8. These parts have PECI enabled.
9. These parts have Enhanced Intel SpeedStep®Technology enabled.
10. These parts have Extended HALT State (C1E) enabled.
11. These parts have Extended Stop Grant State (C2E) enabled.
12. These parts have Deep Sleep State (C3E) enabled.
13. These parts have Deeper Sleep State (C4E) enabled.
14. These processors support the 775_VR_CONFIG_06A specifications.
Table 2. Intel® Xeon® Processor 3300 Series Identification Information
S-Spec Core
Stepping
L2 Cache
Size
(bytes)
Processor
Signature Processor Number Speed Core/ Bus Package Notes
SLAN5 C0 12 MB
(2x6 MB) 10676h X3360 2.83 GHz /
1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8,
9, 10, 11
SLAN7 C0 12 MB
(2x6 MB) 10676h X3350 2.66 GHz / 1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
SLAWZ C1 12 MB
(2x6 MB) 10676h X3360 2.83 GHz / 1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
SLAX2 C1 12 MB
(2x6 MB) 10676h X3350 2.66 GHz / 1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
SLAWF M1 6 MB
(2x3 MB) 10676h X3320 2.50 GHz / 1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
SLB8Y E0 12 MB
(2x6 MB) 1067Ah X3350 2.66 GHz / 1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
SLB8X E0 12 MB
(2x6 MB) 1067Ah X3360 2.83 GHz / 1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
SLB8Z E0 12 MB
(2x6 MB) 1067Ah X3370 3.00 GHz / 1333
MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8,
9, 10, 11, 12, 13
SLGPG E0 12 MB
(2x6 MB) 1067Ah X3380 3.16 GHz / 1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
SLGPF E0 12 MB
(2x6 MB) 1067Ah L3360 2.83 GHz / 1333 MHz 775-land LGA 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 13, 14
SLB69 R0 6 MB
(2x3 MB) 1067Ah X3320 2.50 GHz /
1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8,
9, 10, 11, 12, 13
SLB6C R0 6 MB
(2x3 MB) 1067Ah X3330 2.66 GHz / 1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13

Intel® Xeon® Processor 3300 Series 17
Specification Update January 2012
Errata
AAA1. EFLAGS Discrepancy on Page Fault After a Translation Change
Problem: This erratum is regarding the case where paging structures are modified to change a
linear address from writable to non-writable without software performing an
appropriate TLB invalidation. When a subsequent access to that address by a specific
instruction (ADD, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, OR, ROL/ROR,
SAL/SAR/SHL/SHR, SHLD, SHRD, SUB, XOR, and XADD) causes a page fault, the value
saved for EFLAGS may incorrectly contain the arithmetic flag values that the EFLAGS
register would have held had the instruction completed without fault. This can occur
even if the fault causes a VM exit or if its delivery causes a nested fault.
Implication: None identified. Although the EFLAGS value saved may contain incorrect arithmetic flag
values, Intel has not identified software that is affected by this erratum. This erratum
will have no further effects once the original instruction is restarted because the
instruction will produce the same results as if it had initially completed without a page
fault.
Workaround: If the page fault handler inspects the arithmetic portion of the saved EFLAGS value,
then system software should perform a synchronized paging structure modification and
TLB invalidation.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA2. INVLPG Operation for Large (2M/4M) Pages May be Incomplete Under
Certain Conditions
Problem: The INVLPG instruction may not completely invalidate Translation Look-aside Buffer
(TLB) entries for large pages (2M/4M) when both of the following conditions exist:
• Address range of the page being invalidated spans several Memory Type Range
Registers (MTRRs) with different memory types specified
• INVLPG operation is preceded by a Page Assist Event (Page Fault [#PF] or an
access that results in either A or D bits being set in a Page Table Entry [PTE])
Implication: Stale translations may remain valid in TLB after a PTE update resulting in unpredictable
system behavior. Intel has not observed this erratum with any commercially available
software.
Workaround: Software should ensure that the memory type specified in the MTRRs is the same for
the entire address range of the large page.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA3. Store to WT Memory Data May be Seen in Wrong Order by Two
Subsequent Loads
Problem: When data of Store to WT memory is used by two subsequent loads of one thread and
another thread performs cacheable write to the same address the first load may get the
data from external memory or L2 written by another core, while the second load will
get the data straight from the WT Store.
Implication: Software that uses WB to WT memory aliasing may violate proper store ordering.
Workaround: Do not use WB to WT aliasing.
Status: For the steppings affected, see the Summary Tables of Changes.

18 Intel® Xeon® Processor 3300 Series
Specification Update January 2012
AAA4. Non-Temporal Data Store May be Observed in Wrong Program Order
Problem: When non-temporal data is accessed by multiple read operations in one thread while
another thread performs a cacheable write operation to the same address, the data
stored may be observed in wrong program order (that is, later load operations may
read older data).
Implication: Software that uses non-temporal data without proper serialization before accessing the
non-temporal data may observe data in wrong program order.
Workaround: Software that conforms to the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A, section “Buffering of Write Combining Memory Locations” will
operate correctly.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA5. Page Access Bit May be Set Prior to Signaling a Code Segment Limit
Fault
Problem: If code segment limit is set close to the end of a code page, then due to this erratum
the memory page Access bit (A bit) may be set for the subsequent page prior to
general protection fault on code segment limit.
Implication: When this erratum occurs, a non-accessed page which is present in memory and
follows a page that contains the code segment limit may be tagged as accessed.
Workaround: Erratum can be avoided by placing a guard page (non-present or non-executable page)
as the last page of the segment or after the page that includes the code segment limit.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA6. Updating Code Page Directory Attributes without TLB Invalidation May
Result in Improper Handling of Code #PF
Problem: Code #PF (Page Fault exception) is normally handled in lower priority order relative to
both code #DB (Debug Exception) and code Segment Limit Violation #GP (General
Protection Fault). Due to this erratum, code #PF may be handled incorrectly, if all of
the following conditions are met:
• A PDE (Page Directory Entry) is modified without invalidating the corresponding
TLB (Translation Look-aside Buffer) entry
• Code execution transitions to a different code page such that both
— The target linear address corresponds to the modified PDE
— The PTE (Page Table Entry) for the target linear address has an A (Accessed) bit
that is clear
• One of the following simultaneous exception conditions is present following the
code transition
— Code #DB and code #PF
— Code Segment Limit Violation #GP and code #PF
Implication: Software may observe either incorrect processing of code #PF before code Segment
Limit Violation #GP or processing of code #PF in lieu of code #DB.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA7. Storage of PEBS Record Delayed Following Execution of MOV SS or STI
Problem: When a performance monitoring counter is configured for PEBS (Precise Event Based
Sampling), overflow of the counter results in storage of a PEBS record in the PEBS

Intel® Xeon® Processor 3300 Series 19
Specification Update January 2012
buffer. The information in the PEBS record represents the state of the next instruction
to be executed following the counter overflow. Due to this erratum, if the counter
overflow occurs after execution of either MOV SS or STI, storage of the PEBS record is
delayed by one instruction.
Implication: When this erratum occurs, software may observe storage of the PEBS record being
delayed by one instruction following execution of MOV SS or STI. The state information
in the PEBS record will also reflect the one instruction delay.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA8. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts
transitions from x87 Floating Point (FP) to MMX™ instructions. Due to this erratum, if
only a small number of MMX instructions (including EMMS) are executed immediately
after the last FP instruction, a FP to MMX transition may not be counted.
Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be
lower than expected. The degree of undercounting is dependent on the occurrences of
the erratum condition while the counter is active. Intel has not observed this erratum
with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA9. A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent
Triggering of the Monitoring Hardware
Problem: The MONITOR instruction is used to arm the address monitoring hardware for the
subsequent MWAIT instruction. The hardware is triggered on subsequent memory
store operations to the monitored address range. Due to this erratum, REP STOS/
MOVS fast string operations to the monitored address range may prevent the actual
triggering store to be propagated to the monitoring hardware.
Implication: A logical processor executing an MWAIT instruction may not immediately continue
program execution if a REP STOS/MOVS targets the monitored address range.
Workaround: Software can avoid this erratum by not using REP STOS/MOVS store operations within
the monitored address range.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA10. Performance Monitoring Event MISALIGN_MEM_REF May Over Count
Problem: Performance monitoring event MISALIGN_MEM_REF (05H) is used to count the number
of memory accesses that cross an 8-byte boundary and are blocked until retirement.
Due to this erratum, the performance monitoring event MISALIGN_MEM_REF also
counts other memory accesses.
Implication: The performance monitoring event MISALIGN_MEM_REF may over count. The extent of
the over counting depends on the number of memory accesses retiring while the
counter is active.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.

20 Intel® Xeon® Processor 3300 Series
Specification Update January 2012
AAA11. The Processor May Report a #TS Instead of a #GP Fault
Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)
instead of a #GP fault (general protection exception).
Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP
fault. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA12. Code Segment limit violation may occur on 4 Gigabyte limit check
Problem: Code Segment limit violation may occur on 4 Gigabyte limit check when the code
streamwraps around in a way that one instruction ends at the last byte of the segment
and the next instruction begins at 0x0.
Implication: This is a rare condition that may result in a system hang. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: Avoid code that wraps around segment limit.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA13. A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
Problem: With respect to the retirement of instructions, stores to the uncacheable memory-
based APIC register space are handled in a non-synchronized way. For example if an
instruction that masks the interrupt flag, for example, CLI is executed soon after an
uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the
interrupt masking operation may take effect before the actual priority has been
lowered. This may cause interrupts whose priority is lower than the initial TPR, but
higher than the final TPR, to not be serviced until the interrupt enabled flag is finally
set, that is, by STI instruction. Interrupts will remain pending and are not lost.
Implication: In this example the processor may allow interrupts to be accepted but may delay their
service.
Workaround: This non-synchronization can be avoided by issuing an APIC register read after the
APIC register write. This will force the store to the APIC register before any subsequent
instructions are executed. No commercial operating system is known to be impacted by
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA14. Last Branch Records (LBR) Updates May be Incorrect after a Task
Switch
Problem: A Task-State Segment (TSS) task switch may incorrectly set the LBR_FROM value to
the LBR_TO value.
Implication: The LBR_FROM will have the incorrect address of the Branch Instruction.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAA15. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations.
Problem: Under certain conditions as described in the Software Developers Manual section “Out-
of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family