Intel 80960HA User manual

80960HA/HD/HT32-BitHigh-Performance
Superscalar Processor
Datasheet
Product Features
■32-Bit ParallelArchitecture
—Load/Store Architecture
—Sixteen 32-Bit Global Registers
—Sixteen 32-Bit Local Registers
—1.28 GbyteInternalBandwidth
(80MHz)
—On-Chip Register Cache
■ProcessorCore Clock
—80960HAis1x Bus Clock
—80960HDis2x Bus Clock
—80960HT is3x Bus Clock
■BinaryCompatible with Other80960
Processors
■Issue UpTo150 MillionInstructionsper
Second
■High-Performance On-Chip Storage
—16 Kbyte Four-Way Set-Associative
Instruction Cache
—8 Kbyte Four-Way Set-Associative Data
Cache
—2 Kbyte General Purpose RAM
■Separate 128-Bit Internal PathsFor
Instructions/Data
■3.3 VSupplyVoltage
—5VTolerant Inputs
—TTL CompatibleOutputs
■Guarded Memory Unit
—Provides Memory Protection
—User/Supervisor Read/Write/Execute
■32-Bit DemultiplexedBurst Bus
—Per-Byte Parity Generation/Checking
—Address Pipelining Option
—FullyProgrammable Wait State Generator
—Supports 8-, 16- or 32-BitBus Widths
—160 Mbyte/sExternal Bandwidth
(40 MHz)
■High-Speed InterruptController
—Upto 240 External Interrupts
—31 FullyProgrammable Priorities
—Separate, Non-maskableInterrupt Pin
■Dual On-Chip 32-BitTimers
—Auto Reload Capability andOne-Shot
—CLKINPrescaling, divided by 1, 2, 4 or 8
—JTAG Support - IEEE 1149.1 Compliant
Order Number: 272495-008
September 2002

2Datasheet
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INTELLECTUALPROPERTYRIGHT.Intelproductsare not intended for use inmedical, lifesaving, life sustaining applications.
Intelmay make changes to specifications and product descriptions atany time, without notice.
Designers must not relyon the absence or characteristics ofany featuresor instructions marked "reserved" or "undefined."Intelreserves these for
futuredefinitionand shall have noresponsibility whatsoeverforconflictsorincompatibilities arisingfromfuturechanges to them.
The 80960HA/HD/HT32-BitHigh-Performance Superscalar Processor may containdesign defects or errorsknown as erratawhichmay cause the
product to deviate from published specifications. Current characterized errataare availableon request.
Contact yourlocal Intel sales office or yourdistributor to obtainthe latest specifications and before placing yourproduct order.
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Copyright © Intel Corporation,2002
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Datasheet3
Contents
Contents
1.0About This Document ...................................................................................................................9
2.0Intel 80960Hx Processor...............................................................................................................9
2.1 The i960®ProcessorFamily...............................................................................................10
2.2 Key80960Hx Features.......................................................................................................10
2.2.1Execution Architecture...........................................................................................10
2.2.2Pipelined, Burst Bus..............................................................................................10
2.2.3On-ChipCachesand Data RAM............................................................................11
2.2.4Priority Interrupt Controller.....................................................................................11
2.2.5Guarded MemoryUnit ...........................................................................................11
2.2.6Dual Programmable Timers...................................................................................12
2.2.7ProcessorSelf Test ...............................................................................................12
2.3 InstructionSet Summary....................................................................................................13
3.0PackageInformation...................................................................................................................14
3.1 PinDescriptions..................................................................................................................15
3.2 80960Hx Mechanical Data..................................................................................................20
3.2.1 80960Hx PGA Pinout.............................................................................................20
3.2.2 80960Hx PQ4 Pinout.............................................................................................26
3.3 Package Thermal Specifications........................................................................................31
3.4 Heat Sink Adhesives...........................................................................................................34
3.5 PowerQuad4 PlasticPackage ............................................................................................34
3.6 Stepping Register Information ............................................................................................34
3.7 SourcesforAccessories.....................................................................................................36
4.0ElectricalSpecifications.............................................................................................................37
4.1 Absolute Maximum Ratings................................................................................................37
4.2 Operating Conditions..........................................................................................................37
4.3 Recommended Connections..............................................................................................38
4.4 VCC5 Pin Requirements (VDIFF)........................................................................................38
4.5 VCCPLL Pin Requirements ................................................................................................39
4.6 DC Specifications ...............................................................................................................40
4.7 AC Specifications................................................................................................................42
4.7.1ACTestConditions................................................................................................45
4.8 AC Timing Waveforms........................................................................................................46
5.0BusWaveforms...........................................................................................................................54
5.1 80960Hx BoundaryScan Chain.........................................................................................84
5.2 BoundaryScan Description Language Example ................................................................88
Figures
1 80960Hx BlockDiagram...............................................................................................................9
2 80960Hx 168-Pin PGAPinout—View from Top (PinsFacing Down).........................................20
3 80960Hx 168-Pin PGAPinout—View from Bottom (PinsFacing Up) ........................................21
4 80960Hx 208-Pin PQ4Pinout.....................................................................................................26
5Measuring 80960Hx PGACaseTemperature............................................................................31
6 80960Hx DeviceIdentification Register......................................................................................34

Contents
4Datasheet
7VCC5 Current-Limiting Resistor .................................................................................................38
8AC Test Load..............................................................................................................................45
9CLKIN Waveform........................................................................................................................46
10 OutputDelayWaveform.............................................................................................................46
11 OutputDelayWaveform.............................................................................................................46
12 OutputFloat Waveform..............................................................................................................47
13 Input Setup and Hold Waveform................................................................................................47
14 NMI, XINT7:0 Input Setup and HoldWaveform..........................................................................47
15 HoldAcknowledge Timings........................................................................................................48
16 BusBackoff (BOFF) Timings......................................................................................................48
17 TCK Waveform...........................................................................................................................49
18 Input Setup and Hold Waveformsfor TBSIS1and TBSIH1..........................................................49
19 OutputDelayand Output Float for TBSOV1 and TBSOF1 ........................................................50
20 OutputDelayand Output Float WaveformforTBSOV2and TBSOF2.......................................50
21 Input Setup and Hold WaveformforTBSIS2 and TBSIH2 .........................................................50
22 Riseand Fall TimeDeratingat 85 °C and Minimum VCC..........................................................51
23 ICC Active(Power Supply)vs. Frequency...................................................................................51
24 ICC Active(Thermal) vs.Frequency............................................................................................52
25 OutputDelayor Hold vs. Load Capacitance..............................................................................52
26 OutputDelayvs. Temperature...................................................................................................53
27 OutputHoldTimes vs.Temperature..........................................................................................53
28 OutputDelayvs. VCC ................................................................................................................53
29 ColdReset Waveform................................................................................................................54
30 WarmResetWaveform..............................................................................................................55
31 Entering ONCE Mode.................................................................................................................56
32 Non-Burst, Non-PipelinedRequestswithout WaitStates...........................................................57
33 Non-Burst, Non-PipelinedRead Request withWait States........................................................58
34 Non-Burst, Non-PipelinedWrite Request with WaitStates ........................................................59
35 Burst, Non-Pipelined Read Request without WaitStates, 32-BitBus........................................60
36 Burst, Non-Pipelined Read Request with WaitStates,32-Bit Bus.............................................61
37 Burst, Non-Pipelined Write Request without WaitStates,32-Bit Bus........................................62
38 Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus.............................................63
39 Burst, Non-Pipelined Read Request with WaitStates,16-Bit Bus.............................................64
40 Burst, Non-Pipelined Read Request with WaitStates,8-Bit Bus...............................................65
41 Non-Burst, Pipelined Read Request without WaitStates, 32-BitBus........................................66
42 Non-Burst, Pipelined Read Request with WaitStates,32-Bit Bus.............................................67
43 Burst, PipelinedRead Request without Wait States, 32-Bit Bus................................................68
44 Burst, PipelinedRead RequestwithWait States, 32-BitBus.....................................................69
45 Burst, PipelinedRead RequestwithWait States, 8-Bit Bus.......................................................70
46 Burst, PipelinedRead RequestwithWait States, 16-BitBus.....................................................71
47 Using External READY...............................................................................................................72
48 Terminating a Burstwith BTERM...............................................................................................73
49 BREQand BSTALL Operation ...................................................................................................74
50 BOFF Functional Timing. BOFF occursduring a burstor non-burstdata cycle.........................75
51 HOLD Functional Timing ............................................................................................................76
52 LOCK Delays HOLDA Timing.....................................................................................................77
53 FAIL Functional Timing...............................................................................................................77
54 A Summaryof Aligned and Unaligned Transfers for 32-Bit Regions..........................................78
55 A Summaryof Aligned and Unaligned Transfers for 32-Bit Regions (Continued)......................79
56 A Summaryof Aligned and Unaligned Transfers for 16-Bit Bus.................................................80

Datasheet5
Contents
57 ASummaryof Aligned and Unaligned Transfersfor8-Bit Bus...................................................81
58 Idle BusOperation......................................................................................................................82
59 BusStates..................................................................................................................................83
Tables
1 80960Hx Product Description.......................................................................................................9
2Fail CodesFor BIST(bit7 = 1)...................................................................................................12
3Remaining Fail Codes(bit 7 = 0)................................................................................................12
4 80960Hx Instruction Set .............................................................................................................13
5 80960HA/HD/HT Package Typesand Speeds...........................................................................14
6PinDescription Nomenclature....................................................................................................15
7 80960Hx ProcessorFamilyPinDescriptions..............................................................................16
8 80960Hx 168-Pin PGAPinout—Signal Name Order..................................................................22
9 80960Hx 168-Pin PGAPinout—Pin NumberOrder...................................................................24
10 80960Hx PQ4Pinout—Signal NameOrder................................................................................27
11 80960Hx PQ4Pinout—PinNumber Order.................................................................................29
13 80960Hx 168-Pin PGAPackage Thermal Characteristics.........................................................32
12 MaximumTA at VariousAirflowsin °C(PGAPackage Only).....................................................32
15 80960Hx 208-Pin PQ4Package ThermalCharacteristics..........................................................33
14 MaximumTA at VariousAirflowsin °C(PQ4Package Only)......................................................33
17 80960Hx DeviceID Model Types...............................................................................................35
18 DeviceID Version NumbersforDifferent Steppings...................................................................35
16 Fields of 80960Hx DeviceID......................................................................................................35
19 Absolute Maximum Ratings........................................................................................................37
20 Operating Conditions..................................................................................................................37
21 VDIFFSpecification for DualPowerSupply Requirements (3.3 V, 5 V)......................................39
22 80960Hx DC Characteristics ......................................................................................................40
23 80960Hx AC Characteristics.......................................................................................................42
25 80960Hx BoundaryScan TestSignal Timings...........................................................................44
24 ACCharacteristics Notes............................................................................................................44
26 80960Hx BoundaryScan Chain.................................................................................................84

Contents
6Datasheet
RevisionHistory
Date Revision History
September 2002 008
Formatted the datasheet in a new template.
In “32-BitParallel Architecture”onpage 1:
•Removed operating frequency of 16/32 (bus/core) from 80960HD.
•Removed operating frequency of 20/60 (bus/core) from 80960HT.
In Table 5“80960HA/HD/HTPackage Types and Speeds”on page 14:
•Removed core speed of 32 MHz and bus speed of 16MHz, and order
number A80960HD32-S-L2GGfrom the 168L PGA package, 80960HD
device.
•Removed core speed of 60 MHz and bus speed of 20MHz, and order
number A80960HT60 from the 168L PGApackage, 80960HTdevice.
•Removed core speed of 32 MHz and bus speed of 16MHz, and order
number FC80960HD32-S-L2GL from the 208L PQFPpackage,
80960HD device.
•Removed core speed of 60 MHz and bus speed of 20MHz, and order
number FC80960HT60-S-L2G2 from the 208L PQFPpackage,
80960HT device.
July 1998 007
In “32-BitParallel Architecture”onpage 1:
•Revised 1.2 Gbyte Internal Bandwidth(75 MHz)to1.28 Gbyte Internal
Bandwidth(80 MHz).
In Section 3.0, “Package Information”on page 14:
•Added paragraph two and Table 5“80960HA/HD/HT Package Types
and Speeds”on page 14.
In Table 7“80960Hx Processor Family Pin Descriptions”on page 16:
•Corrected minor typeset and spacing errors.
•BREQ;Revised description.
•ONCE; last sentence, changed ‘low’to ‘high’.
•TDIand TMS; removed last sentence stating, “Pull thispin low when
not in use.”
In Figure 2 “80960Hx 168-Pin PGA Pinout—View from Top (Pins Facing
Down)”on page 20:
•Added insert package marking diagram.
In Figure 4 “80960Hx 208-Pin PQ4 Pinout”on page 26:
•Added insert package marking diagram.
In Table 10 “80960Hx PQ4 Pinout—Signal Name Order”on page 27:
•Corrected TDO(‘O’was zero) and revised alphabetical ordering.
In Table 11 “80960Hx PQ4 Pinout—Pin Number Order”on page 29:
•Corrected TDO(‘O’was zero) and revised alphabetical ordering.
In Section 4.1, “AbsoluteMaximum Ratings”on page 37:
•Revised VCC toVCC5 for Voltage on Other Pins with respect toVSS.
In Section 4.5, “VCCPLL Pin Requirements”onpage 39:
•Added section.
In Table 22 “80960Hx DC Characteristics”on page 40:
•Added footnote (1) toILO notes columnfor TDOpin.
•Added footnote (10)toCIN, COUTand CI/Opin.

Datasheet7
Contents
July 1998
(continued) 007 (continued)
In Table 23 “80960Hx ACCharacteristics”on page 42:
•Added overbars where required.
•Modified TDVNH tolist separatespecifications for 3.3 V and 5 V.
•Modified TOV2, TOH2and TTVEL toreflect specific 80960HA, 80960HD
and 80960HT values.
In Figure 23 “ICC Active (Power Supply) vs.Frequency”on page 51:
•Changed ‘5’to ‘0’on the CLKIN Frequency axis.
In Figure 49 “BREQand BSTALL Operation”on page 74:
•Added figure and following text.
August1997 006 Fixed several font and format issues.
Date Revision History

Contents
8Datasheet
This pageintentionally leftblank.

80960HA/HD/HT
Datasheet9
1.0About ThisDocument
This documentdescribes the parametric performance ofIntel’s 80960Hx embedded superscalar
microprocessors. Detailed descriptions for functional topics, other than parametricperformance,
are published inthe i960®Hx MicroprocessorUser’s Guide (272484).
Inthis document, ‘80960Hx’and ‘i960 Hxprocessor’refer tothe productsdescribed inTable1.
Throughout this document, information thatisspecific to each is clearly indicated.
2.0Intel 80960Hx Processor
The Intel80960Hxprocessor provides new performance levelswhilemaintaining backward
compatibility (pin1andsoftware)with the i960 CA/CF processor.This newestmember ofthe
family of i960 32-bit,RISC-style, embedded processorsallows customerstocreate scalable
designsthat meet multiple price andperformance points.This is accomplishedby providing
processorsthat may run at the bus speed or faster using Intel’s clockmultiplyingtechnology
(see Table1).The 80960Hx coreis capable ofissuing 150 millioninstructionspersecond, usinga
sophisticated instructionscheduler that allows the processorto sustain a throughputoftwo
instructionsevery core clock, with a peak performance of three instructions per clock. The
80960Hx-series comprisesthree processors, which differ inthe ratio ofcoreclock speed toexternal
busspeed.
Figure 1. 80960Hx Block Diagram
Execution Unit
Programmable
BusController
Bus RequestQueues
Six-PortRegisterFile
32-bit Base Bus
Instruction Cache
128-BitCache Bus
Instruction Prefetch Queue
Interrupt Controller
Control
Address
Data
Memory-Side
Machine Bus
Register-Side
Machine Bus
MemoryRegion Configuration
Multiply/Divide Unit
Interrupt
Port
Address Generation Unit
Data Cache
16 Kbyte, Four-Way Set-Associative
8 Kbyte, Four-Way Set-Associative
Guarded Memory Unit
Timers
JTAG Port
Parallel InstructionScheduler
DataRAM- 2 Kbyte
RegisterCache- 5to 15sets
64-bit SRC1 Bus
64-bit SRC2 Bus
64-bitDSTBus
128-bit Load Bus
128-bit Store Bus
1.The80960Hx isnot “drop-in”compatibleinan 80960Cx-basedsystem.Customers may design systems thataccept either80960Hx or Cx
processors.
Table1. 80960Hx Product Description
ProductCoreVoltageOperating Frequency(bus/core)
80960HA 1x3.3V†25/25, 33/33, 40/40
80960HD 2x3.3V†25/50, 33/66, 40/80
80960HT 3x3.3V†25/75
†Processor inputsare 5 Vtolerant.

80960HA/HD/HT
10 Datasheet
In addition toexpanded clock frequency options,the 80960Hx provides essentialenhancementsfor
an emergingclassofhigh-performanceembedded applications. Features include a larger
instruction cache, data cache, and dataRAM than any other 80960 processor todate. Italsoboasts
a 32-bitdemultiplexed and pipelined burst bus, fastinterrupt mechanism,guarded memory unit,
wait state generator,dual programmable timers,ONCE and IEEE 1149.1-compliantboundary scan
test and debug support,and newinstructions.
2.1The i960®Processor Family
The i960®processorfamily isa 32-bit RISC architecture created byIntel to serve the needsof
embedded applications. The embedded market includes applications as diverse as industrial
automation,avionics,image processing, graphics and communications.
Becauseall members of the i960processor familyshare a common core architecture, i960
applications are code-compatible.Each new processor in the family adds its own special set of
functionsto the core to satisfy the needsofa specific application orrange ofapplications in the
embedded market.
2.2Key 80960Hx Features
2.2.1Execution Architecture
Independent instructionpathsinsidethe processorallow the execution ofmultiple, out-of-sequence
instructionsperclock.Register andresource scoreboardinginterlocksmaintain the logical integrity
ofsequential instructionsthat are beingexecuted in parallel. Tosustain executionofmultiple
instructionsin each clockcycle, the processordecodesmultiple instructionsinparallel and
simultaneouslyissues these instructions toparallelprocessing units. The various processing units
are then able to independently accessinstruction operandsinparallel from a common register set.
LocalRegister Cache integrated on-chip provides automaticregistermanagementon call/return
instructions. Upon a callinstruction, the processor allocates a set of local registers for the called
procedure, then stores theregisters for the previous procedure in the on-chip register cache. As
additional procedures are called,the cache stores the associated registers such that themostrecently
calledprocedure isthe first available by the next return (ret) instruction. The processor may store up
tofifteen register sets, after whichthe oldestsets are stored (spilled)intoexternal memory.
The 80960Hx supportsthe 80960 architecturally-defined branch prediction mechanism. This
allowsmanybranches toexecutewith no pipeline break. With the 80960Hx’sefficient pipeline, a
branch may take as few as zero clocks to execute. The maximum penaltyfor an incorrect prediction
istwo core clocks.
2.2.2Pipelined, BurstBus
A32-bit high performance buscontroller interfaces the 80960Hxcoreto the external memoryand
peripherals. The BusControl Unit features a maximum transfer rate of 160 Mbytes per second (ata
40 MHz external bus clockfrequency). A keyadvantage ofthis design is its versatility.The user
may independentlyprogram the physical and logical attributes of system memory.Physical
attributes includewaitstate profile, bus width,andparity.Logical attributes includecacheability
andBig orLittle Endian byte order.Internally programmable waitstates and16separately
configurable physical memory regionsallow the processor to interface with a variety of memory

80960HA/HD/HT
Datasheet11
subsystemswith minimumsystem complexity. Toreduce the effect ofwait states, thebusdesignis
decoupled fromthe core. This lets the processorexecute instructionswhile the busperforms
memory accesses independently.
The BusController’skey features include:
•Demultiplexed,Burst Busto support mostefficient DRAM access modes
•Address Pipeliningto reduce memorycost while maintaining performance
•32-,16-and8-bit modes to facilitate I/O interfacing
•Full internal wait state generation to reduce system cost
•Little andBig Endian support
•Unaligned Accesssupportimplemented in hardware
•Three-deep request queue to decouplethe busfrom the core
•Independent physical and logical addressspace characteristics
2.2.3On-Chip Caches and DataRAM
As shownin Figure1, the 80960Hx provides generouson-chip cache and storage features to
decouple CPU execution from the external bus.The processorincludes a 16 Kbyte instruction
cache, an 8 Kbyte data cache and 2 Kbytes of Data RAM. The caches are organized as 4-way set
associative. Stores that hit the data cache are written through to memory. The data cache performs
write allocation on cache misses. A fifteen-set stack framecache allows the processor to rapidly
allocate and deallocate local registers.All of the on-chip RAM sustainsa 4-word(128-bit) access
every clock cycle.
2.2.4Priority Interrupt Controller
The interrupt unit provides the mechanism forthe lowlatencyandhigh throughput interrupt
service essential forembedded applications. A priority interrupt controller provides full
programmability of240 interruptsources witha typical interrupt taskswitch (latency)time of17
coreclocks. The controller supports 31 priority levels. Interrupts are prioritized and signaled within
10 core clocks of the request. When the interrupt has a higher prioritythan the processor priority,
the context switch to the interrupt routine wouldtypically completein anothersevenbusclocks.
External agentspost interruptsthrough the 8-bit external interrupt port. The Interruptunit also
handles the two internal sources fromthe Timers. Interrupts maybelevel- oredge-triggered.
2.2.5Guarded Memory Unit
The GuardedMemoryUnit (GMU) provides memoryprotectionwithout the address translation
found inMemoryManagement Units. TheGMUcontainstwo memoryprotection schemes: one
prevents illegal memory accesses, the other detects memory accessviolations.Bothsignal a fault
to the processor.The programmable protection modesare: user read, write orexecute; and
supervisorread, write or execute.

80960HA/HD/HT
12 Datasheet
2.2.6Dual Programmable Timers
The processor provides twoindependent32-bittimers,withfour programmableclock rates.The
userconfigures the timers through the Timer Unit registers.These registersare memory-mapped
withinthe 80960Hx, addressable on32-bitboundaries. The timers have a single-shot mode and
auto-reloadcapabilities forcontinuousoperation. Each timer has an independent interrupt request
tothe processor’s interrupt controller.
2.2.7Processor Self Test
When a system error is detected, the FAIL pinis asserted, a fail codemessage is driven ontothe
addressbus, and the processorstopsexecution at the pointof failure. The only way to resume
normal operation is to perform a RESET operation. BecauseSystem Error generation may occur
sometimeafter the busconfidence test andeven afterinitializationduring normal processor
operation,theFAIL pinis HIGH (logic “1”) before the detection of a System Error.
The processor usesonly one read bus-transaction to signal the fail codemessage; the addressofthe
bustransactionis the fail codeitself. The fail codeis ofthe form: 0xfeffffnn;bits6 to0 contain a
maskrecordingthe possible failures. Bit 7,when set to 1, indicates that the mask containsfailures
fromthe internal Built-InSelf-Test (BIST); when 0, the mask indicates otherfailures.
Ignorereservedbits0 and 1.Also ignorebits5 and 6 whenbit 7 isclear(=0).
Themask isshown in Table2 and Table3.
Table 2. Fail CodesFor BIST (bit 7 = 1)
BitWhen Set
6On-chip Data-RAM failure detected by BIST.
5Internal Microcode ROMfailure detected byBIST.
4Instruction cache failure detected by BIST.
3Data cache failure detected by BIST.
2Local-register cache or processor corefailure detected by BIST.
1Reserved. Alwayszero.
0Reserved. Alwayszero.
Table 3. Remaining Fail Codes(bit7 = 0)
BitWhen Set
6Reserved. Alwaysone.
5Reserved. Alwaysone.
4Adatastructure within the IMIis notaligned toa word boundary.
3ASystem Error during normaloperation has occurred.
2The Bus Confidence test has failed.
1Reserved. Alwayszero.
0Reserved. Alwayszero.

80960HA/HD/HT
Datasheet13
2.3Instruction Set Summary
Table4 summarizes the 80960Hx instruction setby logical groupings.
Table 4. 80960Hx InstructionSet
DataMovementArithmeticLogical Bit / Bit Field/ Byte
Load
Store
Move
Load Address
Conditional Select2
Add
Subtract
Multiply
Divide
Remainder
Modulo
Shift
Extended Shift
Extended Multiply
Extended Divide
Add with Carry
Subtract with Carry
Rotate
Conditional Add2
Conditional Subtract2
And
Not And
And Not
Or
ExclusiveOr
Not Or
Or Not
Nor
ExclusiveNor
Not
Nand
SetBit
Clear Bit
Not Bit
AlterBit
Scan For Bit
Span OverBit
Extract
Modify
Scan Bytefor Equal
ByteSwap2
Comparison Branch Call/Return Fault
Compare
Conditional Compare
Compare and Increment
Compare and Decrement
Compare Byte2
Compare Short2
Test Condition Code
Check Bit
UnconditionalBranch
Conditional Branch
Compare and Branch
Call
Call Extended
Call System
Return
Branch and Link
Conditional Fault
Synchronize Faults
Debug ProcessorMgmt AtomicCache Control
ModifyTrace Controls
Mark
Force Mark
Flush LocalRegisters
ModifyArithmetic Controls
ModifyProcess Controls
Interrupt Enable/ Disable1, 2
System Control1
AtomicAdd
AtomicModify
Instruction Cache
Control1, 2
DataCache Control1, 2
NOTES:
1. 80960Hx extensions tothe 80960 core instruction set.
2. 80960Hx extensions tothe 80960Cx instruction set.

80960HA/HD/HT
14 Datasheet
3.0 Package Information
Thissection describes the pins, pinoutsand thermal characteristics for the 80960Hxinthe 168-pin
ceramic Pin Grid Array (PGA)package, 208-pin PowerQuad2* (PQ4). For complete package
specificationsandinformation, see the Intel Packaging Handbook (Order# 240800).
The 80960HA/HD/HT is offered with eight speeds and two package types (Table5).Both the
168-pinceramicPin GridArray (PGA)and the 208-pin PowerQuad2* (PQ4)devices are specified
for operation at VCC =3.3 V±0.15 Vover a case temperature range of0 °C to 85 °C.
Table 5. 80960HA/HD/HT Package Types andSpeeds
Package/Name Device Core Speed
(MHz)Bus Speed (MHz)Order #
168L PGA
80960HA
25 A80960HA25 S L2GX
33 A80960HA33 S L2GY
40 A80960HA40 S L2GZ
80960HD
50 25 A80960HD50 S L2GH
66 33 A80960HD66 S L2GJ
80 40 A80960HD80 S L2GK
80960HT 75 25 A80960HT75 S L2GP
208L PQFP
(also known as PQ4)
80960HA
25 FC80960HA25 S L2GU
33 FC80960HA33 S L2GV
40 FC80960HA40 S L2GW
80960HD
50 25 FC80960HD50 S L2GM
66 33 FC80960HD66 S L2GN
80 40 FC80960HD80 S L2LZ
80960HT 75 25 FC80960HT75 S L2GT

80960HA/HD/HT
Datasheet15
3.1 PinDescriptions
Thissection defines the 80960Hx pins. Table6 presents the legend forinterpreting the pin
descriptionsin Table7. All pins float while the processor is inthe ONCE mode, except TDO,
which may bedriven active according to normal JTAG specifications.
Table6. Pin Description Nomenclature
SymbolDescription
IInput only pin.
OOutput only pin.
I/OPin may be input or output.
-Pin must be connected as indicated forproper device functionality.
S(E)Synchronous edge sensitive input. This input mustmeet the setup and hold times relative to
CLKIN toensure proper operation of the processor.
S(L) Synchronous level sensitive input. This input must meet the setup and hold times relative to
CLKIN toensure proper operation of the processor.
A(E)Asynchronous edge-sensitive input.
A(L) Asynchronous level-sensitive input.
H(...)
While the processor bus is in the HOLD state (HOLDA asserted), the pin:
H(1) isdriven toVCC
H(0) isdriven toVSS
H(Z)floats
H(Q)continues tobe a valid output
B(...)
While the processor is in the bus backoff state(BOFF asserted), the pin:
B(1) is driven toVCC
B(0) is driven toVSS
B(Z)floats
B(Q)continues tobea valid output
R(...)
While the processor’s RESETpin is asserted, the pin:
R(1) isdriven toVCC
R(0) isdriven toVSS
R(Z)floats
R(Q)continues tobe a valid output

80960HA/HD/HT
16 Datasheet
Table 7. 80960HxProcessor Family Pin Descriptions (Sheet1 of 4)
Name TypeDescription
A31:2
O
H(Z)
B(Z)
R(Z)
ADDRESS BUScarries the upper 30 bitsof the physical address. A31 is the most
significant address bit and A2 isthe least significant.During a bus access, A31:2
identify all external addresses toword (4-byte) boundaries. The byteenable
signals indicatethe selected bytein each word. During burst accesses, A3and
A2 increment toindicatesuccessive addresses.
D31:0
I/O
S(L)
H(Z)
B(Z)
R(Z)
DATABUS carries 32, 16, or 8-bit data quantitiesdepending on bus width
configuration. The least significant bit of the data is carried on D0 and the most
significant on D31. The lower eight data lines (D7:0) are used when the bus is
configured for 8-bit data. When configured for16-bit data, D15:0 are used.
DP3:0
I/O
S(L)
H(Z)
B(Z)
R(Z)
DATAPARITY carries parityinformation for the data bus.Each paritybit is
assigned a group ofeightdata bus pins asfollows:
DP3 generates/checks parityfor D31:24
DP2 generates/checks parityfor D23:16
DP1 generates/checks parityfor D15:8
DP0 generates/checks parityfor D7:0
Parityinformation is generated for a processor writecycle and is checked for a
processor read cycle.Paritychecking and polarity are programmable. Parity
generation/checking isonly performed for the size of the data accessed.
PCHK
O
H(Q)
B(Q)
R(1)
PARITYCHECK indicates the result of a paritycheck operation. An asserted
PCHK indicates that the previous bus read access resulted in a paritycheck error.
BE3:0
O
H(Z)
B(Z)
R(1)
BYTE ENABLESselect which of the four bytes addressed by A31:2 are active
during a bus access. Byteenable encoding is dependent on the bus width of the
memory region accessed:
32-bit bus:
BE3enables D31:24
BE2enables D23:16
BE1enables D15:8
BE0enables D7:0
16-bit bus:
BE3becomes ByteHigh Enable (enables D15:8)
BE2is not used (stateis undefined)
BE1becomes Address Bit1 (A1)
BE0becomes ByteLow Enable (enables D7:0)
8-bit bus:
BE3is not used (stateis undefined)
BE2is not used (stateis undefined)
BE1Address Bit 1 (A1)
BE0Address Bit 0 (A0)
W/R
O
H(Z)
B(Z)
R(0)
WRITE/READ is low for read accesses and high for write accesses.
W/Rbecomes valid during the address phase of a bus cycle and remains valid
until the end of the cyclefornon-pipelined accesses. For pipelined accesses, W/
Rchanges state when the next address is presented.
0= Read
1= Write
D/C
O
H(Z)
B(Z)
R(0)
DATA/CODEindicates that a bus access is a data accessor an instruction
access. D/Chas the same timing as W/R.
0 = Code
1 = Data

80960HA/HD/HT
Datasheet17
SUP
O
H(Z)
B(Z)
R(1)
SUPERVISOR ACCESS indicates whether the current bus access originates
from a requestissued while in supervisor mode or user mode. SUPmay be used
by the memory subsystem toisolate supervisor code and data structures from
non-supervisor access.
0 = Supervisor Mode
1 = User Mode
ADS
O
H(Z)
B(Z)
R(1)
ADDRESS STROBE indicates a valid address and the start of a new bus access.
ADSis asserted for the firstclock of a bus access.
READYI
S(L)
READY,when enabled for a memory region, is asserted by the memory
subsystemtoindicatethe completion of a data transfer.READYis used to
indicatethat read data on the bus is valid, or that a write transfer has completed.
READYworks in conjunction with the internal wait state generator to
accommodate various memory speeds.READYis sampled after any
programmed wait states:
During each data cycle of a burst access
During the data cycleof a non-burstaccess
BTERMI
S(L)
BURST TERMINATE, when enabled for a memory region, is asserted by the
memory subsystem toterminate a burst access in progress.When BTERMis
asserted, the current burst accessisterminated and another address cycle
occurs.
WAIT
O
H(Z)
B(Z)
R(1)
WAITindicatesthe status of the internalwait-stategenerator. WAITis asserted
when the internal waitstate generator generates NWAD, NRAD, NWDDand NRDD
waitstates. WAITmay be used toderive a write data strobe.
BLAST
O
H(Z)
B(Z)
R(1)
BURST LASTindicates the last transfer in a bus access. BLASTis asserted in
the lastdata transfer of burst and non-burst accesses after the internal wait-state
generatorreaches zero. BLASTremains activeas long as waitstates are inserted
through the READYpin. BLASTbecomes inactive after the finaldata transfer ina
bus cycle.
DT/R
O
H(Z)
B(Z)
R(0)
DATATRANSMIT/RECEIVEindicates direction fordata transceivers. DT/Ris
used with DENtoprovide controlfor data transceivers connected tothe databus.
DT/R is drivenlow toindicatethe processor expectsdata (aread cycle). DT/Ris
driven high when the processor is “transmitting”data(a store cycle). DT/Ronly
changes state when DEN is high.
0 = DataReceive
1 = DataTransmit
DEN
O
H(Z)
B(Z)
R(1)
DATAENABLE indicatesdata transfer cycles during a bus access.DENis
asserted at the start of the first data cycle in a bus accessand de-asserted at the
end of the last data cycle. DEN remains asserted for an entire bus request, even
when that request spans several bus accesses. For example, a ldq instruction
starting at an unaligned quad word boundary is one bus requestspanning at least
two bus accesses. DENremains asserted throughout all the accesses (including
ADSstates) and de-asserts when the Iqd instruction requestis satisfied. DEN is
used with DT/Rtoprovide control fordata transceivers connected tothe data bus.
DENremains asserted for sequential reads from pipelined memory regions.
LOCK
O
H(Z)
B(Z)
R(1)
BUS LOCK indicates that an atomic read-modify-writeoperation is inprogress.
LOCK may be used bythe memory subsystem toprevent external agents from
accessing memorythat is currently involved inan atomic operation (e.g., a
semaphore). LOCK is asserted inthe first clock of anatomic operation and de-
asserted when BLASTis deasserted in the last bus cycle.
Table 7. 80960Hx ProcessorFamily PinDescriptions(Sheet 2 of4)
Name TypeDescription

80960HA/HD/HT
18 Datasheet
HOLD I
S(L)
HOLDREQUESTsignals that an external agent requestsaccess tothe
processor’saddress, data, and control buses. When HOLD is asserted, the
processor:
Completes the current bus request.
Asserts HOLDA and floatsthe address, data, and control buses.
When HOLD is deasserted, the HOLDA pin is deasserted and the processor
reassumes control of the address, data, and controlpins.
HOLDA
O
H(1)
B(0)
R(Q)
HOLDACKNOWLEDGEindicates toan external masterthat the processor has
relinquished control of the bus. The processor grants HOLD requestsand enters
the HOLDA state while the RESETpin isasserted.
HOLDA is never granted while LOCK is asserted.
BOFF I
S(L)
BUS BACKOFF forces the processor toimmediately relinquish control of the bus
on the next clock cycle. When READY/BTERMisenabled and:
When BOFF isasserted, the address, data, and controlbuses are floated on the
next clock cycleand the current accessis aborted.
When BOFF isdeasserted, the processor resumes by regenerating the aborted
bus access.
See Figure 16 on page 48 forBOFF timing requirements.
BREQ
O
H(Q)
B(Q)
R(0)
BUS REQUESTindicatesthat a bus request is pending in the bus controller.
BREQdoes not indicatewhether or not the processor is stalled. See BSTALL for
processor stall status.BREQ may be used with BSTALL toindicatetoan external
bus arbiterthe processor’s bus ownership requirements.
BSTALL
O
H(Q)
B(Q)
R(0)
BUS STALL indicates that the processor has stalled pending the result of a
requestinthe bus controller. When BSTALL isasserted, the processor must
regain bus ownership tocontinue processing (i.e., it may no longer execute
strictly out of on-chip cache memory).
CT3:0
O
H(Z)
B(Z)
R(Z)
CYCLE TYPE indicatesthe type of bus cycle currently being started or processor
state. CT3:0 encoding follows:
Cycle TypeADSCT3:0
Program-initiated accessusing 8-bit bus00000
Program-initiated accessusing 16-bit bus00001
Program-initiated accessusing 32-bit bus00010
Event-initiated accessusing 8-bit bus 00100
Event-initiated accessusing 16-bitbus 00101
Event-initiated accessusing 32-bitbus 00110
Reserved 00X11
Reserved for future products01XXX
Reserved 1XXXX
XINT7:0I
A(E)
A(L)
EXTERNAL INTERRUPTpins are used torequestinterrupt service. These pins
may be configured in three modes:
Dedicated Mode: Each pin is assigned a dedicated interruptlevel. Dedicated
inputsmay be programmed to be level (low or high) or edge (rising or falling)
sensitive.
Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt
pins are levelsensitive inthismode.
Mixed Mode: The XINT7:5pins act as dedicated sources and the XINT4:0pins
act as the five most significant bitsof a vectored source.The least significant bits
of the vectored source are set to“010”internally.
NMI I
A(E)NON-MASKABLE INTERRUPTcauses a non-maskable interruptevent tooccur.
NMI is the highest priorityinterrupt source. NMIisfalling edge triggered.
Table 7. 80960HxProcessor Family Pin Descriptions (Sheet3 of 4)
Name TypeDescription

80960HA/HD/HT
Datasheet19
CLKINI
CLOCK INPUTprovides the timebase for the 80960Hx. All internal circuitry is
synchronized toCLKIN. All input and output timings are specified relative to
CLKIN.
For the 80960HD, the 2x internal clock is derived by multiplying the CLKIN
frequency by two. For the 80960HT, the 3x internal clock isderived by multiplying
the CLKIN frequency by three.
RESETI
A(L)
RESETforces the device intoreset. RESETcauses all external and internal
signals toreturn totheir reset state (when defined). The rising edge of RESET
startsthe processor boot sequence.
STESTI
S(L) SELF TEST,whenasserted during the rising edge of RESET,causes the
processor toexecute its built in self-test.
FAIL
O
H(Q)
B(Q)
R(0)
FAILindicates a failure of the processor’sbuilt-in self-testperformed during
initialization. FAILis asserted immediately out of reset and toggles during self-test
toindicatethe status of individual tests. When self-testpasses, FAILisde-
asserted and the processor branches tothe user’s initialization code. When self-
test fails, theFAIL pin asserts and the processor ceases execution.
ONCE I
ON-CIRCUITEMULATION control: the processor samples this pin during reset.
When it isasserted low at the end of reset, the processor enters ONCE mode. In
ONCEmode, the processor stopsall clocks and floats all output pins except the
TDOpin. ONCE uses an internal pull-up resistor; see RPU definition in Table 22,
“80960Hx DC Characteristics”on page 40.Pull thispin high when not in use.
TCK ITEST CLOCK provides the clocking function for IEEE 1149.1 Boundary Scan
testing.
TDI I TEST DATAINPUTis the serial input pinfor IEEE 1149.1 Boundary Scan testing. TDIuses an internalpull-up resistor; see RPU definition inTable 22, “80960Hx DC
Characteristics”on page 40.
TDO OTESTDATAOUTPUT is the serial output pin for IEEE 1149.1 Boundary Scan
testing. ONCE does not disable this pin.
TRST I
TEST RESETasynchronouslyresetsthe Test Access Port (TAP) controller.TRST
must be held low at least 10,000 clock cycles after power-up. One method is to
provide TRSTwith a separatepower-on-reset circuit. TRST includes aninternal
pull-up resistor; see RPU definition in Table 22, “80960Hx DC Characteristics”on
page 40.Pull thispin lowwhen not in use.
TMSI
TEST MODESELECTis sampled at the rising edge of TCK. TCK controls the
sequence of TAP controller state changes for IEEE 1149.1 Boundary Scan
testing. TMSuses an internal pull-up resistor; see RPU definition in Table 22,
“80960Hx DC Characteristics”on page 40.
VCC5 I5VREFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O buffers.Connect thissignal to+5 Vfor use withinputs which exceed3.3V.When
all inputsare from 3.3Vcomponents,connect this signal to3.3V.
VCCPLL IPLL VOLTAGE isthe +3.3VDC analog input for the PLL.
VOLDET O
VOLTAGE DETECT signal allows external system logic todistinguish between a
5V80960Cx processor and the 3.3V80960Hx processor.This signal is active
low for a 3.3V80960Hx (it is high impedance for 5 V80960Cx). This pin is
available only on the PGA version.
0 = 80960Hx
1 = 80960Cx
Table 7. 80960Hx ProcessorFamily PinDescriptions(Sheet 4 of4)
Name TypeDescription

80960HA/HD/HT
20 Datasheet
3.2 80960Hx Mechanical Data
3.2.180960Hx PGA Pinout
Figure2 depictsthe complete80960HxPGApinout as viewed from the top side of the component
(i.e., pins facing down). Figure3 shows the complete80960HxPGA pinoutas viewed from the
pin-side ofthe package (i.e., pins facing up). Table9 liststhe 80960Hxpin names withpackage
location. See Section 4.3, “Recommended Connections”onpage 38 for specifications and
recommended connections.
Figure 2. 80960Hx 168-Pin PGAPinout—Viewfrom Top (Pins Facing Down)
D5D7D8D9D11D12D13D15D16D17D19D21D24D25
D2D4D6VCC D10VCC VCC D14VCC D18D20D23D27D29
NCD0VCC VSS VSS VSS VSS VSS VSS VCC D22D31READYD26
D28BTERM
HOLDA
D30HOLD
BE3
VCC
ADSBE2
VSS VCC
BE1
VSS VCC
BLAST
VSS
BE0
DEN
VSS VCC
W/R
VSS VCC
DT/R
A29LOCK
SUPWAITBSTALL
A28
A30BREQD/C
D3
D1
ONCE
VSS
VCC5
VCC
VSS
VSS
VSS
VSS
VSS
CLKIN
VCC
VSS
BOFF
STEST
DP1
DP3
TCK
TMS
VCC
PCHK
VCC
VCCPLL
VCC
NC
NC
VCC
VSS
FAIL
DP0
DP2
VOLDET
TRST
TDI
TDO
NC
NC
CTO
CT2
CT3
CT1
VSS
A2
VCC
A22A25
A20VSS
A3A5
NMIVCC VSS VSS VSS VSS VSS A24A31A26
A4VCC
A6A8A9A10A11A12A14A15A17A18
VCC VCC VCC A13VCC A16A19A21A23A27A7 XINT6
XINT7
XINT4
XINT3
XINT5
XINT0
RESET
XINT2
XINT1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
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3
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