Intel E5345 - Xeon 2.33 GHz 8M L2 Cache 1333MHz FSB LGA771 Active Quad-Core... User manual

Order Number: 315569, Revision: 001
Quad-Core Intel® Xeon® Processor
5300 Series
Datasheet
November 2006

2Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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The Quad-Core Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting
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details on Execute Disable can be found at http://www3.intel.com/cd/ids/developer/asmo-na/eng/149308.htm.
Intel® Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and
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Copyright © 2006, Intel Corporation

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 3
Contents
1 Introduction.................................................................................................................9
1.1 Terminology ..................................................................................................... 11
1.2 State of Data .................................................................................................... 13
1.3 References ....................................................................................................... 13
2 Electrical Specifications ............................................................................................... 15
2.1 Front Side Bus and GTLREF ................................................................................ 15
2.2 Power and Ground Lands.................................................................................... 16
2.3 Decoupling Guidelines........................................................................................ 16
2.3.1 VCC Decoupling...................................................................................... 16
2.3.2 VTT Decoupling ...................................................................................... 16
2.3.3 Front Side Bus AGTL+ Decoupling ............................................................ 17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ....................................... 17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0]) .................................. 18
2.4.2 PLL Power Supply ................................................................................... 19
2.5 Voltage Identification (VID) ................................................................................ 19
2.6 Reserved, Unused, or Test Signals....................................................................... 21
2.7 Front Side Bus Signal Groups.............................................................................. 22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals .................................... 24
2.9 Test Access Port (TAP) Connection....................................................................... 24
2.10 Platform Environmental Control Interface (PECI) DC Specifications........................... 24
2.10.1 DC Characteristics .................................................................................. 24
2.10.2 Input Device Hysteresis .......................................................................... 25
2.11 Mixing Processors.............................................................................................. 26
2.12 Absolute Maximum and Minimum Ratings ............................................................. 26
2.13 Processor DC Specifications ................................................................................ 27
2.13.1 Flexible Motherboard Guidelines (FMB) ...................................................... 27
2.13.2 VCC Overshoot Specification .................................................................... 33
2.13.3 Die Voltage Validation ............................................................................. 34
2.14 AGTL+ FSB Specifications................................................................................... 34
3 Mechanical Specifications............................................................................................. 39
3.1 Package Mechanical Drawings ............................................................................. 39
3.2 Processor Component Keepout Zones................................................................... 43
3.3 Package Loading Specifications ........................................................................... 43
3.4 Package Handling Guidelines............................................................................... 44
3.5 Package Insertion Specifications.......................................................................... 44
3.6 Processor Mass Specifications ............................................................................. 44
3.7 Processor Materials............................................................................................ 44
3.8 Processor Markings............................................................................................ 45
3.9 Processor Land Coordinates ................................................................................ 45
4 Land Listing ............................................................................................................... 49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments ........................... 49
4.1.1 Land Listing by Land Name ...................................................................... 49
4.1.2 Land Listing by Land Number................................................................... 60
5 Signal Definitions ....................................................................................................... 71
5.1 Signal Definitions .............................................................................................. 71
6 Thermal Specifications ................................................................................................ 79
6.1 Package Thermal Specifications........................................................................... 79
6.1.1 Thermal Specifications ............................................................................ 79
6.1.2 Thermal Metrology ................................................................................. 83
6.2 Processor Thermal Features................................................................................ 84

4Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
6.2.1 Thermal Monitor Features ........................................................................84
6.2.2 Thermal Monitor (TM1) ............................................................................84
6.2.3 Thermal Monitor 2 ..................................................................................85
6.2.4 On-Demand Mode...................................................................................86
6.2.5 PROCHOT# Signal ..................................................................................87
6.2.6 FORCEPR# Signal ...................................................................................87
6.2.7 THERMTRIP# Signal ................................................................................88
6.3 Platform Environment Control Interface (PECI) ......................................................88
6.3.1 Introduction...........................................................................................88
6.3.2 PECI Specifications .................................................................................89
7 Features ....................................................................................................................91
7.1 Power-On Configuration Options ..........................................................................91
7.2 Clock Control and Low Power States .....................................................................91
7.2.1 Normal State .........................................................................................92
7.2.2 HALT or Extended HALT State...................................................................92
7.2.3 Stop-Grant State ....................................................................................94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant
Snoop State...........................................................................................94
7.3 Enhanced Intel SpeedStep® Technology...............................................................95
8 Boxed Processor Specifications .....................................................................................97
8.1 Introduction......................................................................................................97
8.2 Mechanical Specifications ....................................................................................99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK).............................................99
8.2.2 Boxed Processor Heat Sink Weight .......................................................... 107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink
Support (CEK) ...................................................................................... 107
8.3 Electrical Requirements .................................................................................... 107
8.3.1 Fan Power Supply (Active CEK)............................................................... 107
8.3.2 Boxed Processor Cooling Requirements.................................................... 108
8.4 Boxed Processor Contents................................................................................. 109
9 Debug Tools Specifications ......................................................................................... 111
9.1 Debug Port System Requirements ...................................................................... 111
9.2 Target System Implementation.......................................................................... 111
9.2.1 System Implementation......................................................................... 111
9.3 Logic Analyzer Interface (LAI) ........................................................................... 111
9.3.1 Mechanical Considerations ..................................................................... 112
9.3.2 Electrical Considerations ........................................................................ 112

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 5
Figures
2-1 Input Device Hysteresis ..................................................................................... 25
2-2 Quad-Core Intel® Xeon® Processor E5300 Series Load Current versus Time............. 29
2-3 Quad-Core Intel® Xeon® Processor X5300 Series Load Current versus Time ............ 30
2-4 Quad-Core Intel® Xeon® Processor E5300 Series VCC Static and
Transient Tolerance Load Lines........................................................................... 31
2-5 Quad-Core Intel® Xeon® Processor X5300 Series VCC Static and
Transient Tolerance Load Lines........................................................................... 32
2-6 VCC Overshoot Example Waveform...................................................................... 34
2-7 Electrical Test Circuit ......................................................................................... 36
2-8 Differential Clock Waveform................................................................................ 36
2-9 Differential Clock Crosspoint Specification............................................................. 37
3-1 Processor Package Assembly Sketch .................................................................... 39
3-2 Processor Package Drawing (Sheet 1 of 3) ............................................................ 40
3-3 Processor Package Drawing (Sheet 2 of 3) ............................................................ 41
3-4 Processor Package Drawing (Sheet 3 of 3) ............................................................ 42
3-5 Processor Top-side Markings (Example)................................................................ 45
3-6 Processor Land Coordinates, Top View.................................................................. 46
3-7 Processor Land Coordinates, Bottom View............................................................. 47
6-1 Quad-Core Intel® Xeon® Processor E5300 Series Thermal Profile ........................... 81
6-2 Quad-Core Intel® Xeon® Processor X5300 Series Thermal Profiles .......................... 82
6-3 Case Temperature (TCASE) Measurement Location ................................................ 84
6-4 Thermal Monitor 2 Frequency and Voltage Ordering ............................................... 86
6-5 PECI Topology .................................................................................................. 88
6-6 Conceptual Fan Control Diagram For A PECI-Based Platform.................................... 89
7-1 Stop Clock State Machine ................................................................................... 93
8-1 Boxed Quad-Core Intel® Xeon® Processor 5300 Series 1U Passive/3U+
Active Combination Heat Sink (With Removable Fan) ............................................. 97
8-2 Boxed Quad-Core Intel® Xeon® Processor 5300 Series 2U Passive Heat Sink ........... 98
8-3 2U Passive Quad-Core Intel® Xeon® Processor 5300 Series Processor
Thermal Solution (Exploded View) ....................................................................... 98
8-4 Top Side Board Keepout Zones (Part 1) .............................................................. 100
8-5 Top Side Board Keepout Zones (Part 2) .............................................................. 101
8-6 Bottom Side Board Keepout Zones..................................................................... 102
8-7 Board Mounting-Hole Keepout Zones ................................................................. 103
8-8 Volumetric Height Keep-Ins .............................................................................. 104
8-9 4-Pin Fan Cable Connector (For Active CEK Heat Sink) ......................................... 105
8-10 4-Pin Base Board Fan Header (For Active CEK Heat Sink)...................................... 106
8-11 Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution ....................... 108

6Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Tables
1-1 Quad-Core Intel® Xeon® Processor 5300 Series Features.......................................10
2-1 Core Frequency to FSB Multiplier Configuration ......................................................18
2-2 BSEL[2:0] Frequency Table .................................................................................18
2-3 Voltage Identification Definition ...........................................................................20
2-4 Loadline Selection Truth Table for LL_ID[1:0] ........................................................21
2-5 Market Segment Selection Truth Table for MS_ID[1:0] ...........................................21
2-6 FSB Signal Groups .............................................................................................22
2-7 AGTL+ Signal Description Table ...........................................................................23
2-8 Non AGTL+ Signal Description Table.....................................................................23
2-9 Signal Reference Voltages...................................................................................24
2-10 PECI DC Electrical Limits.....................................................................................25
2-11 Processor Absolute Maximum Ratings ...................................................................26
2-12 Voltage and Current Specifications .......................................................................27
2-13 VCC Static and Transient Tolerance ......................................................................30
2-14 AGTL+ Signal Group Specifications.......................................................................32
2-15 CMOS Signal Input/Output Group and TAP Signal Group DC Specifications.................33
2-16 Open Drain Output Signal Group DC Specifications .................................................33
2-17 VCC Overshoot Specifications ..............................................................................33
2-18 AGTL+ Bus Voltage Definitions ............................................................................35
2-19 FSB Differential BCLK Specifications .....................................................................35
3-1 Package Loading Specifications............................................................................43
3-2 Package Handling Guidelines ...............................................................................44
3-3 Processor Materials ............................................................................................44
4-1 Land Listing by Land Name .................................................................................49
4-2 Land Listing by Land Number ..............................................................................60
5-1 Signal Definitions...............................................................................................71
6-1 Quad-Core Intel® Xeon® Processor E5300 Series Thermal Specifications..................80
6-2 Quad-Core Intel® Xeon® Processor E5300 Series Thermal Profile Table ...................81
6-3 Quad-Core Intel® Xeon® Processor X5300 Series Thermal Specifications .................82
6-4 Quad-Core Intel® Xeon® Processor X5300 Series Thermal Profile A Table ................83
6-5 Quad-Core Intel® Xeon® Processor X5300 Series Thermal Profile B Table ................83
6-6 GetTemp0() and GetTemp1() Error Codes .............................................................90
7-1 Power-On Configuration Option Lands...................................................................91
7-2 Extended HALT Maximum Power ..........................................................................93
8-1 PWM Fan Frequency Specifications for 4-Pin Active CEK Thermal Solution................ 108
8-2 Fan Specifications for 4-Pin Active CEK Thermal Solution....................................... 108
8-3 Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution........................ 108

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 7
Revision History
§
Document
Number Revision Description Date
315569 -001 Initial Release November 2006

8Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 9
Introduction
1Introduction
The Quad-Core Intel® Xeon® Processor 5300 Series are 64-bit server/workstation
processors utilizing four Intel Core™ microarchitecture cores. These processors are
based on Intel’s 65 nanometer process technology combining high performance with
the power efficiencies of low-power Intel Core™ microarchitecture cores. The
Quad-Core Intel® Xeon® Processor 5300 Series consists of two die, each containing
two processor cores. All processors maintain the tradition of compatibility with IA-32
software. Some key features include on-die, 32 KB Level 1 instruction data caches per
core and 4 MB shared Level 2 cache per die (8 MB Total Cache per processor) with
Advanced Transfer Cache Architecture. The processor’s Data Prefetch Logic
speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting
in reduced bus cycle penalties and improved performance. The 1333 MHz Front Side
Bus (FSB) is a quad-pumped bus running off a 333 MHz system clock, which results in
10.6 GBytes per second data transfer. The 1066 MHz Front Side Bus is based on a
266 MHz system clock for an 8.5 GBytes per second data transfer rate. The Quad-Core
Intel® Xeon® Processor X5300 Series offers higher clock frequencies than the
Quad-Core Intel® Xeon® Processor E5300 Series for platforms that are targeted for
the performance optimized segment..
Enhanced thermal and power management capabilities are implemented including
Thermal Monitor 1 (TM1), Thermal Monitor 2 (TM2) and Enhanced Intel SpeedStep®
Technology. TM1 and TM2 provide efficient and effective cooling in high temperature
situations. Enhanced Intel SpeedStep® Technology provides power management
capabilities to servers and workstations.
The Quad-Core Intel® Xeon® Processor 5300 Series features include Advanced
Dynamic Execution, enhanced floating point and multi-media units, Streaming SIMD
Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3). Advanced Dynamic
Execution improves speculative execution and branch prediction internal to the
processor. The floating point and multi-media units include 128-bit wide registers and a
separate register for data movement. SSE3 instructions provide highly efficient double-
precision floating point, SIMD integer, and memory management operations.
The Quad-Core Intel® Xeon® Processor 5300 Series supports Intel® 64 architecture
as an enhancement to Intel's IA-32 architecture. This enhancement allows the
processor to execute operating systems and applications written to take advantage of
the 64-bit extension technology. Further details on Intel 64 architecture and its
programming model can be found in the Intel® 64 and IA-32 Architecture Software
Developer's Manual.
In addition, the Quad-Core Intel® Xeon® Processor 5300 Series supports the Execute
Disable Bit functionality. When used in conjunction with a supporting operating system,
Execute Disable allows memory to be marked as executable or non executable. This
feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities
and can thus help improve the overall security of the system. Further details on
Execute Disable can be found at:
http://www3.intel.com/cd/ids/developer/asmo-na/eng/149308.htm
The Quad-Core Intel® Xeon® Processor 5300 Series supports Intel® Virtualization
Technology for hardware-assisted virtualization within the processor. Intel Virtualization
Technology is a set of hardware enhancements that can improve virtualization
solutions. Intel Virtualization Technology is used in conjunction with Virtual Machine

Introduction
10 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Monitor software enabling multiple, independent software environments inside a single
platform. Further details on Intel Virtualization Technology can be found at
http://developer.intel.com/technology/virtualization/index.htm.
The Quad-Core Intel® Xeon® Processor 5300 Series are intended for high performance
server and workstation systems. The processors support a Dual Independent Bus (DIB)
architecture with one processor on each bus, up to two processor sockets in a system.
The DIB architecture provides improved performance by allowing increased FSB speeds
and bandwidth. The processors will be packaged in an FC-LGA6 Land Grid Array
package with 771 lands for improved power delivery. It utilizes a surface mount
LGA771 socket that supports Direct Socket Loading (DSL).
Quad-Core Intel® Xeon® Processor 5300 Series based platforms implement
independent core voltage (VCC) power planes for each processor. FSB termination
voltage (VTT) is shared and must connect to all FSB agents. The processor core voltage
utilizes power delivery guidelines specified by VRM/EVRD 11.0 and its associated load
line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 11.0 Design Guidelines for further details). VRM/EVRD 11.0 will support the
power requirements of all frequencies of the processors including Flexible Motherboard
Guidelines (FMB) (see Section 2.13.1). Refer to the appropriate platform design
guidelines for implementation details.
The Quad-Core Intel® Xeon® Processor 5300 Series support either 1333 or 1066 MHz
Front Side Bus operation. The FSB utilizes a split-transaction, deferred reply protocol
and Source-Synchronous Transfer (SST) of address and data to improve performance.
The processor transfers data four times per bus clock (4X data transfer rate, as in AGP
4X). Along with the 4X data bus, the address bus can deliver addresses two times per
bus clock and is referred to as a ‘double-clocked’ or a 2X address bus. In addition, the
Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 10.66 GBytes (1333 MHz) or 8.5
GBytes (1066 MHz) per second. The FSB is also used to deliver interrupts.
Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages.
Section 2.1 contains the electrical specifications of the FSB while implementation
details are fully described in the appropriate platform design guidelines (refer to
Section 1.3).
Table 1-1. Quad-Core Intel® Xeon® Processor 5300 Series Features
# of Processor
Cores
L1 Cache (per
core)
L2 Advanced
Transfer Cache
Front Side Bus
Frequency Package
4 32 KB instruction
32 KB data
4MB Shared L2
Cache per die
8MB Total Cache
1333 MHz
1066 MHz
FC-LGA6
771 Lands

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 11
Introduction
1.1 Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the asserted state when driven to a low level. For example, when RESET# is low, a
reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
Commonly used terms are explained here for clarification:
•Quad-Core Intel® Xeon® Processor 5300 Series – Intel 64-bit microprocessor
intended for dual processor servers and workstations. The Quad-Core Intel®
Xeon® Processor 5300 Series is based on Intel’s 65 nanometer process, in the
FC-LGA6 package with four processor cores. For this document, “processor” is used
as the generic term for the “Quad-Core Intel® Xeon® Processor 5300 Series”. The
term ‘processors’ and “Quad-Core Intel® Xeon® Processor 5300 Series” are
inclusive of Quad-Core Intel® Xeon® Processor E5300 Series and Quad-Core
Intel® Xeon® Processor X5300 Series.
•Quad-Core Intel® Xeon® Processor E5300 Series – A mainstream
performance version of the Quad-Core Intel® Xeon® Processor E5300 Series. For
this document “Quad-Core Intel® Xeon® Processor E5300 Series” is used to call
out specifications that are unique to the Quad-Core Intel® Xeon® Processor E5300
Series SKU.
•Quad-Core Intel® Xeon® Processor X5300 Series – An accelerated
performance version of the Quad-Core Intel® Xeon® Processor X5300 Series. For
this document “Quad-Core Intel® Xeon® Processor X5300 Series” is used to call
out specifications that are unique to the Quad-Core Intel® Xeon® Processor X5300
Series SKU.
•FC-LGA6 (Flip Chip Land Grid Array) Package – The Quad-Core Intel® Xeon®
Processor 5300 Series package is a Land Grid Array, consisting of a processor core
mounted on a pinless substrate with 771 lands, and includes an integrated heat
spreader (IHS).
•LGA771 socket – The Quad-Core Intel® Xeon® Processor 5300 Series interfaces
to the baseboard through this surface mount, 771 Land socket. See the LGA771
Socket Design Guidelines for details regarding this socket.
•Processor core – Processor core with integrated L1 cache. L2 cache and system
bus interface are shared between the two cores on the die. All AC timing and signal
integrity specifications are at the pads of the processor die.
•FSB (Front Side Bus) – The electrical interface that connects the processor to the
chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.

Introduction
12 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
•Dual Independent Bus (DIB) – A front side bus architecture with one processor
on each bus, rather than a FSB shared between two processor agents. The DIB
architecture provides improved performance by allowing increased FSB speeds and
bandwidth.
•Flexible Motherboard Guidelines (FMB) – Are estimates of the maximum
values the Quad-Core Intel® Xeon® Processor 5300 Series will have over certain
time periods. The values are only estimates and actual specifications for future
processors may differ.
•Functional Operation – Refers to the normal operating conditions in which all
processor specifications, including DC, AC, FSB, signal quality, mechanical and
thermal are satisfied.
•Storage Conditions – Refers to a non-operational state. The processor may be
installed in a platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased or receive any clocks.
Upon exposure to “free air” (that is, unsealed packaging or a device removed from
packaging material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.
•Priority Agent – The priority agent is the host bridge to the processor and is
typically known as the chipset.
•Symmetric Agent – A symmetric agent is a processor which shares the same I/O
subsystem and memory array, and runs the same operating system as another
processor in a system. Systems using symmetric agents are known as Symmetric
Multiprocessing (SMP) systems.
•Integrated Heat Spreader (IHS) – A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
•Thermal Design Power – Processor thermal solutions should be designed to meet
this target. It is the highest expected sustainable power while running known
power intensive real applications. TDP is not the maximum power that the
processor can dissipate.
•Intel®64 Architecture – Instruction set architecture and programming
environment of Intel’s 64-bit processors, which are a superset of and compatible
with IA-32. This 64-bit instruction set architecture was formerly known as IA-32
with EM64T or Intel® EM64T.
•Enhanced Intel SpeedStep®Technology – Technology that provides power
management capabilities to servers and workstations.
•Platform Environment Control Interface (PECI) – A proprietary one-wire bus
interface that provides a communication channel between Intel processor and
chipset components to external thermal monitoring devices, for use in fan speed
control. PECI communicates readings from the processor’s Digital Thermal Sensor
(DTS). The replaces the thermal diode available in previous processors.
•Intel®Virtualization Technology (Intel® VT) – Processor virtualization which
when used in conjunction with Virtual Machine Monitor software enables multiple,
robust independent software environments inside a single platform.
•VRM (Voltage Regulator Module) – DC-DC converter built onto a module that
interfaces with a card edge socket and supplies the correct voltage and current to
the processor based on the logic state of the processor VID bits.
•EVRD (Enterprise Voltage Regulator Down) – DC-DC converter integrated onto
the system board that provides the correct voltage and current to the processor
based on the logic state of the processor VID bits.

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 13
Introduction
•VCC – The processor core power supply.
•VSS – The processor ground.
•VTT – FSB termination voltage. (Note: In some Intel processor EMTS documents,
VTT is instead called VCCP .)
1.2 State of Data
The data contained within this document is the most accurate information available by
the publication date of this document.
1.3 References
Material and concepts available in the following documents may be beneficial when
reading this document:
Notes:
1. Document is available publicly at http://developer.intel.com.
2. Document not available at the time of printing.
§
Document Document
Number1Notes
AP-485, Intel® Processor Identification and the CPUID Instruction 241618 1
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B
253665
253666
253667
253668
253669
1
IA-32 Intel® Architecture Optimization Reference Manual 248966 1
Intel® Virtualization Technology Specification for the IA-32 Intel® Architecture C97063 1
Quad-Core Intel® Xeon® Processor 5300 Series Specification Update 315338 1
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD)
11.0 Design Guidelines
2
Quad-Core Intel® Xeon® Processor 5300 SeriesThermal/Mechanical Design
Guidelines
315794 1
LGA771 Socket Mechanical Design Guide 313871 1
Quad-Core Intel® Xeon® Processor 5300 Series Boundary Scan Description
Language (BSDL) Model
1
Debug Port Design Guide for UP/DP Systems 1

Introduction
14 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 15
Electrical Specifications
2Electrical Specifications
2.1 Front Side Bus and GTLREF
Most Quad-Core Intel® Xeon® Processor 5300 Series FSB signals use Assisted
Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides
improved noise margins and reduced ringing through low voltage swings and controlled
edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the
high logic level and termination. AGTL+ output buffers differ from GTL+ buffers with
the addition of an active PMOS pull-up transistor to “assist” the pull-up resistors during
the first clock of a low-to-high voltage transition. Platforms implement a termination
voltage level for AGTL+ signals defined as VTT
. Because platforms implement separate
power planes for each processor (and chipset), separate VCC and VTT supplies are
necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address buses have made
signal integrity considerations and platform design methods even more critical than
with previous processor families. Design guidelines for the processor FSB are detailed
in the appropriate platform design guidelines (refer to Section 1.3).
The AGTL+ inputs require reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID and GTLREF_ADD_END) which are used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF_DATA_MID and
GTLREF_DATA_END are used for the 4X front side bus signaling group and
GTLREF_ADD_MID and GTLREF_ADD_END are used for the 2X and common clock front
side bus signaling groups. GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END must be generated on the baseboard (See
Ta b l e 2 - 1 8 for GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID and
GTLREF_ADD_END specifications). Refer to the applicable platform design guidelines
for details. Termination resistors (RTT) for AGTL+ signals are provided on the processor
silicon and are terminated to VTT . The on-die termination resistors are always enabled
on the processor to control reflections on the transmission line. Intel chipsets also
provide on-die termination, thus eliminating the need to terminate the bus on the
baseboard for most AGTL+ signals.
Some FSB signals do not include on-die termination (RTT) and must be terminated on
the baseboard. See Tab le 2 - 7 and Ta ble 2 - 8 for details regarding these signals.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for
AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog
signal simulation of the FSB, including trace lengths, is highly recommended when
designing a system. Contact your Intel Field Representative to obtain the applicable
signal integrity models, which includes buffer and package models.

Electrical Specifications
16 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
2.2 Power and Ground Lands
For clean on-chip processor core power distribution, the processor has 223 VCC (power)
and 267 VSS (ground) inputs. All VCC lands must be connected to the processor power
plane, while all VSS lands must be connected to the system ground plane. The
processor VCC lands must be supplied with the voltage determined by the processor
Voltage IDentification (VID) signals. See Tab l e 2 - 3 for VID definitions.
Twenty two lands are specified as VTT , which provide termination for the FSB and
provides power to the I/O buffers. The platform must implement a separate supply for
these lands which meets the VTT specifications outlined in Ta b l e 2 - 1 2 .
2.3 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large average current swings between low and full power states.
This may cause voltages on power planes to sag below their minimum values if bulk
decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors,
supply current during longer lasting changes in current demand by the component,
such as coming out of an idle condition. Similarly, they act as a storage well for current
when entering an idle condition from a running condition. Care must be taken in the
baseboard design to ensure that the voltage provided to the processor remains within
the specifications listed in Ta b l e 2 - 1 2. Failure to do so can result in timing violations or
reduced lifetime of the component. For further information and guidelines, refer to the
appropriate platform design guidelines.
2.3.1 VCC Decoupling
Vcc regulator solutions need to provide bulk capacitance with a low Effective Series
Resistance (ESR), and the baseboard designer must assure a low interconnect
resistance from the regulator (EVRD or VRM pins) to the LGA771 socket. Bulk
decoupling must be provided on the baseboard to handle large current swings. The
power delivery solution must insure the voltage and current specifications are met (as
defined in Tabl e 2 - 1 2 ). For further information regarding power delivery, decoupling
and layout guidelines, refer to the appropriate platform design guidelines.
2.3.2 VTT Decoupling
Bulk decoupling must be provided on the baseboard. Decoupling solutions must be
sized to meet the expected load. To insure optimal performance, various factors
associated with the power delivery solution must be considered including regulator
type, power plane and trace sizing, and component placement. A conservative
decoupling solution consists of a combination of low ESR bulk capacitors and high
frequency ceramic capacitors. For further information regarding power delivery,
decoupling and layout guidelines, refer to the appropriate platform design guidelines.

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 17
Electrical Specifications
2.3.3 Front Side Bus AGTL+ Decoupling
The processor integrates signal termination on the die, as well as a portion of the
required high frequency decoupling capacitance on the processor package. However,
additional high frequency capacitance must be added to the baseboard to properly
decouple the return currents from the FSB. Bulk decoupling must also be provided by
the baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in
the appropriate platform design guidelines.
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor
Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous processor generations, the processor core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is set during
manufacturing. The default setting is for the maximum speed of the processor. It is
possible to override this setting using software (see the Intel® 64 and IA-32
Architectures Software Developer’s Manual). This permits operation at lower
frequencies than the processor’s tested frequency.
The processor core frequency is configured during reset by using values stored
internally during manufacturing. The stored value sets the highest bus fraction at which
the particular processor can operate. If lower speeds are desired, the appropriate ratio
can be configured via the CLOCK_FLEX_MAX Model Specific Register (MSR). For details
of operation at core frequencies lower than the maximum rated processor speed, refer
to the Intel® 64 and IA-32 Architectures Software Developer’s Manual.
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread
spectrum clocking. Processor DC and AC specifications for the BCLK[1:0] inputs are
provided in Ta b l e 2 -1 9 . These specifications must be met while also meeting signal
integrity requirements as outlined in Tab l e 2 -19 . The processor utilizes differential
clocks. Ta b l e 2 - 1 contains processor core frequency to FSB multipliers and their
corresponding core frequencies.

Electrical Specifications
18 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Notes:
1. Individual processors operate only at or below the frequency marked on the package.
2. Listed frequencies are not necessarily committed production frequencies.
3. For valid processor core frequencies, refer to the Quad-Core Intel® Xeon® Processor 5300 Series
Specification Update.
4. The lowest bus ratio supported is 1/6.
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])
Upon power up, the FSB frequency is set to the maximum supported by the individual
processor. BSEL[2:0] are CMOS outputs which must be pulled up to VTT , and are used
to select the FSB frequency. Please refer to Ta b l e 2 - 1 5 for DC specifications. Tab l e 2 - 2
defines the possible combinations of the signals and the frequency associated with each
combination. The frequency is determined by the processor(s), chipset, and clock
synthesizer. All FSB agents must operate at the same core and FSB frequency. See the
appropriate platform design guidelines for further details.
Table 2-1. Core Frequency to FSB Multiplier Configuration
Core Frequency to FSB
Multiplier
Core Frequency with
333.333 MHz Bus Clock
Core Frequency with
266.666 MHz Bus Clock Notes
1/6 2 GHz 1.60 GHz 1, 2, 3, 4
1/7 2.33 GHz 1.86 GHz 1, 2, 3
1/8 2.66 GHz 2.13 GHz 1, 2, 3
1/9 3 GHz 2.40 GHz 1, 2, 3
Table 2-2. BSEL[2:0] Frequency Table
BSEL2 BSEL1 BSEL0 Bus Clock Frequency
0 0 0 266.666 MHz
0 0 1 Reserved
0 1 0 Reserved
0 1 1 Reserved
1 0 0 333.333 MHz
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 19
Electrical Specifications
2.4.2 PLL Power Supply
An on-die PLL filter solution is implemented on the processor. The VCCPLL input is used
to provide power to the on chip PLL of the processor. Please refer to Tab l e 2 - 1 2 for DC
specifications. Refer to the appropriate platform design guidelines for decoupling and
routing guidelines.
2.5 Voltage Identification (VID)
The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines. The voltage set by the VID signals is the reference VR output voltage to be
delivered to the processor Vcc pins. Please refer to Table 2 - 1 6 for the DC specifications
for these signals. A voltage range is provided in Table 2- 1 2 and changes with
frequency. The specifications have been set such that one voltage regulator can
operate with all supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core frequency may have different default VID settings. This is
reflected by the VID range values provided in Tab l e 2 - 3 .
The Quad-Core Intel® Xeon® Processor 5300 Series uses six voltage identification
signals, VID[6:1], to support automatic selection of power supply voltages. Tab le 2- 3
specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table
refers to a high voltage level and a ‘0’ refers to a low voltage level. The definition
provided in Tab le 2 - 3 is not related in any way to previous Intel® Xeon® processors or
voltage regulator designs. If the processor socket is empty (VID[6:1] = 111111), or
the voltage regulation circuit cannot supply the voltage that is requested, the voltage
regulator must disable itself. See the Voltage Regulator Module (VRM) and Enterprise
Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details.
Although the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 11.0 Design Guidelines defines VID [7:0], VID 7 and VID 0 are not used on the
Quad-Core Intel® Xeon® Processor 5300 Series. Please refer to the appropriate
platform design guide for details.
The Quad-Core Intel® Xeon® Processor 5300 Series provide the ability to operate
while transitioning to an adjacent VID and its associated processor core voltage (VCC).
This will represent a DC shift in the load line. It should be noted that a low-to-high or
high-to-low voltage state change may result in as many VID transitions as necessary to
reach the target core voltage. Transitions above the specified VID are not permitted.
Ta b l e 2 - 1 2 includes VID step sizes and DC shift ranges. Minimum and maximum
voltages must be maintained as shown in Table 2-1 3 .
The VRM or EVRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in
Ta b l e 2 - 12 .
Power source characteristics must be guaranteed to be stable whenever the supply to
the voltage regulator is stable.

Electrical Specifications
20 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Notes:
1. When the “111111” VID pattern is observed, the voltage regulator output should be disabled.
2. Shading denotes the expected VID range of the Quad-Core Intel® Xeon® Processor 5300 Series.
3. The VID range includes VID transitions that may be initiated by thermal events, assertion of the FORCEPR# signal (see
Section 6.2.3), Extended HALT state transitions (see Section 7.2.2), or Enhanced Intel SpeedStep® Technology transitions
(see Section 7.3). The Extended HALT state must be enabled for the processor to remain within its specifications.
4. Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a specific VID off code is
received, the VRM/EVRD must turn off its output (the output should go to high impedance) within 500 ms and latch off until
power is cycled.
Table 2-3. Voltage Identification Definition
HEX
VID6
400
mV
VID5
200
mV
VID4
100
mV
VID3
50
mV
VID2
25
mV
VID1
12.5
mV
VCC_MAX HEX
VID6
400
mV
VID5
200
mV
VID4
100
mV
VID3
50
mV
VID2
25
mV
VID1
12.5
mV
VCC_MAX
7A111101 0.8500 3C 0111101.2375
78111100 0.8625 3A 0111011.2500
76111011 0.8750 38 0111001.2625
74111010 0.8875 36 0110111.2750
72111001 0.9000 34 0110101.2875
70111000 0.9125 32 0110011.3000
6E110111 0.9250 30 0110001.3125
6C110110 0.9375 2E 0101111.3250
6A110101 0.9500 2C 0101101.3375
68 110100 0.9625 2A 0101011.3500
66 1100110.9750 28 0101001.3625
64 1100100.9875 26 0100111.3750
62 1100011.0000 24 0100101.3875
60 1100001.0125 22 0100011.4000
5E 1011111.0250 20 0100001.4125
5C 1011101.0375 1E 0011111.4250
5A 1011011.0500 1C 0011101.4375
58 1011001.0625 1A 0011011.4500
56 1010111.0750 18 0011001.4625
54 1010101.0875 16 0010111.4750
52 1010011.1000 14 0010101.4875
50 1010001.1125 12 0010011.5000
4E 1001111.1250 100010001.5125
4C 1001101.1375 0E0001111.5250
4A 1001011.1500 0C0001101.5375
48 1001001.1625 0A0001011.5500
46 1000111.1750 080001001.5625
44 1000101.1875 060000111.5750
42 1000011.2000 040000101.5875
40 1000001.2125 020000011.6000
3E 0111111.2250 00000000OFF
1