Intel DUAL-CORE - UPDATE REV 010 User manual

Intel® Pentium® Dual-Core
Processor
Specification Update
December 2010
Revision 010

2Specification Update
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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the
absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The
information here is subject to change without notice. Do not finalize a design with this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to
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Copyright © 2007, Intel Corporation. All rights reserved.

Specification Update 3
Contents
Preface ...............................................................................................................................5
Summary Tables of Changes..................................................................................................7
Identification Information ....................................................................................................15
Errata...............................................................................................................................17
Specification Changes .........................................................................................................55
Specification Clarifications ...................................................................................................56
Documentation Changes......................................................................................................57

4Specification Update
Revision History
Document
Number Revision Description Date
316515 -001 Initial release February 2007
316515 -002 •Added T2080 product SKU March 2007
316515 -003 •Updated erratum AN45
•Updated Summary Table of Changes
April 2007
316515 -004 •Updated Summary Table of Changes July 2007
316515 -005 •Added processors for the Mobile 965 Express Chipset
Family
•Added M-0 stepping errata
August 2007
316515 -006 •Added Processors based on the Intel Mobile 965 series
chipset.
•Added M-0 Errata and Microcode in separate tables
•Removed Errata AN11, AN19, AN21, AN42, AN55, AN63,
AN 69, AN72, AN74, AN79, AN83, AN96, AN104, AN5S
and AN11S.
•Updated Errata AN45
September 2007
316515 -007 •Added AN106 – AN109 October 2007
316515 -008 •Added AN110 November 2007
316515 -009 •Updated Summary Table of Changes - Added AU - AY
•Updated AN34
•Added AN111
December 2007
316515 -010 •Added AN112 November 2010
§

Preface
Specification Update 5
Preface
This document is an update to the specifications contained in the documents listed in
the following Affected Documents table. It is a compilation of device and document
errata and specification clarifications and changes, and is intended for hardware
system manufacturers and for software developers of applications, operating system,
and tools.
Information types defined in the Nomenclature section of this document are
consolidated into this update document and are no longer published in other
documents. This document may also contain information that has not been previously
published.
Affected Documents
Document Title Document
Number/Location
Intel® Pentium® Dual-Core Processor Mobile Processor Datasheet 316519
Intel® Pentium® Dual-Core Processor for Intel® 965 Express Chipset
Family Datasheet 318125
Related Documents
Document Title Document
Number/Location
Debug Port Design Guide for Crestline and Intel® 945PM/GM/GT and
940GML Express Chipset Systems Note
Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 1: Basic Architecture 253665
Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 2A: Instruction Set Reference, A-M 253666
Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 2B: Instruction Set Reference, N-Z 253667
Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 3A: System Programming Guide 253668
Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 3B: System Programming Guide 253669
Intel® 64 and IA-32 Architectures Optimization Reference Manual 248966
Intel® 64 and IA-32 Architectures Optimization Reference Manual
Documentation Changes 252046

Preface
6Specification Update
Nomenclature
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics (e.g., core speed, L2 cache size, package
type, etc.) as described in the processor identification information table. Care should
be taken to read all notes associated with each S-Spec number
Errata are design defects or errors. Errata may cause the products’ behavior to
deviate from published specifications. Hardware and software designed to be used
with any given stepping must assume that all errata documented for that stepping are
present on all devices.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications
will be incorporated in the next release of the specifications.
Documentation Changesinclude typos, errors, or omissions from the current
published specifications. These changes will be incorporated in the next release of the
specifications.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, etc.).
§

Summary Tables of Changes
Specification Update 7
Summary Tables of Changes
The following table indicates the Specification Changes, Errata, Specification
Clarifications or Documentation Changes, which apply to the listed Processor
steppings. Intel intends to fix some of the errata in a future stepping of the
component, and to account for the other outstanding issues through documentation or
Specification Changes as noted. This table uses the following notations:
Codes Used in Summary Table
Stepping
X: Erratum, Specification Change or Clarification that applies
to this stepping.
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification
change does not apply to listed stepping.
Status
Doc: Document change or update that will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the
product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Shaded: This item is either new or modified from the previous
version of the document.

Summary Tables of Changes
8Specification Update
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
Specification Updates:
A = Dual-Core Intel® Xeon® processor 7000Δsequence
C = Intel® Celeron® processor
D = Dual-Core Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor
I = Dual-Core Intel® Xeon® processor 5000Δseries
J = 64-bit Intel® Xeon® processor MP with 1-MB L2 cache
K = Mobile Intel® Pentium® III processor
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel ® Pentium® 4 processor
O = Intel ® Xeon® processor MP
P = Intel ® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading Technology on
90-nm process technology
R = Intel® Pentium® 4 processor on 90-nm process
S = 64-bit Intel® Xeon® processor with 800-MHz system bus (1-MB and 2-MB L2
cache versions)
T = Mobile Intel® Pentium® 4 processor–M
U = 64-bit Intel® Xeon® processor MP with up to 8-MB L3 cache
V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA Package
W= Intel® Celeron®-M processor
X = Intel® Pentium® M processor on 90-nm process with 2-MB L2 cache and Intel®
Processors A100 and A110 with 512-kB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533-MHz system bus
AA= Intel® Pentium® D Processor 900ΔSequence and Intel® Pentium® processor
Extreme Edition 955Δ, 965Δ
AB= Intel® Pentium® 4 processor 6x1 sequence
AC= Intel® Celeron® processor in 478-pin package
AD = Intel® Celeron® D processor on 65-nm process
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65-nm
process
AF = Dual-Core™ Intel® Xeon® processor LV
AG = Dual-Core Intel® Xeon® processor 5100Δseries
AH= Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor
technology
AI = Intel® Core™2 Extreme processor X6800Δand Intel®Core™2 Duo Desktop
processor E6000Δand E4000Δsequence
AJ = Quad-Core Intel® Xeon® processor 5300Δseries

Summary Tables of Changes
Specification Update 9
AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel®
Core™2 Quad processor Q6000 sequence
AL = Dual-Core Intel® Xeon® processor 7100 Δseries
AM = Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® Dual-Core processor
AO = Quad-Core Intel® Xeon® processor 3200Δseries
AP = Dual-Core Intel® Xeon® processor 3000Δseries
AQ = Intel® Pentium® Dual-Core Desktop processor E2000Δsequence
AR = Intel® Celeron® Processor 500Δseries
AS = Intel® Xeon® processor 7200, 7300Δseries
AT = Intel® Celeron® processor 200 series
AU = Mobile Value Celeron
AV = Intel® Core™2 Extreme Processor QX9000 Sequence and Intel® Core™2 Quad
Processor Q9000 Sequence processor
AX = Quad-Core Intel® Xeon® Processor 5400 Series
AY = Wolfdale DP
Note: ΔIntel processor numbers are not a measure of performance. Processor numbers
differentiate features within each processor family, not across different processor
families. See http://www.intel.com/products/processor_number for details.
Errata for Intel® Pentium® Dual-Core Mobile Processors
Number D0 M0 Plans ERRATA
AN1 X Fixed FST Instruction with Numeric and Null Segment Exceptions May
Take Numeric Exception with Incorrect FPU Operand Pointer
AN2 X X No Fix Code Segment Limit Violation May Occur on 4-Gbyte Limit Check
AN3 Erratum Removed
AN4 X X No Fix REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an
Incorrect Data Size or Lead to Memory-Ordering Violations
AN5 X Fixed Memory Aliasing with Inconsistent A and D Bits May Cause
Processor Deadlock
AN6 X X No Fix VM Bit Is Cleared on Second Fault Handled by Task Switch from
Virtual-8086 (VM86)
AN7 X Fixed Page with PAT (Page Attribute Table) Set to USWC (Uncacheable Speculative Write Combine) While Associated MTRR (Memory Type
Range Register) Is UC (Uncacheable) May Consolidate to UC
AN8 X Fixed FPU Operand Pointer May Not Be cleared following FINIT/FNINIT
AN9 X Fixed LTR Instruction May Result in Unexpected Behavior
AN10 X Fixed Invalid Entries in Page-Directory-Pointer-Table Register (PDPTR) May Cause General Protection (#GP) Exception if the Reserved Bits
are Set to One
AN11 Fixed Erratum Removed

Summary Tables of Changes
10 Specification Update
Number D0 M0 Plans ERRATA
AN12 X Fixed FP Inexact-Result Exception Flag May Not Be Set
AN13 X Fixed A Locked Data Access that Spans Across Two Pages May Cause the
System to Hang
AN14 X X No Fix MOV To/From Debug Registers Causes Debug Exception
AN15 X X No Fix INIT Does Not Clear Global Entries in the TLB
AN16 X Fixed Use of Memory Aliasing with Inconsistent Memory Type May Cause
System Hang
AN17 X Fixed Machine Check Exception May Occur when Interleaving Code
Between Different Memory Types
AN18 Erratum removed
AN19 Erratum removed
AN20 X X No Fix LOCK# Asserted During a Special Cycle Shutdown Transaction May
Unexpectedly Deassert
AN21 Erratum removed
AN22 X X No Fix Last Branch Records (LBR) Updates May be Incorrect After a Task
Switch
AN23 X X No Fix Address Reported by Machine-Check Architecture (MCA) on Single-
bit L2 ECC Errors May be Incorrect
AN24 X Fixed Disabling of Single-step On Branch Operation May be Delayed
following a POPFD Instruction
AN25 X Fixed Performance Monitoring Counters that Count External Bus Events
May Report Incorrect Values after Processor Power State Transitions
AN26 X X No Fix VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the
Last Exception Record (LER) MSR
AN27 X X No Fix General Protection (#GP) Fault May Not Be Signaled on Data
Segment Limit Violation Above 4-G Limit
AN28 X Fixed Performance Monitoring Events for Retired Floating Point Operations
(C1h) May Not be Accurate
AN29 X
X No Fix DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring
Count for Saturating SIMD Instructions Retired (Event CFH)
AN30 X Fixed Global Pages in the Data Translation Look-Aside Buffer (DTLB) May Not Be Flushed by RSM instruction before Restoring the
Architectural State from SMRAM
AN31 X Fixed Data Breakpoint/Single Step on MOV SS/POP SS May be Lost after
Entry into SMM
AN32 X Fixed CS Limit Violation on RSM May be Serviced before Higher Priority
Interrupts/Exceptions
AN33 Erratum removed
AN34 X X No Fix Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
Before Higher Priority Interrupts

Summary Tables of Changes
Specification Update 11
Number D0 M0 Plans ERRATA
AN35 X X No Fix Programming the Digital Thermal Sensor (DTS) Threshold May
Cause Unexpected Thermal Interrupts
AN36 Erratum removed
AN37 X X No Fix The Processor May Report a #TS Instead of a #GP Fault
AN38 X Fixed BTS Message May be Lost when the STPCLK# Signal is Active
AN39 X Fixed Certain Performance Monitoring Counters Related to Bus, L2 Cache
and Power Management are Inaccurate
AN40 X X No Fix A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
AN41 X X No Fix IO_SMI Indication in SMRAM State Save Area May be Set
Incorrectly
AN42 Erratum removed
AN43 Erratum removed
AN44 X Fixed Logical Processors May Not Detect Write-Back (WB) Memory Writes
AN45 X X No Fix LER MSRs May be Incorrectly Updated.
AN46 X Fixed SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null Segment
Selector” to SS and CS Registers
AN47 X X No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
AN48 X X No Fix Using 2M/4M pages When A20M# Is Asserted May Result in
Incorrect Address Translations
AN49 X Fixed Counter Enable bit [22] of IA32_CR_PerfEvtSel0 and IA32_CR_PerfEvtSel1 Do Not Comply with PerfMon (Architectural
Performance Monitoring) Specification
AN50 X X No Fix Premature Execution of a Load Operation Prior to Exception Handler
Invocation
AN51 X X No Fix Performance Monitoring Events for Retired Instructions (C0H) May
Not Be Accurate
AN52 X X No Fix #GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34]
When Execute Disable Bit is Not Supported
AN53 X Fixed Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
AN54 X Fixed SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code
(SMC) Event May Cause Unexpected Behavior
AN55 No Fix Erratum Removed
AN56 X X No Fix Split Locked Stores May Not Trigger the Monitoring Hardware
AN57 X X No Fix Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering
Issue

Summary Tables of Changes
12 Specification Update
Number D0 M0 Plans ERRATA
AN58 X
X No Fix MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
after a Machine Check Exception (MCE)
AN59 X Fixed Using Memory Type Aliasing with Memory Types WB/WT May Lead
to Unpredictable Behavior
AN60 X X No Fix Code Breakpoint May Be Taken after POP SS Instruction if It Is
Followed by an Instruction that Faults
AN61 X X No Fix Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
AN62 X X No Fix Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
AN63 No Fix Erratum Removed
AN64 X X No Fix Returning to Real Mode from SMM with EFLAGS.VM Set May Result
in Unpredictable System Behavior
AN65 X X No Fix A Thermal Interrupt is Not Generated when the Current
Temperature is Invalid
AN66 X X No Fix Performance Monitoring Event FP_ASSIST May Not be Accurate
AN67 X X No Fix The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception
AN68 X X No Fix BTM/BTS Branch-From Instruction Address May Be
Incorrect for Software Interrupts
AN69 Erratum removed
AN70 X X No Fix Single Step Interrupts with Floating Point Exception Pending May Be
Mishandled
AN71 X X No Fix Fault on ENTER Instruction May Result in Unexpected Values on
Stack Frame
AN72 Erratum removed
AN73 X X No Fix Unaligned Accesses to Paging Structures May Cause the Processor
To Hang
AN74 No Fix Erratum Removed
AN75 X X No Fix INVLPG Operation for Large (2M/4M) Pages May be Incomplete
Under Certain Conditions
AN76 X X No Fix Page Access Bit May Be Set Prior to Signaling a Code Segment Limit
Fault
AN77 X Fixed Performance Monitoring Events for Hardware Prefetch Requests (4EH) and Hardware Prefetch Request Cache Misses (4FH) May Not
be Accurate
AN78 X X No Fix EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after
Shutdown
AN79 X No Fix Erratum Removed
AN80 X X No Fix Store Ordering May be Incorrect between WC and WP Memory
Types

Summary Tables of Changes
Specification Update 13
Number D0 M0 Plans ERRATA
AN81 X X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
AN82 X No Fix Count Value for Performance-Monitoring Counter PMH_PAGE_WALK
May Be Incorrect
AN83 No Fix Erratum Removed
AN84 X No Fix Some Bus Performance Monitoring Events May Not Count Local
Events under Certain Conditions
AN85 X No Fix EIP May Be Incorrect after Shutdown in IA-32e Mode
AN86 X No Fix Upper 32 bits of ‘From’ Address Reported through BTMs or BTSs
May Be Incorrect
AN87 X No Fix Code Segment Limit/Canonical Faults on RSM May be Serviced
before Higher Priority Interrupts/Exceptions
AN88 X No Fix LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
AN89 X No Fix CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or
Equal to 248 May Terminate Early
AN90 X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
AN91 X No Fix PMI May Be Delayed to Next PEBS Event
AN92 X No Fix An Asynchronous MCE during a Far Transfer May Corrupt ESP
AN93 X No Fix B0-B3 Bits in DR6 May Not Be Properly Cleared after Code
Breakpoint
AN94 X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect
Values
AN95 X No Fix Performance Monitoring Events for L1 and L2 Miss May Not Be
Accurate
AN96 No Fix Erratum Removed
AN97 X No Fix Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is
Counted Incorrectly for PMULUDQ Instruction
AN98 X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or
STI
AN99 X No Fix Updating Code Page Directory Attributes without TLB Invalidation
May Result in Improper Handling of Code #PF
AN100 X No Fix Performance Monitoring Event MISALIGN_MEM_REF May Over
Count
AN101 X No Fix A REP STOS/MOVS to a MONITOR/MWAIT Address Range May
Prevent Triggering of the Monitoring Hardware
AN102 X No Fix A Memory Access May Get a Wrong Memory Type Following a #GP
due to WRMSR to an MTRR Mask
AN103 X No Fix PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR
Information
AN104 No Fix Erratum Removed

Summary Tables of Changes
14 Specification Update
Number D0 M0 Plans ERRATA
AN105 X No Fix BIST Failure after Reset
AN106 X X No Fix Instruction Fetch May Cause a Livelock during Snoops of the L1
Data Cache
AN107 X X No Fix Use of Memory Aliasing with Inconsistent Memory Type May Cause a
System Hang or a Machine Check Exception
AN108 X X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to
Memory-Ordering Violations
AN109 X X No Fix Using Memory Type Aliasing with Cacheable and WC Memory Types
May Lead to Memory Ordering Violations
AN110 X No Fix RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
AN111 X X Plan Fix NMIs May Not Be Blocked by a VM-Entry Failure
AN112 X X No Fix A 64-bit Register IP-relative Instruction May Return Unexpected
Results
Number SPECIFICATION CHANGES
There are no Specification Changes in this Specification Update revision.
Number SPECIFICATION CLARIFICATIONS
There are no Specification Clarifications in this Specification Update revision.
Number DOCUMENTATION CHANGES
There are no Documentation Changes in this Specification Update revision.
§

Identification Information
Specification Update 15
Identification Information
Component Marking Information
Figure 1. Intel® Pentium® Dual-Core Mobile Processor on 65-nm Process (Micro-
FCPGA/FCBGA) S-Spec Markings
Table 1. Pentium Dual-Core Mobile Processor on 65-nm Process Identification
Information
QDF/S-
SPEC# Processor # Package Stepping CPUID FSB(MHz) Speed HFM/LFM
(GHz)
Notes
SL9VX T2060 Micro-FCPGA D-0 06ECh 533 1.6/800 1
SL9VY T2080 Micro-FCPGA D-0 06ECh 533 1.73/800 1
SLAEC T2310 Micro-FCPGA M-0 06FDh 533 1.46/800 1
SLA4K T2330 Micro-FCPGA M-0 06FDh 533 1.60/800 1
NOTES:
1. VCC_CORE=1.2125 V-1.025 V for HFM Range/LFM.

Identification Information
16 Specification Update
Table 2. Pentium Dual-Core Mobile Processor on 65-nm Process Identification
Information for 965 Express Chipset Family
QDF/S-
SPEC# Processor # Package Stepping CPUID FSB(MHz) Speed HFM/LFM
(GHz)
Notes
SLAEC T2310 Micro-FCPGA M-0 06FDh 533 1.46/800 1
SLA4J T2370 Micro-FCPGA M-0 06FDh 533 1.73/800 1
SLA4K T2330 Micro-FCPGA M-0 06FDh 533 1.60/800 1
NOTES:
1. VCC_CORE=1.2125 V-1.025 V for HFM Range/LFM.
§

Errata
Specification Update 17
Errata
AN1. FST Instruction with Numeric and Null Segment Exceptions May Take
Numeric Exception with Incorrect FPU Operand Pointer
Problem: If execution of an FST (Store Floating Point Value) instruction would generate both
numeric and Null segment exceptions, the numeric exceptions may be taken first and
with the Null x87 FPU Instruction Operand (Data) Pointer.
Implication: Due to this erratum, on an FST instruction the processor reports a numeric exception
instead of reporting an exception because of a Null segment. If the numeric exception
handler tries to access the FST data it will get a #GP fault. Intel has not observed this
erratum with any commercially available software, or system.
Workaround:The numeric exception handler should check the segment and if it is Null avoid further
access to the data that caused the fault.
Status: For the steppings affected, see the Summary Tables of Changes.
AN2. Code Segment Limit Violation May Occur on 4-Gbyte Limit Check
Problem: Code Segment limit violation may occur on 4-Gbyte limit check when the code stream
wraps around in a way that one instruction ends at the last byte of the segment and
the next instruction begins at 0x0.
Implication: This is a rare condition that may result in a system hang. Intel has not observed this
erratum with any commercially available software, or system.
Workaround:Avoid code that wraps around segment limit.
Status: For the steppings affected, see the Summary Tables of Changes.

Errata
18 Specification Update
AN3. Erratum removed
AN4. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types May Use an
Incorrect Data Size or Lead to Memory-Ordering Violations
Problem: Under certain conditions as described in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 3A: System Programming Guide,the processor
performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP
MOVS/REP STOS instructions that cross page boundaries from WB/WC memory types
to UC/WP/WT memory types, may start using an incorrect data size or may observe
memory ordering violations.
Implication: Upon crossing the page boundary the following may occur, dependent on the new
page memory type:
•UC the data size of each write will now always be 8 bytes, as opposed to the
original data size.
•WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.
•WT there may be a memory ordering violation.
Workaround:Software should avoid crossing page boundaries from WB or WC memory type to UC,
WP or WT memory type within a single REP MOVS or REP STOS instruction that will
execute with fast strings enabled.
Status: For the steppings affected, see the Summary Tables of Changes.
AN5. Memory Aliasing with Inconsistent A and D Bits May Cause Processor
Deadlock
Problem: In the event that software implements memory aliasing by having two Page Directory
Entries (PDEs) point to a common Page Table Entry (PTE) and the Accessed and Dirty
bits for the two PDEs are allowed to become inconsistent the processor may become
deadlocked.
Implication: This erratum has not been observed with commercially available software.
Workaround:Software that needs to implement memory aliasing in this way should manage the
consistency of the Accessed and Dirty bits.
Status: For the steppings affected, see the Summary Tables of Changes.

Errata
Specification Update 19
AN6. VM Bit Is Cleared on Second Fault Handled by Task Switch from
Virtual-8086 (VM86)
Problem: Following a task switch to any fault handler that was initiated while the processor was
in VM86 mode, if there is an additional fault while servicing the original task switch
then the VM bit will be incorrectly cleared in EFLAGS, data segments will not be
pushed and the processor will not return to the correct mode upon completion of the
second fault handler via IRET.
Implication: When the OS recovers from the second fault handler, the processor will no longer be
in VM86 mode. Normally, operating systems should prevent interrupt task switches
from faulting, thus the scenario should not occur under normal circumstances.
Workaround:None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AN7. Page With PAT (Page Attribute Table) Set to USWC (Uncacheable
Speculative Write Combine) While Associated MTRR (Memory Type
Range Register) Is UC (Uncacheable) May Consolidate to UC
Problem: A page whose PAT memory type is USWC while the relevant MTRR memory type is
UC, the consolidated memory type may be treated as UC (rather than WC as specified
in Intel® 64 and IA-32 Architectures Software Developer's Manual).
Implication: When this erratum occurs, the memory page may be as UC (rather than WC). This
may have a negative performance impact.
Workaround:None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AN8. FPU Operand Pointer May Not Be Cleared Following FINIT/FNINIT
Problem: Initializing the floating point state with either FINIT or FNINT, may not clear the x87
FPU Operand (Data) Pointer Offset and the x87 FPU Operand (Data) Pointer Selector
(both fields form the FPUDataPointer). Saving the floating point environment with
FSTENV, FNSTENV, or floating point state with FSAVE, FNSAVE or FXSAVE before an
intervening FP instruction may save un-initialized values for the FPUDataPointer.
Implication: When this erratum occurs, the values for FPUDataPointer in the saved floating point
image structure may appear to be random values. Executing any non-control FP
instruction with memory operand will initialize the FPUDataPointer. Intel has not
observed this erratum with any commercially available software.
Workaround:After initialization, do not expect a floating point state saved memory image to be
correct, until at least one non-control FP instruction with a memory operand has been
executed.
Status: For the steppings affected, see the Summary Tables of Changes.

Errata
20 Specification Update
AN9. LTR Instruction May Result in Unexpected Behavior
Problem: Under certain circumstances an LTR (Load Task Register) instruction may result in an
unexpected behavior if all the following conditions are met:
1. Invalid data selector of the TR (Task Register) resulting with either #GP (General
Protection Fault) or #NP (Segment Not Present Fault).
2. GDT (Global Descriptor Table) is not 8-bytes aligned.
Implication: If all conditions have been met then under certain circumstances LTR instruction may
result in system hang, memory corruption or other unexpected behavior. This
erratum has not been observed in commercial operating systems or software.
Workaround:Operating system software should align GDT to 8-bytes, as recommended in the
Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System
Programming Guide.For performance reasons, GDT is typically aligned to 8-bytes.
Status: For the steppings affected, see the Summary Tables of Changes.
AN10. Invalid Entries In Page-Directory-Pointer-Table Register (PDPTR)
May Cause General Protection (#GP) Exception If the Reserved Bits
Are Set to One
Problem: Invalid entries in the Page-Directory-Pointer-Table Register (PDPTR) that have the
reserved bits set to one may cause a General Protection (#GP) exception.
Implication: Intel has not observed this erratum with any commercially available software.
Workaround:Do not set the reserved bits to one when PDPTR entries are invalid.
Status: For the steppings affected, see the Summary Tables of Changes.
AN11. Erratum removed