Intel DUAL-CORE - UPDATE REV 010 User manual

Intel® Pentium® Dual-Core
Processor
Specification Update
December 2010
Revision 010

2Specification Update
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definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The
information here is subject to change without notice. Do not finalize a design with this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to
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Copyright © 2007, Intel Corporation. All rights reserved.

Specification Update 3
Contents
Preface ...............................................................................................................................5
Summary Tables of Changes..................................................................................................7
Identification Information ....................................................................................................15
Errata...............................................................................................................................17
Specification Changes .........................................................................................................55
Specification Clarifications ...................................................................................................56
Documentation Changes......................................................................................................57

4Specification Update
Revision History
Document
Number Revision Description Date
316515 -001 Initial release February 2007
316515 -002 •Added T2080 product SKU March 2007
316515 -003 •Updated erratum AN45
•Updated Summary Table of Changes
April 2007
316515 -004 •Updated Summary Table of Changes July 2007
316515 -005 •Added processors for the Mobile 965 Express Chipset
Family
•Added M-0 stepping errata
August 2007
316515 -006 •Added Processors based on the Intel Mobile 965 series
chipset.
•Added M-0 Errata and Microcode in separate tables
•Removed Errata AN11, AN19, AN21, AN42, AN55, AN63,
AN 69, AN72, AN74, AN79, AN83, AN96, AN104, AN5S
and AN11S.
•Updated Errata AN45
September 2007
316515 -007 •Added AN106 – AN109 October 2007
316515 -008 •Added AN110 November 2007
316515 -009 •Updated Summary Table of Changes - Added AU - AY
•Updated AN34
•Added AN111
December 2007
316515 -010 •Added AN112 November 2010
§

Preface
Specification Update 5
Preface
This document is an update to the specifications contained in the documents listed in
the following Affected Documents table. It is a compilation of device and document
errata and specification clarifications and changes, and is intended for hardware
system manufacturers and for software developers of applications, operating system,
and tools.
Information types defined in the Nomenclature section of this document are
consolidated into this update document and are no longer published in other
documents. This document may also contain information that has not been previously
published.
Affected Documents
Document Title Document
Number/Location
Intel® Pentium® Dual-Core Processor Mobile Processor Datasheet 316519
Intel® Pentium® Dual-Core Processor for Intel® 965 Express Chipset
Family Datasheet 318125
Related Documents
Document Title Document
Number/Location
Debug Port Design Guide for Crestline and Intel® 945PM/GM/GT and
940GML Express Chipset Systems Note
Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 1: Basic Architecture 253665
Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 2A: Instruction Set Reference, A-M 253666
Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 2B: Instruction Set Reference, N-Z 253667
Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 3A: System Programming Guide 253668
Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 3B: System Programming Guide 253669
Intel® 64 and IA-32 Architectures Optimization Reference Manual 248966
Intel® 64 and IA-32 Architectures Optimization Reference Manual
Documentation Changes 252046

Preface
6Specification Update
Nomenclature
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics (e.g., core speed, L2 cache size, package
type, etc.) as described in the processor identification information table. Care should
be taken to read all notes associated with each S-Spec number
Errata are design defects or errors. Errata may cause the products’ behavior to
deviate from published specifications. Hardware and software designed to be used
with any given stepping must assume that all errata documented for that stepping are
present on all devices.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications
will be incorporated in the next release of the specifications.
Documentation Changesinclude typos, errors, or omissions from the current
published specifications. These changes will be incorporated in the next release of the
specifications.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, etc.).
§

Summary Tables of Changes
Specification Update 7
Summary Tables of Changes
The following table indicates the Specification Changes, Errata, Specification
Clarifications or Documentation Changes, which apply to the listed Processor
steppings. Intel intends to fix some of the errata in a future stepping of the
component, and to account for the other outstanding issues through documentation or
Specification Changes as noted. This table uses the following notations:
Codes Used in Summary Table
Stepping
X: Erratum, Specification Change or Clarification that applies
to this stepping.
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification
change does not apply to listed stepping.
Status
Doc: Document change or update that will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the
product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Shaded: This item is either new or modified from the previous
version of the document.

Summary Tables of Changes
8Specification Update
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
Specification Updates:
A = Dual-Core Intel® Xeon® processor 7000Δsequence
C = Intel® Celeron® processor
D = Dual-Core Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor
I = Dual-Core Intel® Xeon® processor 5000Δseries
J = 64-bit Intel® Xeon® processor MP with 1-MB L2 cache
K = Mobile Intel® Pentium® III processor
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel ® Pentium® 4 processor
O = Intel ® Xeon® processor MP
P = Intel ® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading Technology on
90-nm process technology
R = Intel® Pentium® 4 processor on 90-nm process
S = 64-bit Intel® Xeon® processor with 800-MHz system bus (1-MB and 2-MB L2
cache versions)
T = Mobile Intel® Pentium® 4 processor–M
U = 64-bit Intel® Xeon® processor MP with up to 8-MB L3 cache
V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA Package
W= Intel® Celeron®-M processor
X = Intel® Pentium® M processor on 90-nm process with 2-MB L2 cache and Intel®
Processors A100 and A110 with 512-kB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533-MHz system bus
AA= Intel® Pentium® D Processor 900ΔSequence and Intel® Pentium® processor
Extreme Edition 955Δ, 965Δ
AB= Intel® Pentium® 4 processor 6x1 sequence
AC= Intel® Celeron® processor in 478-pin package
AD = Intel® Celeron® D processor on 65-nm process
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65-nm
process
AF = Dual-Core™ Intel® Xeon® processor LV
AG = Dual-Core Intel® Xeon® processor 5100Δseries
AH= Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor
technology
AI = Intel® Core™2 Extreme processor X6800Δand Intel®Core™2 Duo Desktop
processor E6000Δand E4000Δsequence
AJ = Quad-Core Intel® Xeon® processor 5300Δseries

Summary Tables of Changes
Specification Update 9
AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel®
Core™2 Quad processor Q6000 sequence
AL = Dual-Core Intel® Xeon® processor 7100 Δseries
AM = Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® Dual-Core processor
AO = Quad-Core Intel® Xeon® processor 3200Δseries
AP = Dual-Core Intel® Xeon® processor 3000Δseries
AQ = Intel® Pentium® Dual-Core Desktop processor E2000Δsequence
AR = Intel® Celeron® Processor 500Δseries
AS = Intel® Xeon® processor 7200, 7300Δseries
AT = Intel® Celeron® processor 200 series
AU = Mobile Value Celeron
AV = Intel® Core™2 Extreme Processor QX9000 Sequence and Intel® Core™2 Quad
Processor Q9000 Sequence processor
AX = Quad-Core Intel® Xeon® Processor 5400 Series
AY = Wolfdale DP
Note: ΔIntel processor numbers are not a measure of performance. Processor numbers
differentiate features within each processor family, not across different processor
families. See http://www.intel.com/products/processor_number for details.
Errata for Intel® Pentium® Dual-Core Mobile Processors
Number D0 M0 Plans ERRATA
AN1 X Fixed FST Instruction with Numeric and Null Segment Exceptions May
Take Numeric Exception with Incorrect FPU Operand Pointer
AN2 X X No Fix Code Segment Limit Violation May Occur on 4-Gbyte Limit Check
AN3 Erratum Removed
AN4 X X No Fix REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an
Incorrect Data Size or Lead to Memory-Ordering Violations
AN5 X Fixed Memory Aliasing with Inconsistent A and D Bits May Cause
Processor Deadlock
AN6 X X No Fix VM Bit Is Cleared on Second Fault Handled by Task Switch from
Virtual-8086 (VM86)
AN7 X Fixed Page with PAT (Page Attribute Table) Set to USWC (Uncacheable Speculative Write Combine) While Associated MTRR (Memory Type
Range Register) Is UC (Uncacheable) May Consolidate to UC
AN8 X Fixed FPU Operand Pointer May Not Be cleared following FINIT/FNINIT
AN9 X Fixed LTR Instruction May Result in Unexpected Behavior
AN10 X Fixed Invalid Entries in Page-Directory-Pointer-Table Register (PDPTR) May Cause General Protection (#GP) Exception if the Reserved Bits
are Set to One
AN11 Fixed Erratum Removed

Summary Tables of Changes
10 Specification Update
Number D0 M0 Plans ERRATA
AN12 X Fixed FP Inexact-Result Exception Flag May Not Be Set
AN13 X Fixed A Locked Data Access that Spans Across Two Pages May Cause the
System to Hang
AN14 X X No Fix MOV To/From Debug Registers Causes Debug Exception
AN15 X X No Fix INIT Does Not Clear Global Entries in the TLB
AN16 X Fixed Use of Memory Aliasing with Inconsistent Memory Type May Cause
System Hang
AN17 X Fixed Machine Check Exception May Occur when Interleaving Code
Between Different Memory Types
AN18 Erratum removed
AN19 Erratum removed
AN20 X X No Fix LOCK# Asserted During a Special Cycle Shutdown Transaction May
Unexpectedly Deassert
AN21 Erratum removed
AN22 X X No Fix Last Branch Records (LBR) Updates May be Incorrect After a Task
Switch
AN23 X X No Fix Address Reported by Machine-Check Architecture (MCA) on Single-
bit L2 ECC Errors May be Incorrect
AN24 X Fixed Disabling of Single-step On Branch Operation May be Delayed
following a POPFD Instruction
AN25 X Fixed Performance Monitoring Counters that Count External Bus Events
May Report Incorrect Values after Processor Power State Transitions
AN26 X X No Fix VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the
Last Exception Record (LER) MSR
AN27 X X No Fix General Protection (#GP) Fault May Not Be Signaled on Data
Segment Limit Violation Above 4-G Limit
AN28 X Fixed Performance Monitoring Events for Retired Floating Point Operations
(C1h) May Not be Accurate
AN29 X
X No Fix DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring
Count for Saturating SIMD Instructions Retired (Event CFH)
AN30 X Fixed Global Pages in the Data Translation Look-Aside Buffer (DTLB) May Not Be Flushed by RSM instruction before Restoring the
Architectural State from SMRAM
AN31 X Fixed Data Breakpoint/Single Step on MOV SS/POP SS May be Lost after
Entry into SMM
AN32 X Fixed CS Limit Violation on RSM May be Serviced before Higher Priority
Interrupts/Exceptions
AN33 Erratum removed
AN34 X X No Fix Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
Before Higher Priority Interrupts