Intel PXA27x Series Technical manual

Intel® PXA27x Processor Family
Specification Update
October 2004
.Notice: The Intel® PXA27x Processor Family may contain design defects or errors known as
errata that may cause the product to deviate from published specifications. Current characterized
errata are documented in this specification update.
Order Number: 280071-003

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Intel® PXA27x Processor Family Specification Update 3
Revision History
Revision History
Revision Date Version Description
October, 2004 003 Added Errata 51, 52, 53, 54
August, 2004 002 Added Errata 48, 49, 50
Added Documentation Changes 5- 15
April, 2004 001 First publication

4Intel® PXA27x Processor Family Specification Update
Preface
Preface
This document contains updates to the specifications for the Intel® PXA27x Processor Family,
listed in Table 1.This document is a compilation of device and documentation errata, specification
clarifications, and specification changes. It is intended for hardware system manufacturers and
software developers of applications, operating systems, and tools.
Intel Corporation has endeavored to include all documented errata in the consolidation process.
However, Intel makes no representations or warranties concerning the completeness of the Intel®
PXA27x Processor Family Specification Update.
Information types defined in Nomenclature are consolidated into the Intel® PXA27x Processor
Family Specification Update and are no longer published in other documents.
This document might also contain information that was not previously published.

Intel® PXA27x Processor Family Specification Update 5
Affected and Related Documents
Affected and Related Documents
Table 1 lists the documents affected by and related to this errata update.
Contact an Intel® representative to obtain the latest revisions of these documents.
Table 1. Affected Documents / Related Documents
Title
Intel® PXA27x Processor Family Developer’s Manual
Intel® PXA27x Processor Family Design Guide
Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification

6Intel® PXA27x Processor Family Specification Update
Nomenclature
Nomenclature
Errata are design defects or errors. These errata might cause the Intel® PXA27x Processor
Family’s behavior to deviate from published specifications.Hardware and software designed to be
used with any given processor stepping must assume that all errata documented for that stepping
are present on all devices unless otherwise noted.
Documentation changes include typos, errors, and omissions from the current published
specifications. These changes will be incorporated in the next release of the document.
Specification clarifications describe a specification in greater detail or further highlight a
specification’s impact to a complex design situation. These clarifications will be incorporated in
any new release of the document.
Specification changes are modifications to the current published specifications. These changes
will be incorporated in the next release of the document.
Note: Errata remain in the specification update throughout the product’s life cycle, or until a particular
stepping is no longer commercially available. Under these circumstances, errata removed from the
specification update are archived and made available upon request. Specification changes,
specification clarifications, and documentation changes are removed from the specification update
when the appropriate changes are made to the appropriate product specification or user
documentation (data sheets, manuals, and so forth).

Intel® PXA27x Processor Family Specification Update 7
Intel® PXA27x Processor Family Package Markings
Intel® PXA27x Processor Family
Package Markings
The following figure depicts the location, on specific Intel® PXA27x Processor Family packages,
where the actual markings are located. Actual markings are described in Table 2.
Table 2 describes the actual markings that are on the package at the location indicated by “LINE x”
for each package offered.
Figure 1.Intel® PXA27x Processor Family Package Markings Locations
i
“LINE 1”
PIN 1 INDICATOR for PXA270 Processor
“LINE 2”
“LINE 3”
“LINE 4”
“LINE 5”
“LINE 6”
PIN 1 INDICATOR
for PXA271 and PXA272
Processor Family

8Intel® PXA27x Processor Family Specification Update
Intel® PXA27x Processor Family Package Markings
Note: This table is for example only. It must not be used to determine final production offerings.
Table 2. Example Processor Package Markings (For Example Only)
Discrete/
MCP 13x13 T-PBGA 13x13 T-PBGA 14x14 FFCSP/ 256LTyax/256SD 14x14 FFCSP/ 256LTyax/256SD 14x14 FFSCP/ 2x256L Tyax
Max.
Freq. 624 MHz 416 MHz 312 MHz 520 MHz 416 MHz
Lead/
Lead Free Lead (Pb) Lead (Pb) Free Lead (Pb) Lead (Pb) Free Lead (Pb) Free
Stepping C0 C0 C0 C0 C0
Line 1 RCPXA270C0C624 RTPXA270C0C416 LVPXA271FC0312 RVPXA272FC0520 RVPXA272FC0416
Line 2 {FPO#} {FPO#} {MCP FPO#} {MCP FPO#} {MCP FPO#}
Line 3 {QDF#} {QDF#} {QDF#} {QDF#} {QDF#}
Line 4 {M} {C} ’04 {M} {C} ’04 {M} {C} ’04 {M} {C} ’04 {M} {C} ’04
Line 5 ATPO# ATPO# ATPO#
Line 6 COO COO COO

Intel® PXA27x Processor Family Specification Update 9
Summary of Changes
Summary of Changes
The following tables summarize the errata, specification changes, specification clarifications, and
documentation changes that apply to the Intel® PXA27x Processor Family.Intel might fix some of
the errata in a future stepping of the component and account for the other outstanding issues
through documentation or specification changes as noted.These tables use the following notations:
Notation Meaning
XThis erratum exists in the stepping indicated. specification change or clarification that
applies to this stepping.
(No mark) or
(Blank Box) This erratum is fixed in the listed stepping, orthe specification change does not apply to the listed stepping.
Plan Fix This erratum might be fixed in a future stepping of the product.
Fixed This erratum has been previously fixed.
No Fix There are no plans to fix this erratum.
Doc Intel plans to update the appropriate documentation in a future revision.
No Bug This erratum has been determined to be a false erratum.
Shaded This item is either new or modified from the previous version of the document.
Table 3. Summary of Errata (Sheet 1 of 3)
References C0 Status
Number Title Page
1CORE: IFU misses an external abort when a lock command is
outstanding 13 XNo Fix
2CORE: Aborted store that hits D-cache might mark write-back
data as dirty 13 XNo Fix
3CORE: Performance Monitor Unit Counts, using performance monitoring event number 0x1, can be incremented erroneously
by unrelated core events 14 XNo Fix
4CORE: In SDS mode, back-to-back memory operations where
the first instruction aborts might hang 14 XNo Fix
5CORE: Lock aborts resulting from I-cache or I-TLB lock
operations are not presented properly on the trace interface 14 XNo Fix
6CORE: CP15 ID register accesses with opcode2> 0b001 return
unpredictable values 15 XNo Fix
7CORE: Disabling and re-enabling the MMU can hang the core
or cause it to execute the wrong code 15 XNo Fix
8CORE: JTAG parallel register updates require an extra TCK
rising edge 16 XNo Fix
9MMC: SPI mode – if card is deselected, PROG_DONE will not
be set 16 XNo Fix
10 MEMC: No MRS command is given when exiting from Alternate Bus Master Mode when SA1111 Address Muxing Mode is
enabled 16 XNo Fix

10 Intel® PXA27x Processor Family Specification Update
Summary of Changes
11 KBD: Extra Keypad matrix interrupt in IMKP Mode 16 XNo Fix
12 USBH: USBH Register UHCRHPSx[CCS] Bit Set Incorrectly
After Power On 17 XNo Fix
13 AC97: Command Done bit remains set after an AC97 cold reset 17 XNo Fix
14 POWER MANAGER: Fast Ramp rates on voltage pins can
cause high current consumption. 17 XNo Fix
15 LCD: Reconfiguring the LCD controller retains the previous PPL
value for the first line. 18 XNo Fix
16 MSHC: Memory Stick does not come out of SLEEP mode after
wake up process. 19 XNo Fix
17 LCD: Overlay1 is not enabled intermittently after re-enabling
LCD. 19 XPlan Fix
18 POWER MANAGER: Processor ignores BATT/VCC faults while
exiting sleep mode. 20 XNo Fix
19 KBD: Keyboard Edge-Detect Status Register Incorrect After
Standby Mode Wakeup. 20 XNo Fix
20 UART: Character Timeout interrupt remains set under certain
software conditions 21 XNo Fix
21 LCD: LCD not enabling in dual panel mode. 21 XNo Fix
22 UDC: UDC does not correctly support alternate interfaces. 22 XNo Fix
23 ICP: Receiver Aborts randomly occur prematurely and without
End of frame/Error in FIFO interrupt 23 XNo Fix
24 SSP: OSTimer counter increments incorrectly for SSP Frames
in Network mode 23 XNo Fix
25 LCD: Enabling Overlay 2 for YUV420 hangs LCD controller. 23 XPlan Fix
26 USBOTG: Unable to measure duration of Single-Ended Zero
(SE0) for Session Request Protocol (SRP) 24 XPlan Fix
27 MEMC: Write/Read to/from SDRAM can collide with alternate
bus master mode when MDREFR:ALTREFB is set. 25 XNo Fix
28 Power Manger: Core hangs during voltage change when there
are outstanding transactions on the bus 25 XNo Fix
29 MMC: MMC unit in SPI mode always waits a minimum of 1 Ncx cycles, even though the MMC spec dictates that SPI mode
CMD9 can have a minimum of 0 Ncx cycles. 27 XPlan Fix
30 SD: SD Controller in SPI mode not receiving data response for
CMD9 and CMD10 from some SD Cards 27 XPlan Fix
31 MEMC: SDRAM Refresh Commands are issued too often
during a VLIO access while BREQ is asserted. 28 XNo Fix
32 Interrupt Controller: Unexpected exception vector when
ICCR[DIM]=0 and ICMR=0. 28 XNo Fix
33 SSP: TXD line does not tristate when SSP is Slave to Frame 29 XNo Fix
34 PowerManager: Simultaneous BATT and VDD faults results in
going to DeepSleep mode twice. 29 XNo Fix
35 CORE: Non-branch instruction in vector table may execute
twice after a thumb mode exception 29 XNo Fix
36 UART: UART does not correctly indicate a Framing Error
Interrupt in DMA mode. 30 XNo Fix
Table 3. Summary of Errata (Sheet 2 of 3)
References C0 Status
Number Title Page

Intel® PXA27x Processor Family Specification Update 11
Summary of Changes
37 CLOCKS: System Hangs when enabling RUN/TURBO
switching at 520MHz 30 XNo Fix
38 CLOCKS: System Hangs when enabling HalfTurbo Switching 31 XNo Fix
39 MEMC: Memory Controller hangs when entering Self Refresh
Mode. 32 XNo Fix
40 SDIO: SDIO Devices Not Working at 19.5 Mbps 32 XPlan Fix
41 AC97: Command Done bit is never set when data is written in
slot12 33 XNo Fix
42 SD/MMC: SD/MMC controller CRC errors with some SD/MMC
cards 33 XPlan Fix
43 USBH: There is no Individual Power Sense Polarity bit for each Host Port. The Power Sense Polarity bit controls the polarity for
all three Host Ports. 33 XPlan Fix
44 KBD: Keypress wakeup from Standby mode is not reliable 34 XNo Fix
45 USBH: USB Host Port 3 in Transceiverless Mode may not work
correctly with an external device. 34 XPlan Fix
46 SD/MMC: SPI mode commands fail even on cards that are
compatible with SPI spec 1.0 35 XPlan Fix
47 CLOCKS AND POWER: PWM Clock Enables do not work as
specified 35 XNo Fix
48 ICP: Occasionally EIF, EOF and CRC interrupt are missed when
a CRC error is received 36 XNo Fix
49 POWER MANAGER: Batt Fault does not always re-enable
GPIO 0 and GPIO 1 as wake-up sources. 36 XNo Fix
50 POWER MANAGER: The processor does not exit from Sleep/
Deep-Sleep Mode. 37 XPlan Fix
51 SDIO: CMD53 multiple block data transfer with block count set
to 0 not supported 37 XNo Fix
52 LCDC: Disable Done Interrupt does not always occur 38 XNo Fix
53 UDC: RCV can not be tied high during UDC transmission when
using an external transceiver 38 XNo Fix
54 AC97: AC97 CAR[CAIP] bit field can be incorrectly set 38 XNo Fix
Table 4. Summary of Specification Changes
References Status
Number Title Page
NOTE: There are no specification changes at this time.
Table 5. Summary of Specification Clarifications
Number Document Revision Page Status Specification Clarifications
NOTE: There are no specification clarifications at this time.
Table 3. Summary of Errata (Sheet 3 of 3)
References C0 Status
Number Title Page

12 Intel® PXA27x Processor Family Specification Update
Summary of Changes
Table 6. Summary of Documentation Changes
Number Document Revision Page Status Documentation Changes
NOTE: There are no documentation changes at this time.

Intel® PXA27x Processor Family Specification Update 13
Errata
Errata
E1. CORE: IFU misses an external abort when a lock command is
outstanding.
Problem: A bus abort occurs on a code fetch while an I-TLB lock mcr is outstanding. The IFU fails to abort,
instead executing the instruction returned on the aborting transaction. Parity errors are not affected.
The bus abort might be due to either an ABORT pin assertion or a multi-bit ECC error on the core.
On the core, the bus abort can occur as the result of a master abort, a target abort, or a single data
phase disconnect on the system bus.
Implication: TBD
Workaround: Branch flush after every ITLB or I-cache lock.
Status: No Fix
E2. CORE: Aborted store that hits D-cache might mark write-back data as
dirty.
Problem: If an aborted store hits clean data in the data cache (data in an aligned four-word range that has not
been modified from the core since it was last loaded in from memory or cleaned), the data in the
array will not be modified (the store will be blocked), but the dirty bit will be set.
When that line is then aged out of the data cache or explicitly cleaned, the data in that four-word
range will be evicted to external memory, even though it has never been changed. In normal
operation, this will be nothing more than an extra store on the bus that writes the same data to
memory as is already there.
This problem might be visible at the following boundary condition:
1. A cache line is loaded into the cache at address A
2. Another master externally modifies address A
3. An Intel XScale® core store instruction attempts to modify A, hits the cache,aborts because of
MMU permissions, and is backed out the of cache. That line should not be marked “dirty”, but
because of this defect it will be.
4. The cache line at A then ages out or is explicitly cleaned. The original data from location A
will be evicted to external memory, overwriting the data written by the external master.
This situation happen sonly if software is allowing an external master to modify memory that is
write-back or write-allocate in the XScale page tables, and depending on the fact that the data is not
dirty in the XScale cache to preclude the cached version from overwriting the external memory
version. If there are any semaphores or any other handshaking to prevent collisions on shared
memory, this should not be a problem.
Implication: TBD
Workaround: For a shared memory region, mark it as write-through memory in the XScale page table to prevent
the data from ever being written out as dirty, so the defect does not appear. Alternatively, ensure
that any cached copy of the data in external memory is invalidated if an external agent modifies the
external copy.
Status: No Fix

14 Intel® PXA27x Processor Family Specification Update
Errata
E3. CORE: Performance monitor unit counts, using performance
monitoring event number 0x1, can be incremented erroneously by
unrelated core events.
Problem: The performance monitor unit can be used to count cycles in which the I-cache cannot deliver an
instruction. Performance monitoring event number 0x1 is used for this. According to EAS text, the
only cycles counted should be those due to an I-cache miss or an I-TLB miss. The following
unrelated events in the core also cause the corresponding count to increment when event number
0x1 is being monitored:
•Any architectural event (e.g. IRQ, data abort)
•mstr instructions that alter the CPSR control bits
•Some branch instructions, including indirect branches and those mis-predicted by the BTB
•CP15 mcr instructions to registers 7, 8, 9, or 10 which involve the I-cache or the I-TLB
Each of the items above might cause the performance monitoring count to increment several times.
The resulting performance monitoring count might be higher than expected if the above items
occur, but never lower. The performance monitor unit uses ic_instValid_qf2h. This signal asserts
not just at the proper time, but also due to the events described above.
Implication: TBD
Workaround: There is no way to obtain the correct number of cycles stalled due to I-cache misses and I-TLB
misses. One component of the unwanted noise may be filtered out: extra counts due to branch
instructions mis-predicted by the BTB. The number of mispredicted branches can also be
monitored using performance monitoring event 0x6 during the same time period as event 0x1. The
mispredicted branch number can then be subtracted from the I-cache stall number generated by the
performance monitor to get a value closer to the correct one. Depending on the nature of the code
monitored, this workaround might have limited value.
Status: No Fix
E4. CORE: In SDS mode, back-to-back memory operations where the first
instruction aborts might hang.
Problem: If back-to-back memory operations occur in SDS (special debug state, used by ICE and debug
vendors) and the first memory operation gets a precise data abort, the first memory operation is
correctly cancelled and no abort occurs. However, depending on the timing, the second memory
operation might not work correctly. The data cache might internally cancel the second operation,
but the register file may have scoreboarded registers for that second memory operation.
The effect is that the part might hang (due to a permanently scoreboarded register) or that a store
operation might be cancelled incorrectly.
Implication: TBD
Workaround: In SDS, any memory operation that might cause a precise data abort should be followed by a write-
buffer-drain operation. This operation precludes additional memory operations from being in the
pipe when the abort occurs. Do not use load multiple/store multiple, which might cause precise
data aborts.
Status: No Fix
E5. CORE: Lock aborts resulting from I-cache or I-TLB lock operations
are not presented properly on the trace interface.
Problem: This problem affects only processors that use the core’s trace interface. An I-cache or I-TLB lock
operation that results in lock abort creates a unique internal pipeline signal timing that causes

Intel® PXA27x Processor Family Specification Update 15
Errata
trouble on the trace interface, which results in the core reporting the event as if it came with the
next instruction executed after the aborting lock instruction, the data abort vector.
Implication: TBD
Workaround: None.
Status: No Fix
E6. CORE: CP15 ID register accesses with opcode2 > 0b001 return unpre-
dictable values.
Problem: The XScale core does not implement CP15 ID codes registers other than the Main ID register
(opcode2 = 0b000) and the Cache Type register (opcode2 = 0b001). If any of the unimplemented
registers are accessed by software (for example, mrc p15, 0, r3, c15, c15, 2), the value of the Main
ID register should be returned. Instead, an unpredictable value is returned.
Implication: TBD
Workaround: None.
Status: No Fix
E7. CORE: Disabling and re-enabling the MMU can hang the core or
cause it to execute the wrong code.
Problem: If the MMU is disabled via the CP15 control register after being enabled, certain timing cases can
cause the processor to hang. In addition, re-enabling the MMU after disabling it can cause the
processor to fetch and execute code from the wrong physical address. To avoid these issues, the
code sequence below must be employed whenever disabling the MMU or re-enabling it afterwards.
Implication: TBD
Workaround: The following code sequence must be used to disable and/or re-enable the MMU safely. The
alignment of the mcr instruction that disables or re-enables the MMU must be controlled carefully,
so that it lies in the first word of an instruction cache line:
;//@ The following code sequence takes r0 as a parameter. The value of r0 will be
;//@ written to the CP15 control register to either enable or disable the MMU.
mcr p15, 0, r0, c10, c4, 1 ;// @ unlock I-TLB
mcr p15, 0, r0, c8, c5, 0 ;//@ invalidate I-TLB
mrc p15, 0, r0, c2, c0, 0 ;//@ CPWAIT
mov r0, r0
sub pc, pc, #4
b AfterAlign ;//@ branch to aligned code
ALIGN 32 ;//@ align to 32 bytes
AfterAlign
mcr p15, 0, r0, c1, c0, 0 ;//@ enable/disable MMU, caches
mrc p15, 0, r0, c2, c0, 0 ;//@ CPWAIT
mov r0, r0
sub pc, pc, #4
Status: No Fix

16 Intel® PXA27x Processor Family Specification Update
Errata
E8. CORE: JTAG parallel register updates require an extra TCK rising
edge.
Problem: The IEEE 1149.1 spec states that the effects of updating all parallel JTAG registers should be seen
on the falling edge of TCK in the Update-DR state. The XScale core parallel JTAG registers
incorrectly require an extra TCK rising edge to make the update visible. Therefore, operations like
hold-reset, JTAG break, and vector traps require either an extra TCK cycle by going to run-test-idle
or by cycling through the state machine again to trigger the expected hardware behavior.
Implication: TBD
Workaround: If the JTAG interface is polled continuously, this erratum has no effect. If not, an extra TCK cycle
can be caused by going to run-test-idle after writing a parallel JTAG register.
Status: No Fix
E9. MMC: SPI mode – if card is deselected, PROG_DONE will not be set.
Problem: If changing SPI chip selects, the PROG_DONE bit does not get updated with the state of the
selected card.
Implication: If programming card0, then switch to card1, then come back to card0, there is no way of knowing
if card0 ever finished programming.
Workaround: User can switch the MMDAT signal functionality to GPIO functionality and monitor the signal by
reading the GPIO Status register until the signal goes high.
Status: No Fix
E10. MEMC: No MRS command is given when exiting from alternate bus
master mode when SA-1111 address muxing mode is enabled.
Problem: When using alternate bus master with MDCNFG[SA1110x] set, after the alternate bus master has
given the bus back to the processor, if the first access by the processor is a VLIO access, the MRS
commands to switch the SDRAMs back into burst-of-4 mode occurs after a long delay. If SDRAM
is accessed before the MRS command is performed, data returned to the processor registers will not
be valid.
Implication: TBD
Workaround: Use any of the following options to workaround this erratum:
•Do not use SA-1111 address muxing mode with an alternate bus master.
•The alternate bus master can perform the MRS command to put the SDRAM into burst-of-4
mode before de-asserting the MBREQ signal.
Status: No Fix
E11. KBD: Extra keypad matrix interrupt in IMKP mode.
Problem: An unexpected interrupt during keypad-matrix manual scan in ignore-multiple-keypress mode
(IMKP). The test consists of pressing one, single, valid key and holding it down, then pressing a
second, single, valid key and holding it down, then both pressed keys are released simultaneously.
This test results in three vectors to the interrupt-service routine where two are expected.
The first vector to the ISR occurs on first key down. The second vector is unexpected. This is
possibly caused by the second key down. The third vector occurs approximately at the time of all
keys up.
Debounce interval = 3ms, KPC[IMKP] = 1, KPC[ASACT] = 0; KPC[MI] = 1.

Intel® PXA27x Processor Family Specification Update 17
Errata
Implication: TBD
Workaround: Do not set KPKDI[Interval] to less than 10ms.
Status: No Fix
E12. USBH: USBH register UHCRHPSx[CCS] bit set incorrectly afterpower
on
Problem: The UHCRHPSx[CCS] bit may be set after power on reset. Under normal conditions, when set,
this bit indicates that a USB device is connected to the USB host port. The error is that this bit is
being set even though there is no device physically connected to the USB host unit.
Implication: TBD
Workaround: Disable global port power for the USB host unit. Only enable individual port power for the USB
host ports that will be used in the system.
Status: No Fix
E13. AC97: Command-done bit remains set after an AC97 cold reset.
Problem: After an AC97 cold reset is asserted (GCR[nCRST]=0) when the AC97 controller unit is enabled
again, the command-done bit (GSR[CDONE]) is getting set when it should not.
1. Enable the AC97 unit.
2. Enable the codec.
3. Write some data to the codec register using AClink.
4. Wait for command-done bit (GSR[CDONE]) to set and then clear it.
5. Shut down the codec by writing 0x1000 to codec address 0x26.
6. Wait for command-done bit (GSR[CDONE]) to set and then clear it.
7. Generate wakeup event from Codec and wait for primary codec resume bit (GSR[PRESINT])
or secondary codec resume bit (GSR[SRESINT]) to set.
8. Once resume bit is set, assert a cold reset by writing 0 to GCR[nCRST].
9. Enable the AC97 controller and read the GSR. The command-done bit is set; however, it
should be clear.
Implication: TBD
Workaround: After asserting cold reset, the GSR[CDONE] bit must be cleared by writing a 1 to GSR[CDONE].
Status: No Fix
E14. POWER MANAGER: Fast ramp rates on voltage pins can cause high
current consumption.
Problem: If voltage rise/stabilization time is too fast for any of the voltage pins (VCC_core, VCC_mem,
VCC_batt, etc.), then the internal circuitry causes high current consumption on these voltage pins.
This condition will not damage the internal circuitry of the processor. The duration of the high
current consumption is less than 20µsec.
The following describes the current consumption in order of voltage domain bootup sequence.
•If the voltage rise/stabilization time of VCC_BATT is longer than 500µsec at room
temperature, then the combined current on VCC_BATT will be less than 100mA for less than
20µsec.

18 Intel® PXA27x Processor Family Specification Update
Errata
•If the voltage rise/stabilization time of VCC_USB, VCC_IO, VCC_MEM, VCC_BB,
VCC_LCD, VCC_USIM is longer than 500µsec at room temperature, then the combined
current on VCC_USB, VCC_IO, VCC_MEM, VCC_BB, VCC_LCD, VCC_USIM will be
less than 500mA for less than 20µsec.
•If the voltage rise/stabilization time of VCC_CORE, VCC_SRAM, VCC_PLL is longer than
500µsec at room temperature, then the combined current on VCC_CORE, VCC_SRAM,
VCC_PLL will be less than 100mA for less than 20µsec.
Example of battery life consumption:
— Assume square current spike = 850mA = 0.85Coulomb/sec
— Current drain of the current spike lasting 100µsec
— 0.85 Coulomb/sec * 0.0001 sec = 85 µCoulomb total drain
— Assume 150mA-hr battery = 540 Coulombs
— Calculate current spike percentage of total battery capacity: 85µC / 540C = 1.57 e-7
— Current spike consumes only 0.0000157% of battery capacity.
Implication: High current consumption on processor voltage supply pins can cause external power management
circuitry to enter into an error/shutdown condition.
Workaround: Voltage rise/stabilization time must be determined by the system designer to mitigate any error
condition on external circuitry.
Status: No Fix
E15. LCD: Reconfiguring the LCD controller retains the previous PPL
value for the first line.
Problem: If you program the LCD controller for one configuration, then disable the LCD controller and
program it for another configuration and enable it again, the first line retains the pixels-per-line
(PPL) value from the previous configuration.
For example, configuring the LCD to 320x200 and then disabling it and reconfiguring it to
640x480, and enabling it again, the first line retains the PPL value from the previous configuration,
which is 320.
This issue could effect more than just the first frame, due to the fact that the LCD DMA is
initialized with a size to fit the frame size. Datafrom the first frame could spill over into the second
frame, and so on.
Implication: If the wrong number of pixels are sent to the LCD panel for the first line of a frame, the display on
the LCD screen could be corrupt.
Workaround: When configuring the LCD the second time, configure it to the desired LCD configuration, enable
the LCD, disable it, and then enable it again, for the third time. This ensures that when the LCD
controller is enabled for the third time, it will begin the frame with the right PPL value.
Status: No Fix
E16. MSHC: Memory Stick does not come out of SLEEP mode after wake
up process.
Problem: The test is trying to put the memory stick to ”SLEEP” and then wake it up by sending the “RESET”
TPC. The manual says that “Memory Stick wakes up and performs a packet processing, when a
packet transfer by SET_CMD TPC or Write_Reg occurs at SL = 1 in Status Register 0”.

Intel® PXA27x Processor Family Specification Update 19
Errata
The memory stick does not wake up after sending a SET_CMD TPC or Write_Reg once. However,
it does wake up on sending SET_CMD TPC or Write_Reg twice. After reading the value of the
MSINT register (address 0x4180_0008)after sending the first TPC, it contains the value
0x0000200D, indicating that a time out error occurred.
After reading the “SLEEP” bit in the “status register 0”, it remains “1” after the first TPC and
changes to “0” after the second TPC, indicating it was asleep after the first TPC transmission and
awake after the second TPC transmission.
How to reproduce:
•Send “SLEEP” SET_CMD TPC.
•Read the Status Register 0 (Sleep bit should be 1).
•Wake up the Memory Stick by sending “RESET” SET_CMD TPC.
•Pause for 10 seconds.
•Read the Status Register 0 (Sleep bit should be 0 but it shows 1).
•Send “RESET” again.
•Read the Status Register 0 (Sleep bit shows 0).
Implication: TBD
Workaround: Software should send two reset TPC commands to the Memory Stick. Memory Stick wakes up
after two reset TPCs.
Status: No Fix
E17. LCD: Overlay1 is not enabled intermittently after re-enabling LCD.
Problem: When enabling and disabling LCD several times, intermittently, Overlay1 output is all zeros
instead of intended frame buffer overlay pattern. Overlay2 works fine.
Implication: TBD
Workaround: Option1:
Users must not use Overlay 1 but can use Overlay 2.
Option2: Users can use Overlay 1 by:
1. Programming the LCD registers
2. Enabling the LCD (LCCR0[ENB] = 1)
3. Disabling the LCD (LCCR0[DIS] = 1)
4. Reprogramming the lcd registers but not the overlay1/cursor registers. Also, do not write
DMA FDADR registers
5. Enabling the LCD (LCCR0[ENB] = 1)
6. Performing a quick disable of the LCD (LCCR0[ENB] = 0)
7. Programming the DMA registers
8. Enabling the LCD (LCCR0[ENB] = 1)
9. Updating the overlay/cursor registers if required. Follow the instructions mentioned in the
manual in section 7.4.7 for overlay1 and 7.4.10 for cursor as to how to change the overlay/
cursor registers dynamically when the LCD is enabled.

20 Intel® PXA27x Processor Family Specification Update
Errata
Status: Plan Fix
E18. POWER MANAGER: Processor ignores BATT/VCC faults while exiting
sleep mode.
Problem: When asserting nBATT_FAULT or nVCC_FAULT during Sleep mode with the corresponding
IDAE set, and the fault is still present after boot, the part does not enter Deep Sleep. However, if
the IDAE bit is clear, and the fault is still present after boot, the part enters Deep Sleep as expected.
Implication: If a FAULT continues to occur while the processor is exiting Sleep Mode, then the processor is
going to continue to bootup and consume power. There must be enough battery power or the
system must be able to tolerate the fault condition until the workaround below is complete.
Workaround: Before entering sleep or deep sleep via software, first write 1 to the PMCR[IAS] bit to enable
interrupts and then a separate write must be performed to set the desired PMCR[xIDAE] bits.
When the chip exits sleep mode, the interrupt pertaining to Power Management Unit must be
unmasked, ICMR[PWR_I2C] = 0b1, to find out if a fault has occurred. Alternatively, the
PMCR[INTRS] bit can be checked.
Status: No Fix
E19. KBD: Keyboard Edge-Detect Status Register Incorrect After Standby
Mode Wakeup.
Problem: When the processor is in standby mode and it is programmed to wake up by a KeyPad GPIO pulse,
the PKSR (Keyboard Edge detect Status) does not correctly report the GPIO that caused the
Wakeup.
Scenario 1 (Correct):
If only one keypad GPIO is pulsed, and it is programmed to wakeup from standby in PKWR,
the PKSR reports the correct GPIO as the source of the wakeup as expected.
Scenario 2 (Incorrect):
If ALL keypad GPIOs are pulsed but only one is programmed in PKWR to wake up, the PKSR
reports all the GPIOs (except for the ones in use) as the source of the wakeup. This is wrong,
since only one GPIO was programmed to wake up, regardless of the fact that all GPIOs were
pulsed.
Therefore, the following documentation will be added to the Developer’s Manual:
"If any of the PKWR bits are enabled, then only the keypad related to that PKWR will cause a
wakeup. If there is any other activity (active high) on any other keypad pins at this time, then
irrespective of its PKWR setting, it will be registered into the PKSR."
Implication: The user will not be able to detect which keypress woke the processor out of Standby mode.
Workaround: The workaround is to only use PKSR as an indicator that a keypress woke the processor. The user
will not be able to tell which key woke the processor.
Status: No Fix
E20. UART: Character Timeout interrupt remains set under certain
software conditions
Problem: The issue is that randomly the character timeout interrupt does not clear and the DR bit is not set.
The failure was reproduced by adding a software delay loop inside the character timing interrupt
routine between reads from the FIFO. The test continuously repeats and increases the software
delay. After a few iterations, the tests get into a continuous interrupt loop, where the character
timeout interrupt is set, but there is not any data in the FIFO. If the delay loop is placed just outside