Intel PXA27x Series Technical manual

Intel® PXA27x Processor Family
Specification Update
October 2004
.Notice: The Intel® PXA27x Processor Family may contain design defects or errors known as
errata that may cause the product to deviate from published specifications. Current characterized
errata are documented in this specification update.
Order Number: 280071-003

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Intel® PXA27x Processor Family Specification Update 3
Revision History
Revision History
Revision Date Version Description
October, 2004 003 Added Errata 51, 52, 53, 54
August, 2004 002 Added Errata 48, 49, 50
Added Documentation Changes 5- 15
April, 2004 001 First publication

4Intel® PXA27x Processor Family Specification Update
Preface
Preface
This document contains updates to the specifications for the Intel® PXA27x Processor Family,
listed in Table 1.This document is a compilation of device and documentation errata, specification
clarifications, and specification changes. It is intended for hardware system manufacturers and
software developers of applications, operating systems, and tools.
Intel Corporation has endeavored to include all documented errata in the consolidation process.
However, Intel makes no representations or warranties concerning the completeness of the Intel®
PXA27x Processor Family Specification Update.
Information types defined in Nomenclature are consolidated into the Intel® PXA27x Processor
Family Specification Update and are no longer published in other documents.
This document might also contain information that was not previously published.

Intel® PXA27x Processor Family Specification Update 5
Affected and Related Documents
Affected and Related Documents
Table 1 lists the documents affected by and related to this errata update.
Contact an Intel® representative to obtain the latest revisions of these documents.
Table 1. Affected Documents / Related Documents
Title
Intel® PXA27x Processor Family Developer’s Manual
Intel® PXA27x Processor Family Design Guide
Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification

6Intel® PXA27x Processor Family Specification Update
Nomenclature
Nomenclature
Errata are design defects or errors. These errata might cause the Intel® PXA27x Processor
Family’s behavior to deviate from published specifications.Hardware and software designed to be
used with any given processor stepping must assume that all errata documented for that stepping
are present on all devices unless otherwise noted.
Documentation changes include typos, errors, and omissions from the current published
specifications. These changes will be incorporated in the next release of the document.
Specification clarifications describe a specification in greater detail or further highlight a
specification’s impact to a complex design situation. These clarifications will be incorporated in
any new release of the document.
Specification changes are modifications to the current published specifications. These changes
will be incorporated in the next release of the document.
Note: Errata remain in the specification update throughout the product’s life cycle, or until a particular
stepping is no longer commercially available. Under these circumstances, errata removed from the
specification update are archived and made available upon request. Specification changes,
specification clarifications, and documentation changes are removed from the specification update
when the appropriate changes are made to the appropriate product specification or user
documentation (data sheets, manuals, and so forth).

Intel® PXA27x Processor Family Specification Update 7
Intel® PXA27x Processor Family Package Markings
Intel® PXA27x Processor Family
Package Markings
The following figure depicts the location, on specific Intel® PXA27x Processor Family packages,
where the actual markings are located. Actual markings are described in Table 2.
Table 2 describes the actual markings that are on the package at the location indicated by “LINE x”
for each package offered.
Figure 1.Intel® PXA27x Processor Family Package Markings Locations
i
“LINE 1”
PIN 1 INDICATOR for PXA270 Processor
“LINE 2”
“LINE 3”
“LINE 4”
“LINE 5”
“LINE 6”
PIN 1 INDICATOR
for PXA271 and PXA272
Processor Family

8Intel® PXA27x Processor Family Specification Update
Intel® PXA27x Processor Family Package Markings
Note: This table is for example only. It must not be used to determine final production offerings.
Table 2. Example Processor Package Markings (For Example Only)
Discrete/
MCP 13x13 T-PBGA 13x13 T-PBGA 14x14 FFCSP/ 256LTyax/256SD 14x14 FFCSP/ 256LTyax/256SD 14x14 FFSCP/ 2x256L Tyax
Max.
Freq. 624 MHz 416 MHz 312 MHz 520 MHz 416 MHz
Lead/
Lead Free Lead (Pb) Lead (Pb) Free Lead (Pb) Lead (Pb) Free Lead (Pb) Free
Stepping C0 C0 C0 C0 C0
Line 1 RCPXA270C0C624 RTPXA270C0C416 LVPXA271FC0312 RVPXA272FC0520 RVPXA272FC0416
Line 2 {FPO#} {FPO#} {MCP FPO#} {MCP FPO#} {MCP FPO#}
Line 3 {QDF#} {QDF#} {QDF#} {QDF#} {QDF#}
Line 4 {M} {C} ’04 {M} {C} ’04 {M} {C} ’04 {M} {C} ’04 {M} {C} ’04
Line 5 ATPO# ATPO# ATPO#
Line 6 COO COO COO

Intel® PXA27x Processor Family Specification Update 9
Summary of Changes
Summary of Changes
The following tables summarize the errata, specification changes, specification clarifications, and
documentation changes that apply to the Intel® PXA27x Processor Family.Intel might fix some of
the errata in a future stepping of the component and account for the other outstanding issues
through documentation or specification changes as noted.These tables use the following notations:
Notation Meaning
XThis erratum exists in the stepping indicated. specification change or clarification that
applies to this stepping.
(No mark) or
(Blank Box) This erratum is fixed in the listed stepping, orthe specification change does not apply to the listed stepping.
Plan Fix This erratum might be fixed in a future stepping of the product.
Fixed This erratum has been previously fixed.
No Fix There are no plans to fix this erratum.
Doc Intel plans to update the appropriate documentation in a future revision.
No Bug This erratum has been determined to be a false erratum.
Shaded This item is either new or modified from the previous version of the document.
Table 3. Summary of Errata (Sheet 1 of 3)
References C0 Status
Number Title Page
1CORE: IFU misses an external abort when a lock command is
outstanding 13 XNo Fix
2CORE: Aborted store that hits D-cache might mark write-back
data as dirty 13 XNo Fix
3CORE: Performance Monitor Unit Counts, using performance monitoring event number 0x1, can be incremented erroneously
by unrelated core events 14 XNo Fix
4CORE: In SDS mode, back-to-back memory operations where
the first instruction aborts might hang 14 XNo Fix
5CORE: Lock aborts resulting from I-cache or I-TLB lock
operations are not presented properly on the trace interface 14 XNo Fix
6CORE: CP15 ID register accesses with opcode2> 0b001 return
unpredictable values 15 XNo Fix
7CORE: Disabling and re-enabling the MMU can hang the core
or cause it to execute the wrong code 15 XNo Fix
8CORE: JTAG parallel register updates require an extra TCK
rising edge 16 XNo Fix
9MMC: SPI mode – if card is deselected, PROG_DONE will not
be set 16 XNo Fix
10 MEMC: No MRS command is given when exiting from Alternate Bus Master Mode when SA1111 Address Muxing Mode is
enabled 16 XNo Fix

10 Intel® PXA27x Processor Family Specification Update
Summary of Changes
11 KBD: Extra Keypad matrix interrupt in IMKP Mode 16 XNo Fix
12 USBH: USBH Register UHCRHPSx[CCS] Bit Set Incorrectly
After Power On 17 XNo Fix
13 AC97: Command Done bit remains set after an AC97 cold reset 17 XNo Fix
14 POWER MANAGER: Fast Ramp rates on voltage pins can
cause high current consumption. 17 XNo Fix
15 LCD: Reconfiguring the LCD controller retains the previous PPL
value for the first line. 18 XNo Fix
16 MSHC: Memory Stick does not come out of SLEEP mode after
wake up process. 19 XNo Fix
17 LCD: Overlay1 is not enabled intermittently after re-enabling
LCD. 19 XPlan Fix
18 POWER MANAGER: Processor ignores BATT/VCC faults while
exiting sleep mode. 20 XNo Fix
19 KBD: Keyboard Edge-Detect Status Register Incorrect After
Standby Mode Wakeup. 20 XNo Fix
20 UART: Character Timeout interrupt remains set under certain
software conditions 21 XNo Fix
21 LCD: LCD not enabling in dual panel mode. 21 XNo Fix
22 UDC: UDC does not correctly support alternate interfaces. 22 XNo Fix
23 ICP: Receiver Aborts randomly occur prematurely and without
End of frame/Error in FIFO interrupt 23 XNo Fix
24 SSP: OSTimer counter increments incorrectly for SSP Frames
in Network mode 23 XNo Fix
25 LCD: Enabling Overlay 2 for YUV420 hangs LCD controller. 23 XPlan Fix
26 USBOTG: Unable to measure duration of Single-Ended Zero
(SE0) for Session Request Protocol (SRP) 24 XPlan Fix
27 MEMC: Write/Read to/from SDRAM can collide with alternate
bus master mode when MDREFR:ALTREFB is set. 25 XNo Fix
28 Power Manger: Core hangs during voltage change when there
are outstanding transactions on the bus 25 XNo Fix
29 MMC: MMC unit in SPI mode always waits a minimum of 1 Ncx cycles, even though the MMC spec dictates that SPI mode
CMD9 can have a minimum of 0 Ncx cycles. 27 XPlan Fix
30 SD: SD Controller in SPI mode not receiving data response for
CMD9 and CMD10 from some SD Cards 27 XPlan Fix
31 MEMC: SDRAM Refresh Commands are issued too often
during a VLIO access while BREQ is asserted. 28 XNo Fix
32 Interrupt Controller: Unexpected exception vector when
ICCR[DIM]=0 and ICMR=0. 28 XNo Fix
33 SSP: TXD line does not tristate when SSP is Slave to Frame 29 XNo Fix
34 PowerManager: Simultaneous BATT and VDD faults results in
going to DeepSleep mode twice. 29 XNo Fix
35 CORE: Non-branch instruction in vector table may execute
twice after a thumb mode exception 29 XNo Fix
36 UART: UART does not correctly indicate a Framing Error
Interrupt in DMA mode. 30 XNo Fix
Table 3. Summary of Errata (Sheet 2 of 3)
References C0 Status
Number Title Page