Intel NetBurst User manual

A Detailed Look Inside the
Intel®NetBurst™ Micro-Architecture of
the Intel Pentium®4 Processor
November, 2000

A Detailed Look Inside the Intel®NetBurst™Micro-Architecture of the Intel Pentium®4 Processor
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Revision History
Revision Date Revision Major Changes
11/2000 1.0 Release

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Table of Contents
ABOUT THIS DOCUMENT.................................................................................................................5
INTRODUCTION................................................................................................................................6
SIMD TECHNOLOGY AND STREAMING SIMD EXTENSIONS 2.........................................................6
Summary of SIMD Technologies..............................................................................................................................................7
INTEL®NETBURST™ MICRO-ARCHITECTURE.................................................................................9
The Design Considerations of the Intel NetBurst Micro-architecture............................................................................9
Overview of the Intel NetBurst Micro-architecture Pipeline..........................................................................................10
The Front End.............................................................................................................................................................................10
The Out-of-order Core...............................................................................................................................................................11
Retirement...................................................................................................................................................................................11
Front End Pipeline Detail..........................................................................................................................................................11
Prefetching...................................................................................................................................................................................12
Decoder........................................................................................................................................................................................12
Execution Trace Cache..............................................................................................................................................................12
Branch Prediction.......................................................................................................................................................................12
Branch Hints ...............................................................................................................................................................................13
Execution Core Detail................................................................................................................................................................13
Instruction Latency and Throughput......................................................................................................................................13
Execution Units and Issue Ports ..............................................................................................................................................14
Caches..........................................................................................................................................................................................15
Data Prefetch...............................................................................................................................................................................15
Loads and Stores........................................................................................................................................................................16
Store Forwarding........................................................................................................................................................................17

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About this Document
The Intel®NetBurst™micro-architecture is the foundation for the Intel®Pentium
®4 processor. It includes several
important new features and innovations that will allow the Intel Pentium 4 processor and future IA-32 processors to
deliver industry leading performance for the next several years. This paper provides an in-depth examination of the
features and functions the Intel NetBurst micro-architecture.

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Introduction
The Intel®Pentium
®4 processor, utilizing the Intel®NetBurstTM micro-architecture, is a complete processor re-
design that delivers new technologies and capabilities while advancing many of the innovative features, such as
“out-of-order speculative execution” and “super-scalar execution”, introduced on prior Intel®micro-architectural
generations. Many of these new innovations and advances were made possible with the improvements in processor
technology, process technology and circuit design and could not previously be implemented in high-volume,
manufacturable solutions. The features and resulting benefits of the new micro-architecture are defined in the
following sections.
This paper begins with a brief introduction of three generations of single-instruction, multiple-data (SIMD)
technology. The rest of this paper describes the principle of operation of the innovations of Intel Pentium 4
processor with respect to the Intel NetBurst micro-architecture and the implementation characteristics of the
Pentium 4 processor.
SIMD Technology and Streaming SIMD Extensions 2
One way to increase processor performance is to execute several computations in parallel, so that multiple
computations are done with a single instruction. The way to achieve this type of parallel execution is to use the
single-instruction, multiple-data (SIMD) computation technique.
Figure 1 shows a typical SIMD computation. Here two
sets of four packed data elements (X1, X2, X3, and X4,
and Y1, Y2, Y3, and Y4) are operated on in parallel, with
the same operation being performed on each
corresponding pair of data elements (X1 and Y1, X2 and
Y2, X3 and Y3, and X4 and Y4). The results of the four
parallel computations are a set of four packed data
elements.
SIMD computations like those shown in Figure 1 were
introduced into the Intel IA-32 architecture with the Intel
MMX™ technology. The Intel MMX technology allows
SIMD computations to be performed on packed byte,
word, and doubleword integers that are contained in a set
of eight 64-bit registers called the MMX registers (see Figure 2).
The PentiumIII processor extended this initial SIMD computation model with the introduction of the Streaming
SIMD Extensions (SSE). The Streaming SIMD
Extensions allow SIMD computations to be
performed on operands that contain four packed
single-precision floating-point data elements. The
operands can be either in memory or in a set of eight
128-bit registers called the XMM registers (see
Figure 2). The SSE also extended SIMD
computational capability with additional 64-bit MMX
instructions.
The Pentium 4 processor further extends the SIMD
computation model with the introduction of the
Streaming SIMD Extensions 2 (SSE2). The SSE2
extensions also work with operands in either memory
or in the XMM registers. The SSE2 extends SIMD
X4 op Y4 X1 op Y1X2 op Y2X3 op Y3
X4 X1X2X3
Y4 Y1Y2Y3
op opopop
Figure 1 Typical SIMD Operations
Figure 2 Registers available to SIMD Instructions
XMM0
XMM1
XMM2
XMM3
XMM4
XMM5
XMM6
XMM7
128 Bit XMM Registers64 Bit MMX
TM
Registers
MM0
MM1
MM2
MM3
MM4
MM5
MM6
MM7

A Detailed Look Inside the Intel®NetBurst™Micro-Architecture of the Intel Pentium®4 Processor
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computations to operate on packed double-precision floating-point data elements and 128-bit packed integers. There
are 144 instructions in the SSE2 that can operate on two packed double-precision floating-point data elements, or on
16 packed byte, 8 packed word, 4 doubleword, and 2 quadword integers.
The full set of IA-32 SIMD technologies (the Intel MMX technology, the SSE extensions, and the SSE2 extensions)
gives the programmer the ability to develop algorithms that can combine operations on packed 64- and 128-bit
integer and single and double-precision floating-point operands.
This SIMD capability improves the performance of 3D graphics, speech recognition, image processing, scientific,
and other multimedia applications that have the following characteristics:
§inherently parallel
§regular and recurring memory access patterns
§localized recurring operations performed on the data
§data-independent control flow.
The IA-32 SIMD floating-point instructions fully support the IEEE* Standard 754 for Binary Floating-Point
Arithmetic. All SIMD instructions are accessible from all IA-32 execution modes: protected mode, real address
mode, and Virtual 8086 mode.
The SSE2 and SSE extensions, and the Intel MMX technology are architectural extensions in the IA-32 Intel®
architecture. All existing software continues to run correctly, without modification, on IA-32 microprocessors that
incorporate these technologies. Existing software also runs correctly in the presence of new applications that
incorporate these SIMD technologies.
The SSE and SSE2 instruction sets also introduced a set of cacheability and memory ordering instructions that can
improve cache usage and application performance.
For more information on SSE2 instructions, including the cacheability and memory operation instructions, refer to
the IA-32 Intel®Architecture Software Developer’s Manual, Volume 1, Chapter 11 and Volume 2, Chapter 3, which
are available at:http://developer.intel.com/design/pentium4/manuals/.
Summary of SIMD Technologies
The paragraphs below summarize the new features of the three SIMD technologies (MMX technology, SSE, and
SSE2) that have been added to the IA-32 architecture in chronological order.
MMX Technology
§Introduces 64-bit MMX registers.
§Introduces support for SIMD operations on packed byte, word, and doubleword integers.
The MMX instructions are useful for multimedia and communications software.
For more information on the MMX technology, refer to the IA-32 Intel®Architecture Software Developer’s Manual,
Volume 1, available at http://developer.intel.com/design/pentium4/manuals/.
Streaming SIMD Extensions
§Introduces 128-bit XMM registers.
§Introduces 128-bit data type with four packed single-precision floating-point operands.
§Introduces data prefetch instructions.
§Introduces non-temporal store instructions and other cacheability and memory ordering instructions.
§Adds extra 64-bit SIMD integer support.

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The SSE instructions are useful for 3D geometry, 3D rendering, speech recognition, video encoding and decoding.
For more information on the Streaming SIMD Extensions, refer to the IA-32 Intel®Architecture Software
Developer’s Manual, Volume 1, available at http://developer.intel.com/design/pentium4/manuals/.
Streaming SIMD Extensions 2
§Adds 128-bit data type with two packed double-precision floating-point operands.
§Adds 128-bit data types for SIMD integer operation on 16-byte, 8-word, 4-doubleword, or 2-quadword
integers.
§Adds support for SIMD arithmetic on 64-bit integer operands.
§Adds instructions for converting between new and existing data types.
§Extends support for data shuffling.
§Extends support for cacheability and memory ordering operations.
The SSE2 instructions are useful for 3D graphics, scientific computation, video decoding/encoding, and encryption.
For more information, refer to the IA-32 Intel®Architecture Software Developer’s Manual, Volume 1, available at
http://developer.intel.com.com/design/pentium4/manuals/.

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Intel®NetBurst™ Micro-architecture
The Pentium
®4 processor is the first hardware implementation of a new micro-architecture, the Intel NetBurst
micro-architecture. To help reader understand this new micro-architecture, this section examines in detail the
following:
§the design considerations the Intel NetBurst micro-architecture
§the building blocks that make up this new micro-architecture
§the operation of key functional units of this micro-architecture based on the implementation in the Pentium 4
processor.
The Intel NetBurst micro-architecture is designed to achieve high performance for both integer and floating-point
computations at very high clock rates. It has the following features:
§hyper pipelined technology to enable high clock rates and frequency headroom to well above 1GHz
§rapid execution engine to reduce the latency of basic integer instructions
§high-performance, quad-pumped bus interface to the 400 MHz Intel NetBurst micro-architecture system bus.
§execution trace cache to shorten branch delays
§cache line sizes of 64 and 128 bytes
§hardware prefetch
§aggressive branch prediction to minimize pipeline delays
§out-of-order speculative execution to enable parallelism
§superscalar issue to enable parallelism
§hardware register renaming to avoid register name space limitations
The Design Considerations of the Intel®NetBurstTM Micro-architecture
The design goals of Intel NetBurst micro-architecture are: (a) to execute both the legacy IA-32 code and applications
based on single-instruction, multiple-data (SIMD) technology at high processing rates; (b) to operate at high clock
rates, and to scale to higher performance and clock rates in the future. To accomplish these design goals, the Intel
NetBurst micro-architecture has many advanced features and improvements over the Pentium Pro processor micro-
architecture.
The major design considerations of the Intel NetBurst micro-architecture to enable high performance and highly
scalable clock rates are as follows:
§It uses a deeply pipelined design to enable high clock rates with different parts of the chip running at different
clock rates, some faster and some slower than the nominally-quoted clock frequency of the processor. The
Intel NetBurst micro-architecture allows the Pentium 4 processor to achieve significantly higher clock rates as
compared with the PentiumIIIprocessor. These clock rates will achieve well above 1 GHz.
§Its pipeline provides high performance by optimizing for the common case of frequently executed
instructions. This means that the most frequently executed instructions in common circumstances (such as a
cache hit) are decoded efficiently and executed with short latencies, such that frequently encountered code
sequences are processed with high throughput.
§It employs many techniques to hide stall penalties. Among these are parallel execution, buffering, and
speculation. Furthermore, the Intel NetBurst micro-architecture executes instructions dynamically and out-or-
order, so the time it takes to execute each individual instruction is not always deterministic. Performance of a
particular code sequence may vary depending on the state the machine was in when that code sequence was
entered.

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Overview of the Intel®NetBurstTM Micro-architecture Pipeline
The pipeline of the Intel NetBurst micro-architecture contain three sections:
§the in-order issue front end
§the out-of-order superscalar execution core
§the in-order retirement unit.
The front end supplies instructions in program order to
the out-of-order core. It fetches and decodes IA-32
instructions. The decoded IA-32 instructions are
translated into micro-operations (µops). The front end’s
primary job is to feed a continuous stream of µops to
the execution core in original program order.
The core can then issue multiple µops per cycle, and
aggressively reorder µops so that those µops, whose
inputs are ready and have execution resources available,
can execute as soon as possible. The retirement section
ensures that the results of execution of the µops are
processed according to original program order and that
the proper architectural states are updated.
Figure 3 illustrates a block diagram view of the major
functional blocks associated with the Intel NetBurst
micro-architecture pipeline. The paragraphs that follow
Figure 3 provide an overview of each of the three
sections in the pipeline.
The Front End
The front end of the Intel NetBurst micro-architecture consists of two parts:
§fetch/decode unit
§execution trace cache.
The front end performs several basic functions:
§prefetches IA-32 instructions that are likely to be executed
§fetches instructions that have not already been prefetched
§decodes instructions into µops
§generates microcode for complex instructions and special-purpose code
§delivers decoded instructions from the execution trace cache
§predicts branches using highly advanced algorithm.
The front end of the Intel NetBurst micro-architecture is designed to address some of the common problems in high-
speed, pipelined microprocessors. Two of these problems contribute to major sources of delays:
§the time to decode instructions fetched from the target
§wasted decode bandwidth due to branches or branch target in the middle of cache lines.
The execution trace cache addresses both of these problems by storing decoded IA-32 instructions. Instructions are
fetched and decoded by a translation engine. The translation engine builds the decoded instruction into sequences of
Fetch/Decode Trace Cache
Microcode ROM
Execution
Out-Of-Order Core
Retirement
1st Level Cache
4-way
2nd Level Cache
8-Way
BTBs/Branch Prediction
Bus Unit
System Bus
Frequently used paths
Less frequently used paths
Front End
3rd Level Cache
Optional, Server Product Only
Branch History Update
Figure 3 The Intel
®
NetBurstTM Micro-architecture