Intel SL3VS - Celeron 633 MHz Processor User manual

Intel®Celeron®Processor
Specification Update
Release Date: August 2007
Document Number: 243748-051
The Intel®Celeron®processor may contain design defects or errors known as errata, which may cause the
product to deviate from published specifications. Current characterized errata are documented in this
Specification Update.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL®PRODUCTS. NO LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED
BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH
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RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT,
COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.”
Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising
from future changes to them.
The Mobile Intel® Celeron® Processor may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product
order.
Intel, Pentium, Celeron, Intel Xeon and the Intel logo are trademarks or registered trademarks or registered trademarks of
Intel Corporation or its subsidiaries in the United States and other countries*Other names and brands may be claimed as the
property of others.
Copyright © 2007, Intel Corporation. All rights reserved.

i
CONTENTS
REVISION HISTORY....................................................................................................................................... ii
PREFACE ....................................................................................................................................................... vi
Specification Update for the Intel®Celeron®Processor................................................................................... 1
GENERAL INFORMATION.............................................................................................................................. 1
Intel®Celeron®Processor and Boxed Intel®Celeron®Processor Markings (S.E.P. Package).................... 1
Intel®Celeron®Processor and Boxed Intel®Celeron®Processor Markings (PPGA Package).................... 2
Intel®Celeron®Processor and Boxed Intel®Celeron®Processor Markings (FC-PGA/FC-PGA2 Package) 3
IDENTIFICATION INFORMATION .................................................................................................................. 4
SUMMARY OF CHANGES............................................................................................................................ 11
Summary of Errata ..................................................................................................................................... 12
Summary of Documentation Changes ....................................................................................................... 21
Summary of Specification Clarifications..................................................................................................... 23
Summary of Specification Changes ........................................................................................................... 24
ERRATA ........................................................................................................................................................ 25
DOCUMENTATION CHANGES .................................................................................................................... 79
SPECIFICATION CHANGES......................................................................................................................... 99

INTEL®CELERON®PROCESSOR SPECIFICATION UPDATE
ii
REVISION HISTORY
Date of Revision Version Description
April 1998 -001 This document is the first Specification Update for the Intel®
Celeroncprocessor.
May 1998 -002 Added Errata 24 through 28.
June 1998 -003 Updated S-spec Table. Updated Summary Table of Changes.
Updated Erratum 2 and 26. Added Errata 29 and 30. Added
Documentation Changes 7 through 12. Added Specification
Clarification 6 and 7.
July 1998 -004 Updated S-spec Table. Added Documentation Changes 13 through
16. Added Specification Clarifications 7 through 12. Added
Specification Change 1.
August 1998 -005 Updated Summary Table of Changes. Changed numbering in order
to maintain consistency with other product Specification Updates.
Updated Errata 6 and 38. Added Errata 56 through 59. Updated
Specification Clarification 5.
September 1998 -006 Updated S-spec table. Updated Erratum 56. Added Errata 60
through 62.
October 1998 -007 Implemented new numbering nomenclature. Updated Errata C1 and
C27. Added Errata C37 through C39. Added Specification
Clarification C15. Added Specification Change C2.
November 1998 -008 Updated Erratum C23. Added Erratum C40. Updated Documentation
Change C10. Added Documentation Changes C17 and C18. Added
Specification Change C3.
December 1998 -009 Added the Celeron processor (PPGA) markings. Added the Mb0
stepping to the Processor Identification Information table and the
Table of Changes. Added Errata C41 and C42.
December 1998 -010 Updated Identification Information table
January 1999 -011 Added Erratum C3AP. Added Documentation Changes C19 and
C20. Updated Processor Identification Information table.
February 1999 -012 Updated Processor Identification Information table.
March 1999 -013 Updated Processor Markings, Summary Table of Changes,
Documentation Changes, Specification Clarifications, and
Specification Changes sections. Added Specification Change C1.
May 1999 -014 Updated the Processor Identification Information table. Added
Erratum C43.
June 1999 -015 Added Erratum C44. Added Documentation Change C1. Added
Specification Clarifications C2 and C3. Added Specification Change
C1.
July 1999 -016 Added Erratum C45.

INTEL®CELERON®PROCESSOR SPECIFICATION UPDATE
iii
REVISION HISTORY
Date of Revision Version Description
August 1999 -017 Added Documentation Change C2. Updated Preface paragraph.
Updated Codes Used in Summary Table. Updated column heading
in Errata, Documentation Changes, Specification Clarifications and
Specification Changes tables.
October 1999 -018 Added ‘Brand Id’ to Identification Information table. Updated
Processor Identification Information Table. Added Errata C46.
November 1999 -019 Added Errata C47 and C48. Added Documentation Change C3.
December 1999 -020 Added Errata C49. Added Documentation Change C4. Added
Specification Clarification C4.
January 2000 -021 Added Errata C50 and C51. Added Documentation Change C5.
February 2000 -022 Added Documentation Change C6. Updated Summary of Changes
product letter codes.
March 2000 -023 Updated Erratum C47. Updated the CPUID/Stepping information in
the Summary of Changes section.
May 2000 -024 Updated the Intel®Celeron®Processor Identification Information
table. Added Errata C52 – C69. Updated the Summary of Errata,
Summary of Documentation Changes, Summary of Specification
Clarifications and Summary of Changes tables. Added Specification
Change C2.
June 2000 -025 Added Specification Change C3.
July 2000 -026 Added Errata C70 and C71.
August 2000 -027 Updated Processor Identification Information table. Added Erratum
C72.
September 2000 -028 Updated the Intel
®
Celeron®Processor Identification Information
table. Added Erratum C73. Updated Errata C33 ,C47 and C51.
Added Documentation changes C7 and C8.
October 2000 -029 Added Erratum C74. Added Documentation Changes C9 and C10
November 2000 -030 Updated the Intel®Celeron®Processor Identification Information
table Added Errata C75 and C76.
December 2000 -031 Updated Specification Update product key to include the Intel®
Pentium® 4 processor, Updated Erratum C2. Added Documentation
changes C11, C12, C13, C14, C15 and C16.
January 2001 -032 Updated the Intel®Celeron®Processor Identification Information
table, Updated Erratum C2. Added Documentation changes C17 and
C18.
February 2001 -033 Updated Documentation change C17. Added Documentation change
C19.
March 2001 -034 Updated Summary of Errata, Summary of Documentation Changes,
Summary of Specification Clarifications and Summary of
Specification Changes tables. Added Errata C77 and C78.

INTEL®CELERON®PROCESSOR SPECIFICATION UPDATE
iv
REVISION HISTORY
Date of Revision Version Description
July 2001 -035 Updated the Intel®Celeron®Processor Identification Information
table. Updated the Summary of Errata table.
August 2001 -036 Added Errata C79 and C80. Updated the Summary of changes
section.
August 2001 -037 Out of cycle release. Updated the Intel®Celeron®Processor
Identification Information table
October 2001 -038 Updated the identification information section with 0.13 micron
Celeron processor details. Updated Processor Identification
Information Table. Updated Summary of Errata Table. Updated
Summary of Documentation Changes Table. Updated Summary of
Specification Clarifications Table. Updated Summary of
Specifications Changes Table. Added Errata C81 and C82.
December 2001 -039 Added Documentation Changes C1, C2, C3, C4 and C5. Updated
Processor Identification Information Table.
January 2002 -040 Updated Processor Identification Information Table.
January 2002 -041 Added the 1A and 1.10A GHz specifications.
February 2002 -042 Added the 566 MHz at 1.75 VID specifications.
March 2002 -043 Updated Erratum C79. Added Erratum C83. Added Doc change C1.
Updated Processor Identification Information table.
April 2002 -044 Added Documentation change C1
May 2002 -045 Updated Erratum C67. Added Doc changes C1-C3. Updated
Processor Identification Information Table.
July 2002 -046 Added Erratum C84. Added Documentation Changes C1 - C12.
Added/updated CPUID 0x6B4 processor.
September 2002 -047 Updated Processor Identification Information Table. Updated
Summary of Errata Table. Added Documentation Changes C3 – C24.
December 2006 -048 Added Erratum C85, C86, C87, C88, C89, C90, C91, C92, C93, C94,
C95, C96, C97 C98, C99, C100, C101, C102, C103, C104, C105,
C106, C107, C108, C109. Update Summary Table of Changes.
Updated the names and document numbers of the Software
Developers Manual. Updated Processor Identification Table.
January 2007 -049 Added Erratum C110.
May 2007 -050 Updated Summary Table of Changes.

INTEL®CELERON®PROCESSOR SPECIFICATION UPDATE
v
REVISION HISTORY
Date of Revision Version Description
August 2007 -051 Updated Summary Table of Changes. Added Erratum C111.

INTEL®CELERON®PROCESSOR SPECIFICATION UPDATE
vi
PREFACE
This document is an update to the specifications contained in the following documents:
•Pentium®II Processor Developer’s Manual (Order Number 243502)
•P6 Family of Processors Hardware Developer’s Manual (Order Number 244001)
•Intel®Celeron® Processor Datasheet (Document Number 243658)
•Intel® 64 and Intel IA-32 Architectures Software Developer’s Manual, Volumes 1, 2-A, 2-B, 3-A and 3-B
(Document numbers 253665, 253666, 253667, 253668, and 253669, respectively.)
It is intended for hardware system manufacturers and software developers of applications, operating systems,
or tools. It contains S-Specs, Errata, Documentation Changes, Specification Clarifications and, Specification
Changes.
Nomenclature
S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique
characteristics, e.g., core speed, L2 cache size, package type, etc. as described in the processor identification
information table. Care should be taken to read all notes associated with each S-Spec number.
Errata are design defects or errors. Errata may cause the Celeron processor’s behavior to deviate from
published specifications. Hardware and software designed to be used with any given processor must assume
that all errata documented for that processor are present on all devices unless otherwise noted.
Documentation Changes include typos, errors, or omissions from the current published specifications. These
changes will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further highlight a specification’s
impact to a complex design situation. These clarifications will be incorporated in the next release of the
specifications.
Specification Changes are modifications to the current published specifications for the Celeron processor.
These changes will be incorporated in the next release of the specifications.

Specification Update for the Intel®Celeron®Processor
GENERAL INFORMATION
Intel®Celeron®Processor and Boxed Intel®Celeron®Processor
Markings (S.E.P. Package)
®
im©’98
celeron ™
Static White Silkscreen marks
266/66 COA
FFFFFFFF SYYYY
Dynamic laser mark area
NOTES:
•SYYYY = S-spec Number.
•FFFFFFFF = FPO # (Test Lot Traceability #).
COA = Country of Assembly.

INTEL®CELERON® PROCESSOR SPECIFICATION UPDATE
2
Intel®Celeron®Processor and Boxed Intel®Celeron®Processor
Markings (PPGA Package)
celeron
TM
AAAAAAAZZZ
LLL SYYYY
Country of Origin
FFFFFFFF-XXXX
M C ’98
i
Top Bottom
e
int l
®
NOTES:
AAAAAAA = Product Code
ZZZ = Processor Speed (MHz)
LLL = Integrated Level-Two Cache Size (in Kilobytes)
SYYYY = S-Spec Number
FFFFFFFF-XXXX = Assembly Lot Tracking Number
•
2-D Matrix Mark
Intel UCC#
Order Code (Product - speed)
S Number
Lot Number (date, factory)

INTEL®CELERON® PROCESSOR SPECIFICATION UPDATE
3
Intel®Celeron®Processor and Boxed Intel®Celeron®Processor
Markings (FC-PGA/FC-PGA2 Package)
FC-PGA 370 Pin Package
GRP1LN1: INTEL (m)(c) '01_-_{COO}
GRP1LN2: {Core Freq}/{Cache}/{Bus Freq}/{Voltage}
GRP2LN1: {FPO}-{S/N}
GRP2LN2: CELERON {S-Spec}
FC-PGA2 370 Pin Package
GRP2LN1
GRP2LN2
GRP1LN1
GRP1LN2 GRP1LN1: INTEL (m)(c) '01_-_{Country of Origin}
GRP1LN2: {Core freq}/{Cache}/{Bus Freq}/{Voltage}
GRP2LN1: {FPO}-{S/N}
GRP2LN2: CELERON {S-Spec}

INTEL®CELERON® PROCESSOR SPECIFICATION UPDATE
4
IDENTIFICATION INFORMATION
Complete identification information of the Celeron processor can be found in the Intel Processor Identification
and the CPUID Instruction application note (Document Number 241618).
The Celeron processor can be identified by the following values:
Family1Model2Brand ID3
0110 0101 00h = Not Supported
0110 0110 00h = Not Supported
0110 1000 01h = “Intel®Celeron®Processor”
0110 1011403h = “Intel®Celeron®Processor”
NOTES:
1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID
instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible
through Boundary Scan.
2. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after the CPUID
instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through
Boundary Scan.
3. The Brand ID corresponds to bits [7:0] of the EBX register after the CPUID instruction is executed with a 1 in the EAX
register.
4. This only applies to units with processor signature of 0x6B1.
The Celeron processor’s second level (L2) cache size can be determined by the following register contents:
0-Kbyte Unified L2 Cache140h
128-Kbyte Unified L2 Cache141h
256-Kbyte 8 way set associative 32byte line
size, L2 Cache182h
NOTE:
1. When the EAX register contains a value of 2, the CPUID instruction loads the EAX, EBX, ECX and EDX registers with
descriptors that indicate the processors cache and TLB characteristics. The lower 8 bits of the EAX register (AL) contain
a value that identifies the number of times the CPUID has to be executed to obtain a complete image of the processor’s
caching systems. The remainder of the EAX register, the EBX, ECX and EDX registers contain the cache and TLB
descriptors. When bit 31 in a given register is zero, that register contains valid 8-bit descriptors. To decode descriptors,
move sequentially from the most significant byte of the register down through the least significant byte of the register.
Assuming bit 31 is 0, then that register contains valid cache or TLB descriptors in bits 24 through 31, bits 16 through 23,
bits 8 through 15 and bits 0 through 7. Software must compare the value contained in each of the descriptor bit fields
according to the definition of the CPUID instruction . For more details refer to the AP-485 Intel Processor Identification
and the CPUID Instruction Application Note.

INTEL®CELERON® PROCESSOR SPECIFICATION UPDATE
5
Intel®Celeron®Processor Identification Information
S-Spec Core Stepping
L2 Cache
Size
(Kbytes) CPUID Speed (MHz)
Core/Bus
Package
and
Revision Notes
SL2SY A0 0 0650h 266/66 SEPP Rev. 1
SL2YN A0 0 0650h 266/66 SEPP Rev. 1 1
SL2YP A0 0 0650h 300/66 SEPP Rev. 1
SL2Z7 A0 0 0650h 300/66 SEPP Rev. 1 1
SL2TR A1 0 0651h 266/66 SEPP Rev. 1
SL2QG A1 0 0651h 266/66 SEPP Rev. 1 1
SL2X8 A1 0 0651h 300/66 SEPP Rev. 1
SL2Y2 A1 0 0651h 300/66 SEPP Rev. 1 1
SL2Y3 B0 0 0652h 266/66
SEPP Rev. 1 1
SL2Y4 B0 0 0652h 300/66
SEPP Rev. 1 1
SL2WM A0 128 0660h 300A/66
SEPP Rev. 1 3
SL32A A0 128 0660h 300A/66
SEPP Rev. 1 1
SL2WN A0 128 0660h 333/66
SEPP Rev. 1 3
SL32B A0 128 0660h 333/66
SEPP Rev. 1 1
SL376 A0 128 0660h 366/66 SEPP Rev. 1
SL37Q A0 128 0660h 366/66 SEPP Rev. 1 1
SL39Z A0 128 0660h 400/66 SEPP Rev. 1
SL37V A0 128 0660h 400/66 SEPP Rev. 1 1
SL3BC A0 128 0660h 433/66 SEPP Rev. 1
SL39Z A0 128 0660h 400/66
PPGA
SL37V A0 128 0660h 400/66
PPGA
SL3BC A0 128 0660h 433/66
PPGA
SL35Q B0 128 0665h 300A/66
PPGA
SL35Q B0 128 0665h 300A/66 PPGA 2
SL36A B0 128 0665h 300A/66
PPGA 18
SL35R B0 128 0665h 333/66 PPGA 2
SL36B B0 128 0665h 333/66 PPGA
SL36C B0 128 0665h 366/66 PPGA
SL35S B0 128 0665h 366/66 PPGA 2

INTEL®CELERON® PROCESSOR SPECIFICATION UPDATE
6
Intel®Celeron®Processor Identification Information
S-Spec Core Stepping
L2 Cache
Size
(Kbytes) CPUID Speed (MHz)
Core/Bus
Package
and
Revision Notes
SL3A2 B0 128 0665h 400/66 PPGA
SL37X B0 128 0665h 400/66 PPGA 2
SL3BA B0 128 0665h 433/66 PPGA
SL3BS B0 128 0665h 433/66 PPGA 2
SL3EH B0 128 0665h 466/66 PPGA
SL3FL B0 128 0665h 466/66 PPGA 2
SL3FY B0 128 0665h 500/66 PPGA
SL3LQ B0 128 0665h 500/66 PPGA 2
SL3FZ B0 128 0665h 533/66 PPGA
SL3PZ B0 128 0665h 533/66 PPGA 2
SL46S B0 128 0683h 533A/66 FC-PGA
SL3W6 B0 128 0683h 533A/66 FC-PGA 2
SL46T B0 128 0683h 566/66 FC-PGA
SL3W7 B0 128 0683h 566/66 FC-PGA 2
SL4PC C0 128 0686h 566/66 FC-PGA 2, 7, 5
SL4NW C0 128 0686h 566/66 FC-PGA 2, 7, 5
SL5L5 D0 128 068Ah 566/66 FC-PGA 7, 8
SL46U B0 128 0683h 600/66 FC-PGA
SL3W8 B0 128 0683h 600/66 FC-PGA 2
SL4PB C0 128 0686h 600/66 FC-PGA 2, 7, 5
SL4NX C0 128 0686h 600/66 FC-PGA 2, 7, 5
SL3VS B0 128 0683h 633/66 FC-PGA
SL3W9 B0 128 0683h 633/66 FC-PGA 2
SL4PA C0 128 0686h 633/66 FC-PGA 2, 6, 5
SL4NY C0 128 0686h 633/66 FC-PGA 2, 6, 5
SL48E B0 128 0683h 667/66 FC-PGA
SL4AB B0 128 0683h 667/66 FC-PGA 2
SL4P9 C0 128 0686h 667/66 FC-PGA 2, 6, 5
SL4NZ C0 128 0686h 667/66 FC-PGA 2, 6, 5

INTEL®CELERON® PROCESSOR SPECIFICATION UPDATE
7
Intel®Celeron®Processor Identification Information
S-Spec Core Stepping
L2 Cache
Size
(Kbytes) CPUID Speed (MHz)
Core/Bus
Package
and
Revision Notes
SL48F B0 128 0683h 700/66 FC-PGA
SL4EG B0 128 0683h 700/66 FC-PGA 2
SL4P8 C0 128 0686h 700/66 FC-PGA 2, 4, 5
SL4P2 C0 128 0686h 700/66 FC-PGA 2, 4, 5
SL4P7 C0 128 0686h 733/66 FC-PGA 4, 5
SL4P3 C0 128 0686h 733/66 FC-PGA 2, 4, 5
SL52Y D0 128 068Ah 733/66 FC-PGA 4, 8
SL5E9 D0 128 068Ah 733/66 FC-PGA 2, 4, 8
SL4P6 C0 128 0686h 766/66 FC-PGA 4, 5
SL4QF C0 128 0686h 766/66 FC-PGA 2, 4, 5
SL52X D0 128 068Ah 766/66 FC-PGA 4, 8
SL5EA D0 128 068Ah 766/66 FC-PGA 2, 4, 8
SL4TF C0 128 0686h 800/100 FC-PGA 4, 5
SL45R C0 128 0686h 800/100 FC-PGA 2, 4, 5
SL54P D0 128 068Ah 800/100 FC-PGA 4, 8
SL5WC D0 128 068Ah 800/100 FC-PGA 4, 8
SL5EB D0 128 068Ah 800/100 FC-PGA 2, 4, 8
SL5WW D0 128 068Ah 800/100 FC-PGA 2, 4, 8
SL5GA C0 128 0686h 850/100 FC-PGA 4, 5
SL5GB C0 128 0686h 850/100 FC-PGA 2, 4, 5
SL54Q D0 128 068Ah 850/100 FC-PGA 4, 8
SL5EC D0 128 068Ah 850/100 FC-PGA 2, 4, 8
SL5LX D0 128 068Ah 900/100 FC-PGA 8, 9
SL5WA D0 128 068Ah 900/100 FC-PGA 8, 9
SL5MQ D0 128 068Ah 900/100 FC-PGA 2, 8, 9
SL5WY D0 128 068Ah 900/100 FC-PGA 2, 8, 9
SL633 D0 128 068Ah 900/100 FC-PGA2
2,8,14
SL5UZ D0 128 068Ah 950/100 FC-PGA
8, 10
SL5V2 D0 128 068Ah 950/100 FC-PGA 2, 8, 10

INTEL®CELERON® PROCESSOR SPECIFICATION UPDATE
8
Intel®Celeron®Processor Identification Information
S-Spec Core Stepping
L2 Cache
Size
(Kbytes) CPUID Speed (MHz)
Core/Bus
Package
and
Revision Notes
SL634 D0 128 068Ah 950/100 FC-PGA2
2,8,14

INTEL®CELERON® PROCESSOR SPECIFICATION UPDATE
9
Intel®Celeron®Processor Identification Information
S-Spec Core Stepping
L2 Cache
Size
(Kbytes) CPUID Speed (MHz)
Core/Bus
Package
and
Revision Notes
SL5XT D0 128 068Ah 1 GHz/100 FC-PGA
8,11
SL5XQ D0 128 068Ah 1 GHz/100 FC-PGA 2, 8,11
SL5XU D0 128 068Ah 1.10
GHz/100
FC-PGA 8, 9
SL5XR D0 128 068Ah 1.10
GHz/100
FC-PGA 2, 8,9
SL5VQ A1 256 06B1h 1.10A
GHz/100
FC-PGA2 2,12,13
SL5ZE A1 256 06B1h 1.10A
GHz/100
FC-PGA2 2,12,13
SL6CA B1 256 06B4h 1.10A
GHz/100
FC-PGA2 13, 15
SL6JR B1 256 06B4h 1.10A
GHz/100
FC-PGA2 2,13, 15
SL5XS A1 256 06B1h 1.20
GHz/100
FC-PGA2 12,13
SL5Y5 A1 256 06B1h 1.20
GHz/100
FC-PGA2 2,12,13
SL656 A1 256 06B1h 1.20
GHz/100
FC-PGA2 15,17
SL68P A1 256 06B1h 1.20
GHz/100
FC-PGA2 2, 15, 17
SL6C8 B1 256 06B4h 1.20
GHz/100
FC-PGA2 15, 17
SL6JS B1 256 06B4h 1.20
GHz/100
FC-PGA2 2,15, 17
SL5VR A1 256 06B1h 1.30
GHz/100
FC-PGA2 15,16
SL5ZJ A1 256 06B1h 1.30
GHz/100
FC-PGA2 2,15,16
SL6C7 B1 256 06B4h 1.30
GHz/100
FC-PGA2 15, 16
SL6JT B1 256 06B4h 1.30
GHz/100
FC-PGA2 2,15, 16
SL64V A1 256 06B1h 1.40
GHz/100
FC-PGA2 14,15
SL68G A1 256 06B1h 1.40
GHz/100
FC-PGA2 2,14,15

INTEL®CELERON® PROCESSOR SPECIFICATION UPDATE
10
Intel®Celeron®Processor Identification Information
S-Spec Core Stepping
L2 Cache
Size
(Kbytes) CPUID Speed (MHz)
Core/Bus
Package
and
Revision Notes
SL6C6 B1 256 06B4h 1.40
GHz/100
FC-PGA2 14, 15
SL6JU B1 256 06B4h 1.40
GHz/100
FC-PGA2 2,14, 15
SL6C5 B1 256 06B4h 1.50
GHz/100
FC-PGA2 1,3, 19
SL6JV B1 256 06B4h 1.50
GHz/100
FC-PGA2 1,3, 19
NOTES:
1. This is a boxed Celeron processor with an attached fan heatsink.
2. This is a boxed Celeron processor with an unattached fan heatsink.
3. This part also ships as a boxed Celeron processor with an attached fan heatsink.
4. This part requires Tj of 80°C.
5. This part uses a VCCCORE of 1.7 V.
6. This part will require Tj of 82C.
7. This part will require Tj of 90C.
8. This part uses a VCCCORE of 1.75 V.
9. This part has max Tj of 77°C.
10. This part has max Tj of 79°C.
11. This part has max Tj of 75°C.
12. This part uses a VCCCORE of 1.475 V.
13. This part has max Tcase of 69 Deg C
14. This part has max Tcase of 72 Deg C
15. This part uses a VCCCORE of 1.5 V.
16. This part has max Tcase of 71 Deg C
17. This part has max Tcase of 70 Deg C
18. This part has min Tcase of 5 deg C, max Tcase of 85 deg C and TDP of 17.8 W,
19. This part uses a VCCCORE of 1.5V.

INTEL®CELERON® PROCESSOR SPECIFICATION UPDATE
11
SUMMARY OF CHANGES
The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that
apply to Celeron processors. Intel intends to fix some of the errata in a future stepping of the component, and to account for
the other outstanding issues through documentation or specification changes as noted. This table uses the following
notations:
X:
Specification Change, Erratum, Specification Clarification, or Documentation
Change applies to the given processor stepping.
(No mark) or (blank box): This item is fixed in or does not apply to the given stepping.
Doc: Document change or update that will be implemented.
PlanFix: This erratum may be fixed in a future stepping of the product.
Fixed: This erratum has been previously fixed.
NoFix: There are no plans to fix this erratum.
Doc: Intel intends to update the appropriate documentation in a future revision.
AP: APIC related erratum.
PKG: This column refers to errata on the Intel®Celeron® processor substrate.
Shaded: This item is either new or modified from the previous version of the document.
Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below
details the letters that are used in Intel’s microprocessor Specification Updates:
A = Dual-Core Intel®Xeon®processor 7000 sequence
C = Intel®Celeron®processor
D = Dual-Core Intel®Xeon®Processor 2.80 GHz
E = Intel®Pentium®III processor
F = Intel®Pentium®processor Extreme Edition and Intel®Pentium®D processor
I = Dual-Core Intel®Xeon®Processor
J = 64-bit Intel®Xeon®processor MP with 1 MB L2 Cache
K = Mobile Intel®Pentium®III processor
L = Intel®Celeron®D processor
M = Mobile Intel®Celeron®processor
N = Intel®Pentium®4 processor
O = Intel®Xeon®processor MP
P = Intel®Xeon®processor
Q = Mobile Intel®Pentium®4 processor supporting Hyper-Threading Technology on 90 nm process
technology
R = Intel®Pentium®4 processor on 90 nm process
S = 64-bit Intel®Xeon®processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions)
T = Mobile Intel®Pentium®4 processor-M
U = 64-bit Intel®Xeon®processor MP with up to 8 MB L3 Cache
V = Mobile Intel®Celeron®processor on .13 Micron Process in Micro-FCPGA Package
W= Intel®Celeron®M processor
X = Intel®Pentium®M processor on 90 nm process with 2 MB L2 Cache
Y = Intel®Pentium®M processor
Z = Mobile Intel®Pentium®4 processor with 533 MHz system bus
AA = Intel®Pentium®D Processor 900 Sequence and Intel®Pentium®Processor Extreme Edition 955, 965
AB = Intel®Pentium®4 Processor 6x1 Sequence

INTEL®CELERON® PROCESSOR SPECIFICATION UPDATE
12
AC = Intel®Celeron® Processor in 478 Pin Package
AD = Intel®Celeron® D processor on 65 nm process
AE = Intel®Core™ Duo Processor and Intel®Core™ Solo processor on 65 nm process
AF = Dual-Core Intel®Xeon®processor LV
AG = Dual-Core Intel®Xeon®Processor 5100 Series
AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor
Technology
AI = Intel®Core™2 Extreme Processor X6800Δand Intel®Core™2 Duo Desktop Processor E6000Δand
E4000ΔSequence
AJ = Quad-Core Intel®Xeon®Processor 5300 Series
AK = Intel®Core™2 Extreme quad-core processor QX6700Δand Intel®Core™2 Quad processor Q6600Δ
AL = Dual-Core Intel®Xeon®Processor 7100 Series
AN = Intel®Pentium®Dual-Core Processor
AO = Quad-Core Intel®Xeon®processor 3200 series
AP = Dual-Core Intel®Xeon®Processor 3000 Series
AQ = Intel®Pentium®Dual-Core Desktop Processor E2000ΔSequence
AR = Intel® Celeron processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
Summary of Errata
NO. CPUID/Stepping Plans ERRATA
650h
A0 651h A1 660h A0 665h B0 683h B0 686h C0 68Ah D0 6B1h A1 6B4h B1
C1 X X X X X X X X X NoFix
FP Data Operand Pointer
may be incorrectly calculated
after FP access which wraps
64-Kbyte boundary in 16-bit
code
C2 X X X X X X X X X NoFix Differences exist in debug
exception reporting
C3 X X X X X X X X X NoFix Code fetch matching
disabled debug register may
cause debug exception
C4 X X X X X X X X X NoFix FP inexact-result exception
flag may not be set
C5 X X X X X X X X X NoFix BTM for SMI will contain
incorrect FROM EIP
C6 X X X X X X X X X NoFix I/O restart in SMM may fail
after simultaneous MCE
C7 X X X X X X X X X NoFix Branch traps do not function
if BTMs are also enabled
C8 X X X X X X X X X NoFix Machine check exception
handler may not always
execute successfully
C9 X X X X X X X X X NoFix LBER may be corrupted after
some events
C10 X X X X X X X X X NoFix BTMs may be corrupted
during simultaneous L1