Intel i960 Series Guide

Intel®i960®RM/RN I/O Processor
Design Guide
April 2002
Order Number: 273139-004
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Design Guide
Intel®i960®RM/RN I/O Processor
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The Intel®i960®RM/RN I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2002
*Other brands and names are the property of their respective owners.
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Design Guide 3
Intel®i960®RM/RN I/O Processor
Contents
1.0 Introduction...................................................................................................................................9
2.0 Intel®80960RM/RN Processor Ball Map......................................................................................9
2.1 Intel®80960RM/RN Processor PBGA Signal Ball Map.................................................10
3.0 Routing Guidelines .....................................................................................................................11
3.1 Trace Length Limits.......................................................................................................11
4.0 Intel®80960RM/RN Processor Memory Subsystem..................................................................12
4.1 ROM, SRAM, or Flash Guidelines.................................................................................12
4.1.1 Layout Guidelines..........................................................................................................13
4.1.2 Wait State Profiles.........................................................................................................13
4.2 SDRAM Guidelines........................................................................................................14
4.2.1 Layout Guidelines..........................................................................................................15
4.2.2 SDRAM Clocking and Clock Buffer Specifications........................................................20
4.2.3 SDRAM Power Failure Guidelines.................................................................................23
4.2.4 System Assumptions .....................................................................................................23
4.2.5 External Logic Required for Power Failure....................................................................23
5.0 Interrupt Routing.........................................................................................................................25
5.1 Intel®80960RM/RN Processor Implementation on a MotherBoard...............................25
5.2 Intel®80960RM/RN Processor Implementation on an Add-in Card..............................26
6.0 Clocking Guidelines....................................................................................................................27
6.1 Layout Guidelines for Add-in Cards...............................................................................27
6.2 Layout Guidelines for Motherboards..............................................................................28
6.3 Clock Vendors ...............................................................................................................29
7.0 Intel®80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors...............................30
8.0 Intel®80960RM/RN Processor Signals Requiring Pull-Up/Down Resistors...............................32
9.0 Intel®80960RM/RN Processor 5 V and 3.3 V Design Considerations.......................................34
9.1 Providing 3.3 V in a 5 V System....................................................................................34
9.2 Choosing a Power Source.............................................................................................36
9.3 PCI Adapter Card Power Source...................................................................................37
9.4 VCC5REF Pin Requirement (VDIFF).................................................................................37
9.5 VCCPLL Pins Requirement..............................................................................................38
9.6 Pullups and Pulldown Resistors ....................................................................................38
9.7 FAIL# .............................................................................................................................39
10.0 Processor Power Supply Decoupling .........................................................................................40
10.1 High Frequency Decoupling ..........................................................................................40
10.2 Bulk Decoupling Capacitance........................................................................................41
11.0 Intel®80960RM/RN Processor Based Reference Design..........................................................42
12.0 Debug Connector Recommendations.........................................................................................43
12.1 PBGA Sockets and Headers .........................................................................................43
12.2 Logic Analyzer Connectivity...........................................................................................45
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4Design Guide
Intel®i960®RM/RN I/O Processor
12.3 JTAG Connector and Test Interface..............................................................................48
12.3.1 Intel®i960®RM/RN I/O Processor JTAG Emulator.....................................................48
12.3.2 Intel®i960®RM/RN I/O Processor Target Debug Interface Connector.......................48
12.3.3 Connecting The Emulator To The Target......................................................................50
12.3.4 Other Tools....................................................................................................................51
13.0 Design for Manufacturability.......................................................................................................52
14.0 Thermal Solutions.......................................................................................................................53
14.1 Thermal Recommendations ..........................................................................................53
14.2 3-Dimensional View: Processor with Heat Sink Attached..............................................54
14.3 PCB Heatsink Hole Dimensions....................................................................................55
14.4 Clearances of PCI Board and Components ..................................................................57
14.5 Heat Sink Information....................................................................................................58
14.5.1 Socket Information.........................................................................................................58
14.5.2 Socket-Header Vendor..................................................................................................58
14.5.3 Burn-in Socket Vendor ..................................................................................................58
14.5.4 Shipping Tray Vendor....................................................................................................59
14.5.5 Logic Analyzer Interposer Vendor .................................................................................59
14.5.6 JTAG Emulator Vendor .................................................................................................59
15.0 References .................................................................................................................................60
15.1 Related Documents.......................................................................................................60
15.2 Electronic Information....................................................................................................60
AIntel
®i960®RM I/O Processor Schematics..............................................................................61
BIntel
®IQ80960RM Board Bill of Material....................................................................................72
CIntel
®i960®RN I/O Processor Schematics ..............................................................................76
DIntel
®IQ80960RN Board Bill of Material.....................................................................................88
EIntel
®IQ80960RM/RN SDRAM Battery Backup PLD Equations................................................92
FIntel
®80960RM/RN Processor PBGA Signal Ball Map..............................................................93
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Design Guide 5
Intel®i960®RM/RN I/O Processor
Figures
2-1 540L H-PBGA Diagram (Bottom View).......................................................................................10
3-2 Examples of Stubless and Short Stub Traces............................................................................11
4-3 4 Mbyte Flash Memory System..................................................................................................13
4-4 Dual-Bank SDRAM Memory Subsystem....................................................................................15
4-5 SDRAM DIMM Layout Topology #1............................................................................................17
4-6 SDRAM DIMM Layout Topology #2............................................................................................17
4-7 Address and Control Topology for Two Discrete SDRAM Devices ............................................18
4-8 Address and Control Topology for Four or More Discrete SDRAM Devices..............................18
4-9 Data and DQM Topology for Discrete SDRAM Devices.............................................................19
4-10 Clocking for a Dual-Bank SDRAM DIMM ...................................................................................20
4-11 Clock Routing for a Two Device SDRAM Subsystem.................................................................22
4-12 External Power Failure State Machine .......................................................................................23
4-13 External Power Failure Logic in the System...............................................................................24
5-14 Example Secondary PCI Connector Interrupt Routing...............................................................26
6-15 PCI Add-in Card Example Configuration....................................................................................27
6-16 Motherboard Example Configuration..........................................................................................28
9-17 Creating a Power “Island”...........................................................................................................35
9-18 Power Supply Circuit ..................................................................................................................36
9-19 Recommended Power Supply Connection Layout.....................................................................36
9-20 VCC5REF Current-Limiting Resistor.............................................................................................37
9-21 VCCPLL Low-Pass Filter ..............................................................................................................38
9-22 Recommended FAIL# Circuit......................................................................................................39
10-23 High-Frequency Capacitor Values and Layout...........................................................................41
12-24 540L PBGA Header....................................................................................................................43
12-25 540L PBGA Socket.....................................................................................................................44
12-26 Packard-Hughes Direct Mount (Flex Tape) Interposer - Top View.............................................46
12-27 Packard-Hughes Direct Mount (Flex Tape) Interposer - Side View............................................46
12-28 Flex Tape Interposer Application (Add-In Card).........................................................................47
12-29 Flex Tape Interposer (Top View)................................................................................................47
12-30 Flex Tape Interposer (Side View)...............................................................................................47
12-31 JTAG Emulator Connector (Top View).......................................................................................48
14-32 Conceptual 3-D View of Processor with a Heat Sink..................................................................54
14-33 Hole Dimensions for Passive Heatsink.......................................................................................55
14-34 Board Level Keep Out Areas......................................................................................................56
14-35 Clearances of PCI Board and Components................................................................................57
15-36 Decoupling and 3.3 V Power Schematic ....................................................................................62
15-37 Primary PCI Interface Schematic................................................................................................63
15-38 Memory Controller Schematic ....................................................................................................64
15-39 Flash ROM, UART and LEDs Schematic...................................................................................65
15-40 Logic Analyzer I/F Schematic.....................................................................................................66
15-41 SDRAM 168-Pin DIMM Schematic.............................................................................................67
15-42 Secondary PCI/80960 Core Schematic......................................................................................68
15-43 Secondary PCI Bus 1/2 Schematic.............................................................................................69
15-44 Secondary PCI Bus 3/4 Schematic.............................................................................................70
15-45 Battery Monitor Schematic..........................................................................................................71
15-46 Decoupling and 3.3 V Power Schematic ....................................................................................77
15-47 Primary PCI Interface Schematic................................................................................................78
15-48 Memory Controller Schematic ....................................................................................................79
15-49 Flash ROM, UART and LEDs Schematic...................................................................................80
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6Design Guide
Intel®i960®RM/RN I/O Processor
15-50 Logic Analyzer I/F Schematic.....................................................................................................81
15-51 SDRAM 168-Pin DIMM Schematic.............................................................................................82
15-52 Secondary PCI/80960 Core Schematic......................................................................................83
15-53 Secondary PCI Bus 1/2 Schematic ............................................................................................84
15-54 Secondary PCI Bus 3/4 Schematic ............................................................................................85
15-55 SPCI Pull-Ups Schematic...........................................................................................................86
15-56 Battery/Monitor Schematic .........................................................................................................87
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Design Guide 7
Intel®i960®RM/RN I/O Processor
Tables
4-1 Flash Interface Signals...............................................................................................................12
4-2 ROM, SRAM, or Flash Wait State Profile Programming.............................................................13
4-3 SDRAM Interface Signals...........................................................................................................14
4-4 Drive Strength Programmability Options ....................................................................................16
4-5 DCLKIN Routing and Loading Requirements.............................................................................21
4-6 SDRAM Clock Buffer Information ...............................................................................................22
5-7 Intel®80960RM/RN Processor Interrupt Routing Signals..........................................................25
6-8 Low Skew Clock Buffer Information............................................................................................29
7-9 Memory Controller, Core and JTAG Signals ..............................................................................30
7-10 I2C Bus Signals...........................................................................................................................30
7-11 PCI Signals.................................................................................................................................30
8-12 Memory Controller, Core and JTAG Signals ..............................................................................32
8-13 I2C Bus Signals...........................................................................................................................32
8-14 PCI Signals.................................................................................................................................32
9-15 VDIFF Specification for Dual-Power Supply Requirements (3.3 V, 5 V)......................................37
12-16 Logic Analyzer Header Definitions (Mictor) ................................................................................45
12-17 i960®RM/RN I/O Processor Debug Connector Wiring...............................................................49
12-18 i960®RM/RN I/O Processor with PC-1149.1/100F (cable P/N AS01090025-Ax)......................50
12-19 i960®RM/RN I/O Processor with PCMCIA-1149.1 (cable P/N AS01090025-Bx) ......................51
14-20 H-PBGA Package Characteristics..............................................................................................53
14-21 Heat Sink Vendors and Contacts................................................................................................58
14-22 Socket-Header Vendor...............................................................................................................58
14-23 Burn-in Socket Vendor................................................................................................................58
14-24 Shipping Tray Vendor.................................................................................................................59
14-25 Logic Analyzer Interposer Vendor ..............................................................................................59
14-26 JTAG Emulator Vendor...............................................................................................................59
15-27 Related Documentation..............................................................................................................60
15-28 Electronic Information.................................................................................................................60
B-1 Intel®IQ80960RM Bill of Materials.............................................................................................72
D-1 Intel®IQ80960RN Bill of Materials .............................................................................................88
F-1 540-Lead H-PBGA Pinout —Intel®i960®RM I/O Processor Processor..................................93
F-2 540-Lead H-PBGA Pinout —Intel®i960®RN I/O Processor Processor..................................98
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8Design Guide
Intel®i960®RM/RN I/O Processor
Revision History
Rev Date Description of Changes
004 04/2002 •Changed “Thermal Recommendations”section.
003 08/2000 •Added schematics.
002 06/2000
•Updated Trademarks and Branding.
•Updated vendor tables.
•Minor text rewrites.
•Updated Pinout tables.
1.0 06/1998
•Added reference schematics.
•Added debug connector recommendations section.
•Added more detailed heat-sink drawings.
•Updated heat-sink vendor table.
0.9 12/10/97 Original Document
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Design Guide 9
Intel®i960®RM/RN I/O Processor
Introduction
1.0 Introduction
This design guide addresses design considerations for designing with either the Intel® i960® RN
I/O processor or the Intel® i960® RM I/O processor. Where necessary and applicable, differences
in design constraints between the two processors is clarified.
The i960 RN I/O Processor is an Intel I/O processor supporting both 64-bit and 32-bit PCI
operation. The i960 RM I/O Processor is an Intel I/O processor only supporting 32-bit PCI
operation.
2.0 Intel®80960RM/RN Processor Ball Map
Intel®i960®RM/RN I/O processor signals, by design, are located on the PBGA package to
simplify signal routing and system implementation. Figure 2-1 shows the RM/RN I/O processor
major signal sections. To simplify routing and minimize the number of cross traces, keep this
layout in mind when placing components in your system. Individual signals within the respective
groups have also been laid out to minimize signal crossings.
For detailed signal descriptions refer to the Tuzigoot Processor Target Specification document.
Contact your Intel sales representative to obtain a copy of the document.
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Intel®i960®RM/RN I/O Processor
Intel®80960RM/RN Processor Ball Map
10 Design Guide
2.1 Intel®80960RM/RN Processor PBGA Signal Ball
Map
Table F-1 and Table F-2 detail the ballout for the 80960RM and 80960RN processor, respectively.
See Appendix F.
Figure 2-1. 540L H-PBGA Diagram (Bottom View)
T
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AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
AM
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1234567891011121314151617181920212223242526272829303132
T
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
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V
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1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132
Secondary PCI Bus Signals
Memory Controller and Miscellaneous Signals
Primary PCI Bus Signals
Memory Controller Signals
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Design Guide 11
Intel®i960®RM/RN I/O Processor
Routing Guidelines
3.0 Routing Guidelines
The order in which signals are routed first and last varies from designer to designer. Some prefer to
route all clock signals first, while others prefer to route all high speed bus signals first. Either order
can be used, provided the guidelines listed here are followed.
Route the RM/RN I/O processor address/data and control signals using a “daisy chain”topology.
This topology assumes that no stubs are used to connect any devices on the net. Figure 3-2 shows
two possible techniques to achieve a stubless trace. When it is not possible to apply one of these
two techniques due to congestion, a very short stub is allowed —preferably not to exceed
250 mils.
3.1 Trace Length Limits
For add-in cards, trace lengths from the top of the card edge connector to the RM/RN I/O processor
are as follows:
•The maximum trace length for all 32-bit interface signals should not exceed 1.5 inches for
32-bit and 64-bit cards. This includes all signals except those listed as ‘Signal Pins’, ‘Interrupt
Pins’, and ‘JTAG Pins’as per PCI Local Bus Specification, Revision 2.1.
•The trace length of the additional signals used in the 64-bit extension are limited to 2 inches on
all 64-bit cards.
•The trace length for the PCI CLK signal is 2.5 inches ± 0.1 inch for 32-bit and 64-bit cards and
should be routed to only a single load.
Figure 3-2. Examples of Stubless and Short Stub Traces
<250 mils
Stubless Short Stub
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Intel®i960®RM/RN I/O Processor
Intel®80960RM/RN Processor Memory Subsystem
12 Design Guide
4.0 Intel®80960RM/RN Processor Memory
Subsystem
The RM/RN I/O processor integrates a memory controller to provide a direct interface between the
RM/RN I/O processor and its local memory subsystem. The memory controller supports:
•Up to 16 Mbytes of 8-bit Flash, ROM, or SRAM
•Between 8 and 128 Mbytes of 64-bit synchronous DRAM (SDRAM)
•Between 4 and 64 Mbytes of 32-bit synchronous DRAM for low cost solutions
•Single-bit error correction, double-bit and nibble detection support (ECC)
The Flash interface provides an 8-bit data bus, 23-bit address bus, and control to support up to two
64 Mbit Bulk-Erase or Boot-Block Flash devices. The Flash devices provide storage for the
RM/RN I/O processor initialization code.
The memory controller provides a separate SDRAM interface from the Flash interface. The SDRAM
interface consists of a 66 MHz, 64-bit wide data path to support 528 Mbytes/sec throughput. An 8-bit
Error Correction Code (ECC) across each 64-bit word improves system reliability.
•The memory controller supports two banks of SDRAM in the form of a single two-bank dual
inline memory module (DIMM) or two single-bank DIMMs.
•The memory controller supports a 32-bit SDRAM data interface. This mode enables
lower-cost solutions at the cost of system bandwidth.
•The memory controller responds to internal bus memory accesses within its programmed
address range and issues the memory request to either the Flash or SDRAM interface.
The memory controller provides four chip enables to the memory subsystem. Two chip enables
service the SDRAM subsystem (one per bank) and two service the Flash devices.
Note: If the design does not follow the listed guidelines, then it is very important that the design be
simulated. Even if the guidelines are followed it is still recommended that the design be simulated
for proper signal integrity, flight time, and cross talk.
4.1 ROM, SRAM, or Flash Guidelines
The RM/RN I/O processor memory controller provides an interface to two banks of static memory
ranging from 64 Kbytes to 16 Mbytes. This memory may be SRAM, ROM, or Flash. Optionally,
one of the banks may be dedicated to a UART device. Table 4-1 defines all Flash interface signals.
Table 4-1. Flash Interface Signals
Pin Name Description
RCE[1:0]# Chip Enable - Asserted for all transactions to the Flash device.
RWE# Write Enable - Controls the Flash input data buffers.
ROE# Output Enable - Asserted for reads, deasserted for writes. Controls the Flash output data
buffers for write transactions.
RAD[16:0] Address/Data bus - Capable of supporting 16 Mbit of Flash (2Mx8). The data bus is
multiplexed on RAD[16:9].
RALE Address Latch Enable - Indicates the transfer of a physical address. RALE is asserted
during a Flash address cycle and deasserted before the beginning of the data cycle.
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Design Guide 13
Intel®i960®RM/RN I/O Processor
Intel®80960RM/RN Processor Memory Subsystem
4.1.1 Layout Guidelines
Figure 4-3 illustrates how two Flash devices would interface to the RM/RN I/O processor with the
memory controller. The Flash subsystem requires an external latch for address and data
demultiplexing on RAD[16:3]. The data is multiplexed on RAD[16:9].
Flash signal loading should not exceed 50 pF. If the system conforms to I2O specification, then a
minimum 16 Mbit Flash such as Intel’s 28F016SA is suggested.
All traces between the RM/RN I/O processor and Flash/SRAM should not exceed 8 inches.
4.1.2 Wait State Profiles
Table 4-2 summarizes various wait state profiles of SRAM and writable non-volatile memory devices.
Figure 4-3. 4 Mbyte Flash Memory System
Latch
Latch
RALE
RAD[16:0]
ROE#
RWE#
RCE0#
RCE1#
80960RM/RN
A[20:0]
OE#
WE#
DQ[7:0]
CE#
Intel 28F016-70
16 Mbit Flash
A[20:0]
OE#
WE#
DQ[7:0]
CE#
Intel 28F016-70
16 Mbit Flash
RAD[2:0] A[2:0]
A[8:3]
A[22:17]
A[16:9]
DQ[7:0]
RAD[8:3]
RAD[16:9]
Table 4-2. ROM, SRAM, or Flash Wait State Profile Programming
Device Speed Address-to-Data Wait States Recovery Wait States
≤55 ns 4 0
≤115 ns 8 4
≤175 ns 12 4
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Intel®i960®RM/RN I/O Processor
Intel®80960RM/RN Processor Memory Subsystem
14 Design Guide
4.2 SDRAM Guidelines
The RM/RN I/O processor memory controller supports up to two banks of 66 MHz, 72-bit
SDRAM. The memory controller supports 16 Mbit or 64 Mbit technology offering up to 128
Mbytes of ECC protected memory. For low-cost solutions, the memory controller provides a 32-bit
SDRAM interface offering up to 64 Mbytes of memory.
Table 4-3 shows the SDRAM interface signals.
Table 4-3. SDRAM Interface Signals
Pin Name Description
DCLKOUT SDRAM Clock Out - This is the clock to the off-chip SDRAM clock buffer driven by the
RM/RN I/O processor. Section 4.2.2 describes the SDRAM clocking strategy.
DCLKIN SDRAM Clock In - This is the clock returning from the off-chip SDRAM clock buffer.
Section 4.2.2 describes the SDRAM clocking strategy.
SCKE[1:0]
Clock enables - One clock after SCKE[1:0] is deasserted, the data is latched on DQ[63:0]
and SCB[7:0]. The burst counters within the SDRAM device are not incremented.
Deasserting this signal places the SDRAM in self-refresh mode. For normal operation,
SCKE[1:0] must be asserted.
SDQM[7:0] Data Mask - On a write, these signals disable the data on a byte-by-byte basis, thus preventing certain bytes from being written. On a read, two clocks after asserting
SDQM[7:0] the output data bytes from the SDRAM device are disabled.
SCE[1:0]# Chip Select - Must be asserted for all transactions to the SDRAM device. One per bank.
SWE# Write Enable - Controls the SDRAM data input buffers. Asserting SWE# causes the data on
DQ[63:0] and SCB[7:0] to be written into the SDRAM devices.
SBA[1:0] SDRAM Bank Selects - Controls which of the internal SDRAM banks to read or write. For
16 Mbit devices (2 banks), only SBA[0] is used while 64 Mbit devices use SBA[1:0].
SA[10] Address bit 10 - If high during a read or write command, then auto-precharge occurs after
the command. During a row-activate command, this bit is part of the address.
SA[11:0] Address bits 11 through 0 - Indicates the row or column to access depending on the state of
SRAS# and SCAS#.
SRAS# Row Address Strobe - Indicates that the current address on SA[11:0] is the row.
SCAS# Column Address Strobe - Indicates that the current address on SA[11:0] is the column.
DQ[63:0] Data Bus - 64-bit wide data bus.
SCB[7:0] ECC Bus - 8-bit error correction code which accompanies the data on DQ[63:0].
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Design Guide 15
Intel®i960®RM/RN I/O Processor
Intel®80960RM/RN Processor Memory Subsystem
4.2.1 Layout Guidelines
The SDRAM subsystem may be implemented with:
•up to two banks directly connected on the printed circuit board (32, 64, or 72 bits wide)
•up to two 168-pin DIMM sockets (64-bit data bus with or without ECC)
•up to two 144-pin SO-DIMM sockets (64-bit data bus without ECC)
The memory controller supports either one dual-bank DIMM or two single-bank DIMMs. The
4-Clock 66 MHz 72-bit ECC Unbuffered SDRAM DIMM Specification requires four clock inputs.
Figure 4-4 illustrates how two banks of 16 Mbits SDRAM would interface with the RM/RN I/O
processor memory controller. SBA[1] is only connected for 64 Mbit SDRAM devices. For the
clock routing, refer to Figure 4-10.
Figure 4-4. Dual-Bank SDRAM Memory Subsystem
DQ[63:0]
SCB[7:0]
SRAS#
SCAS#
SWE#
SA[10:0]
SBA[0]
SBA[1]
SDQM[7:0]
SCKE
SCE0#
SCE1#
80960RM/RN
DQ[63:0]
CB[7:0]
RAS#
CAS#
WE#
A[10:0]
BA0
DQM[7:0]
CKE[1:0]
CS[3:0]#
SDRAM DIMM
using 16 Mbit
devices
DQ[63:0]
CB[7:0]
RAS#
CAS#
WE#
A[10:0]
BA0
DQM[7:0]
CKE[1:0]
CS[3:0]#
SDRAM DIMM
using 16 Mbit
devices
*

Intel®i960®RM/RN I/O Processor
Intel®80960RM/RN Processor Memory Subsystem
16 Design Guide
The drive strengths for the SDRAM signals are independently programmable using the SDCR
register. Table 4-4 lists some example SDRAM configurations and how the SDCR should be
programmed. The RM/RN I/O processor determines the SDRAM configuration with the Serial
Presence Detect EEROM (SPD) located on the DIMM. The I2C bus interfaces the RM/RN I/O
processor with the SPD.
Specific SDRAM signal topologies have been validated for 66 MHz operation. Figure 4-5 through
Figure 4-9 illustrate the proven topologies and are recommended. Proper signal integrity analysis
should verify any other signal topologies.
To minimize crosstalk, SDRAM signal routing should use a minimum of 4 mils spacing and 4 mils
trace width. SDRAM clocks (out of the buffer) should use a minimum of 12 mils spacing and
6 mils trace width.
Table 4-4. Drive Strength Programmability Options
Bus
Width
Memory
Size1
(Mbytes)
Form
Factor Bank 0 Bank 1 SDCR[3]
(DQ) SDCR[4] (CKE0) SDCR[5] (CKE1) SDCR[6] (DQM) SDCR[7] (SA[11:0])
32 4
On-board
2x1M16
None
000
200
8 4x2M8 0 0 0200
64
84x1M16000
200
16 8X2M8 0 1 0201
81
Single-si
ded
DIMM
4x1M16 0 0 0200
16 8x2M8 0 1 0201
16 1
Double-si
ded
DIMM
4x1M16 4x1M16 1 0 0 1 1
32 8x2M8 8x2M8 1 1 1 1 1
16 2
Single-si
ded
DIMMs
4x1M16 4x1M16 1 0 0 1 1
32 4x1M16 8x2M8 1 0 1 1 1
24 8x2M8 4x1M16 1 1 0 1 1
32 8x2M8 8x2M8 1 1 1 1 1
72
16 On-board 9x2M8
None
010
201
16
1
Single-si
ded
DIMM
9x2M8 0 1 0201
32
1
Double-si
ded
DIMM
9x2M89x2M811111
32
2
Single-si
ded
DIMMs
9x2M89x2M811111
NOTES:
1. The Memory Size column is based on 16 Mbit SDRAM technology. If 64 Mbit SDRAM is populated, then the
size will increase appropriately. Each bank’s technology may be programmed independently.
2. If one SDRAM bank is unpopulated, then the corresponding SCKE and SCE is unconnected.
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Design Guide 17
Intel®i960®RM/RN I/O Processor
Intel®80960RM/RN Processor Memory Subsystem
Figure 4-5. SDRAM DIMM Layout Topology #1
Figure 4-6. SDRAM DIMM Layout Topology #2
DIMM DIMM
Intel®
80960RM/RN
I/O Processor
1 to 8 inches 0 to 0.6 inches
Trace Lengths apply for all SDRAM
signals except the clock
Address, Data and Control
1 to 8 inches
SCE[0], SCKE[0]
1 to 8 inches
SCE[1], SCKE[1]
DIMM0
Intel®
80960RM/RN
I/O Processor
Trace Lengths apply for all SDRAM
signals except the clock
DIMM1
Traces from the processor
to DIMM0 must be 1 to 8
inches
Traces from the
processor to DIMM1
must be 1 to 8 inches
*

Intel®i960®RM/RN I/O Processor
Intel®80960RM/RN Processor Memory Subsystem
18 Design Guide
Figure 4-7. Address and Control Topology for Two Discrete SDRAM Devices
Figure 4-8. Address and Control Topology for Four or More Discrete SDRAM Devices
SDRAM0
Intel®
80960RM/RN
I/O Processor
SDRAM1
Signals must be 3 to 9.5
inches from the processor and
each SDRAM device
Applicable to all signals except
DQ[63:0], SCB[7:0], and SDQM[7:0].
Address and Control
SDRAM0
Intel®
80960RM/RN
I/O Processor
SDRAM1
0 to 0.8 inches
SDRAM2
1to8inches
0 to 0.8 inches
0 to 0.5 inch
0 to 0.5 inch
0 to 0.5 inch
Applicable to all signals except
DQ[63:0], SCB[7:0], and SDQM[7:0].
*

Design Guide 19
Intel®i960®RM/RN I/O Processor
Intel®80960RM/RN Processor Memory Subsystem
The address and control signals for the SDRAM subsystem include SA[11:0], SCAS#, SCE[1:0]#,
SCKE[1:0], SRAS#, and SWE#. The SDRAM data signals include DQ[63:0], and SCB[7:0].
Figure 4-9. Data and DQM Topology for Discrete SDRAM Devices
SDRAM0
Intel®
80960RM/RN
I/O Processor
10 ohms +/- 5%
SDRAM1
SDQ[63:0], SCB[7:0]
Data signals must be 3 to 8
inches from the processor and
each SDRAM device
10 ohms +/- 5%
Resistors must be within 0.5
inches from the SDRAM device
SDQM[7:0]
SDQM signals must be 3 to
9.5 inches from the processor
and each SDRAM device
*

Intel®i960®RM/RN I/O Processor
Intel®80960RM/RN Processor Memory Subsystem
20 Design Guide
4.2.2 SDRAM Clocking and Clock Buffer Specifications
The MCU provides one clock (DCLKOUT) to the SDRAM memory subsystem with a 66 MHz
frequency. The 72-bit, 2-bank SDRAM DIMM specification requires four clocks to distribute the
loading across eighteen x8 SDRAM components. The board designer must buffer DCLKOUT
external to the RM/RN I/O processor with a Texas Instruments CDC318 or equivalent buffer. Refer
to Figure 4-10 for the clock routing diagram. External resistors and capacitors are required for
proper signal integrity and clock skew management.
Note: Any single SDRAM bank will use two clock buffer outputs. Four clock buffer outputs are used
only when two SDRAM banks are populated.
Figure 4-10. Clocking for a Dual-Bank SDRAM DIMM
Intel®
80960RM/RN
I/O Processor Clock
Buffer
SDRAM DIMM
DCLKOUT
Clock0
DCLKIN
35 ohms
+/- 5%
25 ohms
+/- 5%
X pF
30 ohms +/- 5%
Clock1
30 ohms +/- 5%
Clock2
30 ohms +/- 5%
Clock3
30 ohms +/- 5%
Traces from the
processor to the
resistor must be within
0.5 inches.
Traces from the clock buffer
to the resistors must be
within 0.5 inches.
Traces from the processor
to the capacitor must be
within 0.5 inches.
30 ohms +/- 5%
*