Intel BX80532PG3200D User manual

Document Number: 322875-001EN
Intel® Pentium® Processor on
45-nm Process
Datasheet
For Platforms Based on Mobile Intel® 4 Series Express Chipset Family
October 2009

2Datasheet
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Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check
with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
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Datasheet 3
Contents
1Introduction..............................................................................................................7
1.1 Terminology .......................................................................................................8
1.2 References .........................................................................................................9
2 Low Power Features ................................................................................................11
2.1 Clock Control and Low-Power States .................................................................... 11
2.1.1 Core Low-Power State Descriptions...........................................................13
2.1.2 Package Low-power State Descriptions......................................................14
2.2 Enhanced Intel SpeedStep® Technology ..............................................................17
2.3 Extended Low-Power States................................................................................ 18
2.4 FSB Low Power Enhancements............................................................................19
2.5 Processor Power Status Indicator (PSI-2) Signal....................................................19
3 Electrical Specifications...........................................................................................21
3.1 Power and Ground Pins ......................................................................................21
3.2 Decoupling Guidelines........................................................................................21
3.2.1 VCC Decoupling......................................................................................21
3.2.2 FSB AGTL+ Decoupling ...........................................................................21
3.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking........................................... 21
3.3 Voltage Identification and Power Sequencing ........................................................22
3.4 Catastrophic Thermal Protection..........................................................................25
3.5 Reserved and Unused Pins.................................................................................. 25
3.6 FSB Frequency Select Signals (BSEL[2:0])............................................................25
3.7 FSB Signal Groups.............................................................................................26
3.8 CMOS Signals ...................................................................................................27
3.9 Maximum Ratings..............................................................................................27
3.10 Processor DC Specifications ................................................................................28
4 Package Mechanical Specifications and Pin Information ..........................................33
4.1 Package Mechanical Specifications.......................................................................33
4.2 Processor Pinout and Pin List ..............................................................................36
4.3 Alphabetical Signals Reference............................................................................59
5 Thermal Specifications and Design Considerations .................................................. 67
5.1 Monitoring Die Temperature ...............................................................................69
5.1.1 Thermal Diode ....................................................................................... 69
5.1.2 Intel® Thermal Monitor........................................................................... 70
5.1.3 Digital Thermal Sensor............................................................................72
5.2 Out of Specification Detection .............................................................................73
5.3 PROCHOT# Signal Pin........................................................................................73
Figures
1 Core Low-Power States............................................................................................. 12
2 Package Low-Power States........................................................................................13
3 Active VCC and ICC Loadline for Pentium Processors.....................................................30
4 1-MB die Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)...................................34
5 1-MB Die Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ..................................35
6 Processor Pinout (Top Package View, Left Side)............................................................36
7 Processor Pinout (Top Package View, Right Side).......................................................... 37

4Datasheet
Tables
1 Coordination of Core Low-Power States at the Package Level..........................................13
2 Voltage Identification Definition..................................................................................22
3 BSEL[2:0] Encoding for BCLK Frequency......................................................................25
4 FSB Pin Groups ........................................................................................................26
5 Processor Absolute Maximum Ratings..........................................................................27
6 Voltage and Current Specifications for the Pentium Processors........................................29
7 AGTL+ Signal Group DC Specifications ........................................................................31
8 CMOS Signal Group DC Specifications..........................................................................32
9 Open Drain Signal Group DC Specifications ..................................................................32
10 Pin Name Listing ......................................................................................................38
11 Pin # Listing ............................................................................................................51
12 Signal Description.....................................................................................................59
13 Power Specifications for the Pentium Processors ...........................................................68
14 Thermal Diode Interface............................................................................................69
15 Thermal Diode Parameters Using Transistor Model ........................................................70

Datasheet 5
Revision History
§
Document
Number Revision Number Description Date
322875 -001 Initial Draft October 2009

6Datasheet

Datasheet 7
Introduction
1 Introduction
This document contains electrical, mechanical and thermal specifications for the
following processors:
• The Intel® Pentium® support the Mobile Intel® 4 Series Express Chipset and
Intel® ICH9M I/O controller.
Notes: In this document
1. Intel Pentium processor are referred to as the processor
2. Mobile Intel 4 Series Express Chipset is referred as the GMCH.
Key features include:
• Dual-core processor for mobile with enhanced performance
• Supports Intel architecture with Intel® Wide Dynamic Execution
• Supports L1 cache-to-cache (C2C) transfer
• On-die, primary 32-KB instruction cache and 32-KB, write-back data cache in each
core
• The processor have an on-die, 1-MB second-level, shared cache with Advanced
Transfer Cache architecture
• Streaming SIMD extensions 2 (SSE2), streaming SIMD extensions 3 (SSE3), and
supplemental streaming SIMD extensions 3 (SSSE3)
• Enhanced Intel SpeedStep® Technology
• The processors are offered at 800-MHz, source-synchronous front side bus (FSB)
• Digital thermal sensor (DTS)
• Intel® 64 architecture
• Enhanced Multi-Threaded Thermal Management (EMTTM)
• Processor offered in Micro-FCPGA packaging technology
• Execute Disable Bit support for enhanced security
• Half ratio support (N/2) for core to bus ratio

Introduction
8Datasheet
1.1 Terminology
Term Definition
#
A “#” symbol after a signal name refers to an active low signal, indicating a
signal is in the active state when driven to a low level. For example, when
RESET# is low, a reset has been requested. Conversely, when NMI is high,
a nonmaskable interrupt has occurred. In the case of signals where the
name does not imply an active state but describes part of a binary
sequence (such as address or data), the “#” symbol implies that the signal
is inverted. For example, D[3:0] = “HLHL” refers to a hex “A”, and D[3:0]#
= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
Front Side Bus
(FSB) Refers to the interface between the processor and system core logic (also known as the chipset components).
AGTL+ Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+
signaling technology on some Intel processors.
Storage
Conditions
Refers to a non-operational state. The processor may be installed in a
platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor landings should not
be connected to any supply voltages, have any I/Os biased or receive any
clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device
removed from packaging material) the processor must be handled in
accordance with moisture sensitivity labeling (MSL) as indicated on the
packaging material.
Processor Core Processor core die with integrated L1 and L2 cache. All AC timing and signal
integrity specifications are at the pads of the processor core.
Execute Disable
Bit
The Execute Disable bit allows memory to be marked as executable or non-
executable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to
the operating system. This feature can prevent some classes of viruses or
worms that exploit buffer overrun vulnerabilities and can thus help improve
the overall security of the system. See the Intel® 64 and IA-32
Architectures Software Developer's Manuals for more detailed information.
Intel® 64
Technology 64-bit memory extensions to the IA-32 architecture.
Half ratio support
(N/2) for Core to
Bus ratio
Intel Core 2 Duo processors and Intel Core 2 Extreme processors support
the N/2 feature that allows having fractional core-to-bus ratios. This feature
provides the flexibility of having more frequency options and being able to
have products with smaller frequency steps.
TDP Thermal Design Power.
VCC The processor core power supply.
VSS The processor ground.

Datasheet 9
Introduction
1.2 References
Material and concepts available in the following documents may be beneficial when
reading this document.
NOTE: Contact your Intel representative for the latest revision of this document.
§
Document Document
Number
Intel® Pentium® Processor on 45-nm Technology Specification Update
Mobile Intel® 4 Series Express Chipset Family Datasheet 320122
Mobile Intel® 4 Series Express Chipset Family Specification Update 320123
Intel® I/O Controller Hub 9 (ICH9)/ I/O Controller Hub 9M (ICH9M)
Datasheet 316972
Intel® I/O Controller Hub 9 (ICH9)/ I/O Controller Hub 9M (ICH9M)
Specification Update 316973
Intel® 64 and IA-32 Architectures Software Developer's Manuals
Volume 1: Basic Architecture 253665
Volume 2A: Instruction Set Reference, A-M 253666
Volume 2B: Instruction Set Reference, N-Z 253667
Volume 3A: System Programming Guide 253668
Volume 3B: System Programming Guide 253669

Introduction
10 Datasheet