Intel MultiProcessor User manual

MultiProcessor
Specification
Version 1.4
May 1997

THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY
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Copyright 1993-1997
. Intel Corporation, All Rights Reserved.

iii
Revision History
Revision Revision History Date
Pre-release Version 1.0. Formerly called “PC+MP Specification” 10/27/93
-001 Version 1.1. Resolves conflicts with MCA-based systems. The following
changes have been made:
1. Two MP feature information bytes were moved from the BIOS System
Configuration Table to the RESERVED area of the MP Floating Pointer
Structure.
2. If the MP Floating Pointer Structure is present, it indicates that the system
is MP-compliant, in accordance with this specification. (Previously, this was
indicated by bit 0 of MP Feature Information Byte 1.)
3. One more hardware default system configuration was added for MCA+PCI
with the integrated APIC.
4/11/94
-002 Minor technical corrections. 6/1/94
-003 Added Appendix D: Multiple I/O APIC Multiple PCI Bus Systems. 9/1/94
-004 Version 1.4. Added extended configuration table to improve support for
multiple PCI bus configurations and improve future expandability. Made
clarifications to Appendix B.
7/1/95
-005 Added Appendix E: Errata. Includes information for hierarchical PCI bus. 08/15/96
-006 Appendix E Update. Included Byte 2, Bit 6 information to MP Floating Point
Structure section (4.1). 05/12/97

v
Table of Contents
Chapter 1 Introduction
1.1 Goals ........................................................................................................1-1
1.2 Features of the Specification....................................................................1-2
1.3 Scope........................................................................................................1-2
1.4 Target Audience .......................................................................................1-3
1.5 Organization of This Document................................................................1-3
1.6 Conventions Used in This Document .......................................................1-4
1.7 For More Information................................................................................1-4
Chapter 2 System Overview
2.1 Hardware Overview..................................................................................2-2
2.1.1 System Processors......................................................................2-2
2.1.2 Advanced Programmable Interrupt Controller .............................2-3
2.1.3 System Memory...........................................................................2-4
2.1.4 I/O Expansion Bus.......................................................................2-4
2.2 BIOS Overview.........................................................................................2-5
2.3 Operating System Overview.....................................................................2-5
Chapter 3 Hardware Specification
3.1 System Memory Configuration .................................................................3-1
3.2 System Memory Cacheability and Shareability.........................................3-2
3.3 External Cache Subsystem ......................................................................3-4
3.4 Locking .....................................................................................................3-4
3.5 Posted Memory Write...............................................................................3-5
3.6 Multiprocessor Interrupt Control ...............................................................3-5
3.6.1 APIC Architecture ........................................................................3-5
3.6.2 Interrupt Modes............................................................................3-6
3.6.2.1 PIC Mode......................................................................3-7
3.6.2.2 Virtual Wire Mode .........................................................3-9
3.6.2.3 Symmetric I/O Mode...................................................3-11
3.6.3 Assignment of System Interrupts to the APIC Local Unit...........3-12
3.6.4 Floating Point Exception Interrupt..............................................3-12
3.6.5 APIC Memory Mapping..............................................................3-12

Contents
vi
3.6.6 APIC Identification .....................................................................3-13
3.6.7 APIC Interval Timers..................................................................3-13
3.6.8 Multiple I/O APIC Configurations...............................................3-13
3.7 RESET Support......................................................................................3-14
3.7.1 System-wide RESET .................................................................3-14
3.7.2 System-wide INIT.......................................................................3-15
3.7.3 Processor-specific INIT..............................................................3-15
3.8 System Initial State.................................................................................3-16
3.9 Support for Fault-resilient Booting..........................................................3-16
Chapter 4 MP Configuration Table
4.1 MP Floating Pointer Structure...................................................................4-3
4.2 MP Configuration Table Header...............................................................4-5
4.3 Base MP Configuration Table Entries.......................................................4-6
4.3.1 Processor Entries.........................................................................4-7
4.3.2 Bus Entries.................................................................................4-10
4.3.3 I/O APIC Entries.........................................................................4-12
4.3.4 I/O Interrupt Assignment Entries................................................4-12
4.3.5 Local Interrupt Assignment Entries............................................4-15
4.4 Extended MP Configuration Table Entries..............................................4-17
4.4.1 System Address Space Mapping Entries...................................4-18
4.4.2 Bus Hierarchy Descriptor Entries...............................................4-21
4.4.3 Compatibility Bus Address Space Modifier Entries....................4-22
Chapter 5 Default Configurations
5.1 Discrete APIC Configurations...................................................................5-2
5.2 Integrated APIC Configurations................................................................5-4
5.3 Assignment Of I/O Interrupts To The APIC I/O Unit .................................5-6
5.3.1 EISA and IRQ13 ..........................................................................5-7
5.3.2 Level-triggered Interrupt Support.................................................5-7
5.4 Assignment Of System Interrupts To The APIC Local Unit ......................5-7

Contents
vii
Appendix A System BIOS Programming Guidelines
A.1 BIOS Post Initialization ............................................................................A-1
A.2 Controlling the Application Processors....................................................A-2
A.3 Programming the APIC for Virtual Wire Mode.........................................A-2
A.4 Constructing the MP Configuration Table................................................A-4
Appendix B Operating System Programming Guidelines
B.1 Operating System Boot-up .......................................................................B-1
B.2 Operating System Booting and Self-configuration....................................B-2
B.3 Interrupt Mode Initialization and Handling ................................................B-2
B.4 Application Processor Startup ..................................................................B-3
B.4.1 USING INIT IPI ............................................................................B-4
B.4.2 USING STARTUP IPI...................................................................B-5
B.5 AP Shutdown Handling.............................................................................B-5
B.6 Other IPI Applications...............................................................................B-6
B.6.1 Handling Cache Flush..................................................................B-6
B.6.2 Handling TLB Invalidation............................................................B-6
B.6.3 Handling PTE Invalidation............................................................B-6
B.7 Spurious APIC Interrupts..........................................................................B-6
B.8 Supporting Unequal Processors...............................................................B-7
Appendix C System Compliance Checklist
Appendix D Multiple I/O APIC Multiple PCI Bus Systems
D.1 Interrupt Routing with Multiple APICs.......................................................D-1
D.1.1 Variable Interrupt Routing............................................................D-1
D.1.2 Fixed Interrupt Routing................................................................D-2
D.2 Bus Entries in Systems with More Than One PCI Bus.............................D-3
D.3 I/O Interrupt Assignment Entries for PCI Devices.....................................D-3
Appendix E Errata
Glossary

Contents
viii
Figures 1-1. Conceptual Overview......................................................................1-1
1-2. Memory Layout Conventions ..........................................................1-4
2-1. Multiprocessor System Architecture................................................2-2
2-2. APIC Configuration .........................................................................2-3
3-1. System Memory Address Map........................................................3-2
3-2. PIC Mode.......................................................................................3-8
3-3. Virtual Wire Mode via Local APIC...................................................3-9
3-4. Virtual Wire Mode via I/O APIC.....................................................3-10
3-5. Symmetric I/O Mode .....................................................................3-11
3-6. Multiple I/O APIC Configurations ..................................................3-14
4-1. MP Configuration Data Structures ..................................................4-1
4-2. MP Floating Pointer Structure.........................................................4-3
4-3. MP Configuration Table Header......................................................4-5
4-4. Processor Entry...............................................................................4-7
4-5. Bus Entry.......................................................................................4-10
4-6. I/O APIC Entry...............................................................................4-12
4-7. I/O Interrupt Entry .........................................................................4-13
4-8. Local Interrupt Entry......................................................................4-15
4-9. System Address Space Entry .......................................................4-18
4-10. Example System with Multiple Bus Types and Bridge Types .......4-19
4-11. Bus Hierarchy Descriptor Entry.....................................................4-21
4-12. Compatibility Bus Address Space Modifier Entry..........................4-23
5-1. Default Configuration for Discrete APIC..........................................5-3
5-2. Default Configuration for Integrated APIC.......................................5-5
Tables 1-1. Document Organization ..................................................................1-3
3-1. Memory Cacheability Map...............................................................3-3
3-2. APIC Versions.................................................................................3-6
4-1. MP Floating Pointer Structure Fields ..............................................4-3
4-2. MP Configuration Table Header Fields...........................................4-6
4-3. Base MP Configuration Table Entry Types.....................................4-7
4-4. Processor Entry Fields....................................................................4-8
4-5. Intel486™ and Pentium®Processor Signatures .............................4-9

Contents
ix
4-6. Feature Flags from CPUID Instruction............................................4-9
4-7. Bus Entry Fields............................................................................4-10
4-8. Bus Type String Values.................................................................4-11
4-9. I/O APIC Entry Fields....................................................................4-12
4-10. I/O Interrupt Entry Fields...............................................................4-14
4-11. Interrupt Type Values....................................................................4-15
4-12. Local Interrupt Entry Fields...........................................................4-16
4-13. Extended MP Configuration Table Entry Types............................4-17
4-14. System Address Space Mapping Entry Fields..............................4-19
4-15. Bus Hierarchy Descriptor Entry Fields..........................................4-22
4-16. Compatibility Bus Address Space Modifier Entry Fields ...............4-24
4-17. Predefined Range Lists.................................................................4-24
5-1. Default Configurations.....................................................................5-2
5-2. Default Configuration Interrupt Assignments ..................................5-6
5-3. Assignment of System Interrupts to APIC Local Unit......................5-7
D-1. I/O Interrupt Entry Source Bus IRQ Field for PCI Devices..............D-3
Examples A-1. Programming Local APIC for Virtual Wire Mode.............................A-3
B-1. Universal Start-up Algorithm...........................................................B-3

Version 1.4 1-1
1
Introduction
The MultiProcessor Specification, hereafter known as the “MP specification,” defines an
enhancement to the standard to which PC manufacturers design DOS-compatible systems.
MP-capable operating systems will be able to run without special customization on multiprocessor
systems that comply with this specification. End users who purchase a compliant multiprocessor
system will be able to run their choice of operating systems.
The MP specification covers PC/AT-compatible MP platform designs based on Intel processor
architectures and Advanced Programmable Interrupt Controller (APIC) architectures. The term
“PC/AT-compatible” here refers to the software-visible components of the PC/AT, not to hardware
features, such as the bus implementation, that are not visible to software. An implementation of
this specification may incorporate one or more industry standard buses, such as ISA, EISA, MCA,
PCI, or other OEM-specific buses.
1.1 Goals
The intent of this specification is to establish an MP Platform interface standard that extends the
performance of the existing PC/AT platform beyond the traditional single processor limit, while
maintaining 100% PC/AT binary compatibility.
The ultimate goal is to enable scalable, high-end workstations and enterprise server systems that
provide computer users with superior price/performance and have the ability to execute all existing
AT binaries, as well as MP-ready software packages on shrink-wrapped MP operating systems.
Figure 1-1 shows that at the heart of the specification are the data structures that define the
configuration of the MP system. The BIOS constructs the MP configuration data structures,
presenting the hardware in a known format to the standard device drivers or to the hardware
abstraction layer of the operating system. The specification details default hardware
configurations, and, for added flexibility, outlines extensions to the standard BIOS.
HARDWARE
DRIVER/
HARDWARE
ABSTRACTION LAYER
MP BIOS
OPERATING SYSTEM
MP
CONFIGURATION
DATA
STRUCTURES
Figure 1-1. Conceptual Overview

MultiProcessor Specification
1-2 Version 1.4
1.2 Features of the Specification
The MP specification includes the following features:
• A multiprocessor extension to the PC/AT platform that runs all existing uniprocessor shrink-
wrapped binaries, as well as MP binaries.
• Support for symmetric multiprocessing with one or more processors that are Intel architecture
instruction set compatible, such as the CPUs in the Intel486™ and the Pentium®processor
family.
• Support for symmetric I/O interrupt handling with the APIC, a multiprocessor interrupt
controller.
• Flexibility to use a BIOS with minimal MP-specific support.
• An optional MP configuration table to communicate configuration information to an MP
operating system.
• Incorporation of ISA and other industry standard buses, such as EISA, MCA, VL and PCI
buses in MP-compliant systems.
• Requirements that make secondary cache and memory bus implementation transparent to
software.
1.3 Scope
There are many vendors building innovative MP systems based on Intel architectures today. Intel
supports and encourages vendors to develop advanced approaches to the technological
requirements of today's computing environments. In no way does the MP specification prevent
system manufacturers from adding their own unique value to MP systems. This specification does
not define the only way that multiprocessor systems can be implemented. Vendors may, for
example, create noncompliant, high-performance, scalable multiprocessor systems that do not have
the PC/AT compatibility required by this specification. Hardware vendors will always have the
option of offering one or more customized operating systems that support the unique, value-added
capabilities that they have designed into their systems. End users will be able to benefit from the
additional capabilities that these vendors offer.
The MP specification benefits PC vendors who wish to offer MP-enabled systems without having
to invest in the customization of one or more operating systems. This specification focuses on
providing a standard mechanism to add MP support to personal computers built around the PC/AT
hardware standard. With that goal, the specification covers only the minimum set of capabilities
required to extend the PC/AT platform to be MP-capable. The hardware required to implement the
MP specification is kept to a minimum, as follows:
• One or more processors that are Intel architecture instruction set compatible, such as the CPUs
in the Intel486 or Pentium processor family.
• One or more APICs, such as the Intel 82489DX Advanced Programmable Interrupt Controller
or the integrated APIC, such as that on the Intel Pentium 735\90 and 815\100 processors,
together with a discrete I/O APIC unit.
• The necessary supporting electronics to duplicate the initialization and signaling protocol
described in this specification.
• PC/AT-compliant hardware.

Introduction
Version 1.4 1-3
In addition to the hardware requirements, this document also specifies MP features that are visible
to the BIOS and operating system. However, it is important to understand that as hardware
technology progresses, the functions performed by the BIOS may change in accordance with the
hardware technology. ONLY THE INTERFACE TO THE OPERATING SYSTEM LEVEL
IS EXPECTED TO REMAIN CONSTANT.
This specification does not address issues relating to the processor's System Management Mode
(SMM).
1.4 Target Audience
This document is intended for the following users:
• OEMs who will be creating PC/AT-compatible, MP-ready hardware based on this
specification.
• BIOS developers, either those who create general-purpose BIOS products or those who modify
these products to suit specific MP hardware.
• Operating-system developers who will be adapting MP operating systems to run on the class of
MP-ready platform specified here.
1.5 Organization of This Document
Table 1-1 shows the organization of this document.
Table 1-1. Document Organization
Chapter Description
2 Overview of the MultiProcessor Specification
3 Specification of the MP hardware
4 Specification of MP configuration information available to OS
5 Specification of default hardware configurations
Appendix A Guidelines for MP BIOS programming
Appendix B Guidelines for MP operating system programming
Appendix C Checklist for hardware compliance to the specification
Appendix D Clarifications for multiple I/O APIC, multiple PCI bus systems
Glossary Definitions of specialized terms used in this document

MultiProcessor Specification
1-4 Version 1.4
1.6 Conventions Used in This Document
Signal names that are followed by the character # represent active low signals. For example,
FERR# is active when at its low-voltage state.
Throughout this document, the Intel 82489DX APIC is referred to as the “discrete APIC.” The
term “integrated APIC” is used to refer to an APIC integrated with other system components, such
as the Pentium 735\90 and 815\100 processors. This specification uses the term APIC to refer to
both discrete and integrated versions.
The processors of the Intel486 and Pentium processor family are “little endian” machines. This
means that the low-order byte of a multibyte data item in memory is at the lowest address, while
the high-order byte is at the highest address. Illustrations of data structures in memory show the
lowest addresses at the bottom and the highest addresses at the top of the illustration, as shown in
Figure 1-2. Bit positions are numbered from right to left.
RESERVED
RESERVED
THREE-BYTE FIELD
RESERVED
00H
04H
08H
0CH
31 07815162324
31 07815162324
ONE-BYTE
FIELD
TWO-BYTE FIELD
LOW-ORDER BITSHIGH-ORDER BITS
INCREASING
ADDRESSES
Figure 1-2. Memory Layout Conventions
In some memory layout descriptions, certain fields are marked RESERVED. Software should
initialize these fields as binary zeros, but should otherwise treat them as having a future, though
unknown effect. SOFTWARE SHOULD AVOID ANY DEPENDENCE ON THE VALUES
IN THE RESERVED FIELDS.
1.7 For More Information
For more information, refer to any of the following documents:
• 82489DX Advanced Programmable Interrupt Controller (data book), Intel order number
290446
• Intel486 Microprocessor Programmer's Reference Manual, Intel order number 240486
• Intel Processor Identification with the CPUID Instruction AP-485, Intel order number 241618
• Pentium Processor User’s Manual, Intel order number 241428

Version 1.4 2-1
2
System Overview
In the realm of multiprocessor architectures, there are several conceptual models for tying together
computing elements, and there are a variety of interconnection schemes and details of
implementation. Figure 2-1 shows the general structure of a design based on the MP specification.
The MP specification’s model of multiprocessor systems incorporates a tightly-coupled, shared-
memory architecture with a distributed interprocessor and I/O interrupt capability. It is fully
symmetric; that is, all processors are functionally identical and of equal status, and each processor
can communicate with every other processor. There is no hierarchy, no master-slave relationship,
no geometry that limits communication only to “neighboring” processors. The model is symmetric
in two important respects:
• Memory symmetry. Memory is symmetric when all processors share the same memory space
and access that space by the same addresses. Memory symmetry offers a very important
feature—the ability for all processors to execute a single copy of the operating system. Any
existing system and application software will execute the same, regardless of the number of
processors installed in a system.
• I/O symmetry. I/O is symmetric when all processors share access to the same I/O subsystem
(including I/O ports and interrupt controllers) and any processor can receive interrupts from
any source. Some multiprocessor systems that have symmetric access to memory are actually
asymmetric with regard to I/O interrupts, because they dedicate one processor to interrupt
functions. I/O symmetry helps eliminate the potential of an I/O bottleneck, thereby increasing
system scalability.
With both memory and I/O symmetry, a system that complies with the MP specification can
achieve hardware scalability as well as support software standardization. Based on this kind of
scalable architecture, systems developers can produce systems that span a wide range of price and
performance, and that all execute the same binaries.

MultiProcessor Specification
2-2 Version 1.4
HIGH-BANDWIDTH MEMORY BUS
APIC ADVANCED PROGRAMMABLE
INTERRUPT CONTROLLER
ICC INTERRUPT CONTROLLER
COMMUNICATIONS
CPU CPU CPU
SHARED
MEMORY
MODULE
GRAPHICS
FRAME
BUFFER I/O
INTERFACE
APIC
I/O
INTERFACE
APIC
ICC BUS
I/O EXPANSION BUSI/O EXPANSION BUS
Figure 2-1. Multiprocessor System Architecture
2.1 Hardware Overview
The MP specification defines a system architecture based on the following hardware components:
• One or more processors that are Intel architecture instruction set compatible, such as the CPUs
in the Intel486 and the Pentium processor family.
• One or more APICs, such as the Intel 82489DX Advanced Programmable Interrupt Controller
or the integrated APIC on the Pentium 735\90 and 815\100 processors.
• Software-transparent cache and shared memory subsystem.
• Software-visible components of the PC/AT platform.
2.1.1 System Processors
To maintain compatibility with existing PC/AT software products, this specification is based on
the Intel486 and the Pentium processor family. To achieve a minimum level of MP system
performance, two or more processors that are Intel architecture instruction set compatible are
required.
Figure 2-2 gives a different point of view of a compliant system, showing the configuration of the
APICs with respect to the CPUs. While all processors in a compliant system are functionally
identical, this specification classifies them into two types: the bootstrap processor (BSP) and the
application processors (AP). Which processor is the BSP is determined by the hardware or by the
hardware in conjunction with the BIOS. This differentiation is for convenience and is in effect

System Overview
Version 1.4 2-3
only during the initialization and shutdown processes. The BSP is responsible for initializing the
system and for booting the operating system; APs are activated only after the operating system is
up and running. CPU1 is designated as the BSP. CPU2, CPU3, and so on, are designated as the
APs.
ICC BUS
LOCAL
APIC
1
CPU 1
LOCAL
APIC
2
LOCAL
APIC
3
CPU 2 CPU 3
BSP AP1 AP2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
I/O
APIC
INTERRUPT
REQUESTS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
I/O
APIC
INTERRUPT
REQUESTS
Figure 2-2. APIC Configuration
2.1.2 Advanced Programmable Interrupt Controller
The Advanced Programmable Interrupt Controller (APIC) is based on a distributed architecture in
which interrupt control functions are distributed between two basic functional units, the local unit
and the I/O unit. The local and I/O units communicate through a bus called the Interrupt Controller
Communications (ICC) bus, as shown in Figure 2-2.
In a multiprocessor system, multiple local and I/O APIC units operate together as a single entity,
communicating with one another over the ICC bus. The APIC units are collectively responsible
for delivering interrupts from interrupt sources to interrupt destinations throughout the
multiprocessor system.
The APICs help achieve the goal of scalability by doing the following:
• Off-loading interrupt-related traffic from the memory bus, making the memory bus more
available for processor use.
• Helping processors share the interrupt processing load with other processors.
The APICs help achieve the goal of AT-compatibility by cooperating with 8259A-equivalent PICs
in the system.

MultiProcessor Specification
2-4 Version 1.4
The local APIC units also provide interprocessor interrupts (IPIs), which allow any processor to
interrupt any other processor or set of processors. There are several types of IPIs. Among them,
the INIT IPI and the STARTUP IPI are specifically designed for system startup and shutdown.
Each local APIC has a Local Unit ID Register and each I/O APIC has an I/O Unit ID Register.
The ID serves as a physical name for each APIC unit. It is used by software to specify destination
information for I/O interrupts and interprocessor interrupts, and is also used internally for accessing
the ICC bus.
Due to the distributed architecture, the APIC local and I/O units can be implemented in either a
single chip, such as Intel’s 82489DX interrupt controller, or they can be integrated with other parts
of the system’s components. For example, the local APIC may be integrated with the CPU chip,
such as Intel’s Pentium processors (735\90, 815\100), and the I/O APIC may be integrated with the
I/O chipset, such as Intel’s 82430 PCI-EISA bridge chipset.
2.1.3 System Memory
A system that complies with the MP specification uses the standard AT memory architecture. All
memory is allocated for system memory with the exception of addresses 0A_0000h through
0F_FFFFh and 0FFFE_0000h through 0FFFF_FFFFh, which are reserved for I/O devices and the
BIOS.
Compared to a uniprocessor system, a symmetric multiprocessor system imposes a high demand
for memory bus bandwidth. The demand is proportional to the number of processors on the
memory bus. To reduce memory bus bandwidth limitations, an implementation of this
specification should use a secondary cache that has high-performance features, such as a write-back
update policy and a snooping cache-consistency protocol. A secondary cache can push the
scalability limit upward by reducing bus traffic and increasing bus bandwidth.
While both secondary caches and memory bus controllers are critical components for high
performance in a symmetric multiprocessor system, this specification does not detail their
implementation, requiring only that they be totally software transparent.
2.1.4 I/O Expansion Bus
The MP specification provides a multiprocessor extension to the industry-standard PC/AT
platform. The term “industry-standard PC/AT platform” here refers to the software-visible
components of the PC/AT. The standard does not designate a specific bus architecture. All
industry-standard buses, such as ISA, EISA, MCA, VL, and PCI, can be incorporated in the
design. Systems developers can implement one or more bus types in their designs, depending on
the systems’ I/O performance or capacity requirements.

System Overview
Version 1.4 2-5
2.2 BIOS Overview
A BIOS functions as an insulator between the hardware on one hand, and the operating system and
applications software on the other. A standard uniprocessor BIOS performs the following
functions:
• Tests system components.
• Builds configuration tables to be used by the operating system.
• Initializes the processor and the rest of the system to a known state.
• Provides run-time device-oriented services.
For a multiprocessor system, the BIOS may perform the following additional functions:
• Pass configuration information to the operating system that identifies all processors and other
multiprocessing components of the system.
• Initialize all processors and the rest of the multiprocessing components to a known state.
This specification allows a wide range of capability in the BIOS. At the minimal end of the
capability scale, the system developer can simply insert an MP floating pointer structure in the
standard BIOS. The cost of this level of simplicity in the BIOS, however, is that the system
developer has less flexibility in the design of the hardware. At the maximal end of the BIOS
capability scale might be a BIOS that dynamically configures the system to provide resilience in
the face of component malfunctions.
BIOS developers should read Chapters 3, 4, 5, and Appendix A to understand the tradeoffs
between hardware and BIOS capabilities.
2.3 Operating System Overview
Enabling the creation of shrink-wrapped MP operating systems is one of the principal goals of this
specification. This goal is achieved by allowing a flexible balance between the capabilities of the
hardware and those of the BIOS. The potentially vast variety of hardware configurations is
reduced by the BIOS to a few simple scenarios that can be readily handled by the low-level boot-
up phase of the operating system.
Operating-system developers should read Chapters 3, 4, and 5, and Appendixes A and B to fully
understand the interface between the BIOS and the operating system.