Intel MultiProcessor User manual

MultiProcessor
Specification
Version 1.4
May 1997

THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY
OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING
OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
A license is hereby granted to copy and reproduce this specification for internal use only.
No other license, express or implied, by estoppel or otherwise, to any other intellectual property rights is granted herein.
Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to implementation of information in
this specification. Intel does not warrant or represent that such implementation(s) will not infringe such rights.
Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark
or products.
* Third-party trademarks are the property of their respective owners.
Additional copies of this document or other Intel literature may be obtained from:
Intel Corporation
Literature Center
P.O. Box 7641
Mt. Prospect IL 60056-7641
or call 800-879-4683
printed on
recycled paper
Copyright 1993-1997
. Intel Corporation, All Rights Reserved.

iii
Revision History
Revision Revision History Date
Pre-release Version 1.0. Formerly called “PC+MP Specification” 10/27/93
-001 Version 1.1. Resolves conflicts with MCA-based systems. The following
changes have been made:
1. Two MP feature information bytes were moved from the BIOS System
Configuration Table to the RESERVED area of the MP Floating Pointer
Structure.
2. If the MP Floating Pointer Structure is present, it indicates that the system
is MP-compliant, in accordance with this specification. (Previously, this was
indicated by bit 0 of MP Feature Information Byte 1.)
3. One more hardware default system configuration was added for MCA+PCI
with the integrated APIC.
4/11/94
-002 Minor technical corrections. 6/1/94
-003 Added Appendix D: Multiple I/O APIC Multiple PCI Bus Systems. 9/1/94
-004 Version 1.4. Added extended configuration table to improve support for
multiple PCI bus configurations and improve future expandability. Made
clarifications to Appendix B.
7/1/95
-005 Added Appendix E: Errata. Includes information for hierarchical PCI bus. 08/15/96
-006 Appendix E Update. Included Byte 2, Bit 6 information to MP Floating Point
Structure section (4.1). 05/12/97

v
Table of Contents
Chapter 1 Introduction
1.1 Goals ........................................................................................................1-1
1.2 Features of the Specification....................................................................1-2
1.3 Scope........................................................................................................1-2
1.4 Target Audience .......................................................................................1-3
1.5 Organization of This Document................................................................1-3
1.6 Conventions Used in This Document .......................................................1-4
1.7 For More Information................................................................................1-4
Chapter 2 System Overview
2.1 Hardware Overview..................................................................................2-2
2.1.1 System Processors......................................................................2-2
2.1.2 Advanced Programmable Interrupt Controller .............................2-3
2.1.3 System Memory...........................................................................2-4
2.1.4 I/O Expansion Bus.......................................................................2-4
2.2 BIOS Overview.........................................................................................2-5
2.3 Operating System Overview.....................................................................2-5
Chapter 3 Hardware Specification
3.1 System Memory Configuration .................................................................3-1
3.2 System Memory Cacheability and Shareability.........................................3-2
3.3 External Cache Subsystem ......................................................................3-4
3.4 Locking .....................................................................................................3-4
3.5 Posted Memory Write...............................................................................3-5
3.6 Multiprocessor Interrupt Control ...............................................................3-5
3.6.1 APIC Architecture ........................................................................3-5
3.6.2 Interrupt Modes............................................................................3-6
3.6.2.1 PIC Mode......................................................................3-7
3.6.2.2 Virtual Wire Mode .........................................................3-9
3.6.2.3 Symmetric I/O Mode...................................................3-11
3.6.3 Assignment of System Interrupts to the APIC Local Unit...........3-12
3.6.4 Floating Point Exception Interrupt..............................................3-12
3.6.5 APIC Memory Mapping..............................................................3-12

Contents
vi
3.6.6 APIC Identification .....................................................................3-13
3.6.7 APIC Interval Timers..................................................................3-13
3.6.8 Multiple I/O APIC Configurations...............................................3-13
3.7 RESET Support......................................................................................3-14
3.7.1 System-wide RESET .................................................................3-14
3.7.2 System-wide INIT.......................................................................3-15
3.7.3 Processor-specific INIT..............................................................3-15
3.8 System Initial State.................................................................................3-16
3.9 Support for Fault-resilient Booting..........................................................3-16
Chapter 4 MP Configuration Table
4.1 MP Floating Pointer Structure...................................................................4-3
4.2 MP Configuration Table Header...............................................................4-5
4.3 Base MP Configuration Table Entries.......................................................4-6
4.3.1 Processor Entries.........................................................................4-7
4.3.2 Bus Entries.................................................................................4-10
4.3.3 I/O APIC Entries.........................................................................4-12
4.3.4 I/O Interrupt Assignment Entries................................................4-12
4.3.5 Local Interrupt Assignment Entries............................................4-15
4.4 Extended MP Configuration Table Entries..............................................4-17
4.4.1 System Address Space Mapping Entries...................................4-18
4.4.2 Bus Hierarchy Descriptor Entries...............................................4-21
4.4.3 Compatibility Bus Address Space Modifier Entries....................4-22
Chapter 5 Default Configurations
5.1 Discrete APIC Configurations...................................................................5-2
5.2 Integrated APIC Configurations................................................................5-4
5.3 Assignment Of I/O Interrupts To The APIC I/O Unit .................................5-6
5.3.1 EISA and IRQ13 ..........................................................................5-7
5.3.2 Level-triggered Interrupt Support.................................................5-7
5.4 Assignment Of System Interrupts To The APIC Local Unit ......................5-7

Contents
vii
Appendix A System BIOS Programming Guidelines
A.1 BIOS Post Initialization ............................................................................A-1
A.2 Controlling the Application Processors....................................................A-2
A.3 Programming the APIC for Virtual Wire Mode.........................................A-2
A.4 Constructing the MP Configuration Table................................................A-4
Appendix B Operating System Programming Guidelines
B.1 Operating System Boot-up .......................................................................B-1
B.2 Operating System Booting and Self-configuration....................................B-2
B.3 Interrupt Mode Initialization and Handling ................................................B-2
B.4 Application Processor Startup ..................................................................B-3
B.4.1 USING INIT IPI ............................................................................B-4
B.4.2 USING STARTUP IPI...................................................................B-5
B.5 AP Shutdown Handling.............................................................................B-5
B.6 Other IPI Applications...............................................................................B-6
B.6.1 Handling Cache Flush..................................................................B-6
B.6.2 Handling TLB Invalidation............................................................B-6
B.6.3 Handling PTE Invalidation............................................................B-6
B.7 Spurious APIC Interrupts..........................................................................B-6
B.8 Supporting Unequal Processors...............................................................B-7
Appendix C System Compliance Checklist
Appendix D Multiple I/O APIC Multiple PCI Bus Systems
D.1 Interrupt Routing with Multiple APICs.......................................................D-1
D.1.1 Variable Interrupt Routing............................................................D-1
D.1.2 Fixed Interrupt Routing................................................................D-2
D.2 Bus Entries in Systems with More Than One PCI Bus.............................D-3
D.3 I/O Interrupt Assignment Entries for PCI Devices.....................................D-3
Appendix E Errata
Glossary

Contents
viii
Figures 1-1. Conceptual Overview......................................................................1-1
1-2. Memory Layout Conventions ..........................................................1-4
2-1. Multiprocessor System Architecture................................................2-2
2-2. APIC Configuration .........................................................................2-3
3-1. System Memory Address Map........................................................3-2
3-2. PIC Mode.......................................................................................3-8
3-3. Virtual Wire Mode via Local APIC...................................................3-9
3-4. Virtual Wire Mode via I/O APIC.....................................................3-10
3-5. Symmetric I/O Mode .....................................................................3-11
3-6. Multiple I/O APIC Configurations ..................................................3-14
4-1. MP Configuration Data Structures ..................................................4-1
4-2. MP Floating Pointer Structure.........................................................4-3
4-3. MP Configuration Table Header......................................................4-5
4-4. Processor Entry...............................................................................4-7
4-5. Bus Entry.......................................................................................4-10
4-6. I/O APIC Entry...............................................................................4-12
4-7. I/O Interrupt Entry .........................................................................4-13
4-8. Local Interrupt Entry......................................................................4-15
4-9. System Address Space Entry .......................................................4-18
4-10. Example System with Multiple Bus Types and Bridge Types .......4-19
4-11. Bus Hierarchy Descriptor Entry.....................................................4-21
4-12. Compatibility Bus Address Space Modifier Entry..........................4-23
5-1. Default Configuration for Discrete APIC..........................................5-3
5-2. Default Configuration for Integrated APIC.......................................5-5
Tables 1-1. Document Organization ..................................................................1-3
3-1. Memory Cacheability Map...............................................................3-3
3-2. APIC Versions.................................................................................3-6
4-1. MP Floating Pointer Structure Fields ..............................................4-3
4-2. MP Configuration Table Header Fields...........................................4-6
4-3. Base MP Configuration Table Entry Types.....................................4-7
4-4. Processor Entry Fields....................................................................4-8
4-5. Intel486™ and Pentium®Processor Signatures .............................4-9

Contents
ix
4-6. Feature Flags from CPUID Instruction............................................4-9
4-7. Bus Entry Fields............................................................................4-10
4-8. Bus Type String Values.................................................................4-11
4-9. I/O APIC Entry Fields....................................................................4-12
4-10. I/O Interrupt Entry Fields...............................................................4-14
4-11. Interrupt Type Values....................................................................4-15
4-12. Local Interrupt Entry Fields...........................................................4-16
4-13. Extended MP Configuration Table Entry Types............................4-17
4-14. System Address Space Mapping Entry Fields..............................4-19
4-15. Bus Hierarchy Descriptor Entry Fields..........................................4-22
4-16. Compatibility Bus Address Space Modifier Entry Fields ...............4-24
4-17. Predefined Range Lists.................................................................4-24
5-1. Default Configurations.....................................................................5-2
5-2. Default Configuration Interrupt Assignments ..................................5-6
5-3. Assignment of System Interrupts to APIC Local Unit......................5-7
D-1. I/O Interrupt Entry Source Bus IRQ Field for PCI Devices..............D-3
Examples A-1. Programming Local APIC for Virtual Wire Mode.............................A-3
B-1. Universal Start-up Algorithm...........................................................B-3