Intel Xeon Guide

Intel®Xeon™ Processor and
Intel®E7500/E7501 Chipset
Compatible Platform
Design Guide Addendum for Embedded Applications
July 2003
Order Number: 273707-004

2Platform Design Guide Addendum
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Platform Design Guide Addendum 3
Contents
Contents
1.0 Introduction......................................................................................................................................7
1.1 Reference Documentation....................................................................................................7
2.0 Uni-processor System Bus Routing Guidelines...............................................................................9
2.1 Routing Guidelines for the 2X and 4X Signal Groups.........................................................11
2.1.1 Design Recommendations.....................................................................................12
2.2 Routing Guidelines for Common Clock Signals..................................................................13
2.2.1 Wired-OR Signals..................................................................................................13
2.3 Routing Guidelines for Asynchronous GTL+ and Miscellaneous Signals...........................14
2.3.1 Asynchronous GTL+ Signals Driven by the Processor..........................................15
2.3.1.1 Voltage Translation for FERR#..............................................................15
2.3.1.2 Proper THERMTRIP# Usage.................................................................16
2.3.2 Asynchronous GTL+ Signals Driven by the Chipset..............................................17
2.3.2.1 Voltage Translation for INIT#.................................................................17
2.3.3 BR[3:0] Routing Guidelines for Uni-processor Designs.........................................18
3.0 Memory Interface Routing Guidelines ...........................................................................................21
3.1 DIMM Types .......................................................................................................................22
3.2 Dual Channel DDR Overview .............................................................................................22
3.2.1 Dual Channel Source Synchronous Signal Group Routing ...................................23
3.2.2 Dual Channel Command Clock Routing................................................................25
3.2.3 Dual Channel Source Clocked Signal Group Routing ...........................................26
3.2.4 Dual Channel Chip Select Routing ........................................................................27
3.2.5 Dual Channel Clock Enable Routing .....................................................................28
3.2.6 2.5 Volt Decoupling Requirements ........................................................................28
3.3 Single Channel DDR Overview...........................................................................................30
3.3.1 Unused Channel B.................................................................................................31
3.3.2 Single Channel Source Synchronous Signal Group Routing.................................32
3.3.3 Single Channel Command Clock Routing..............................................................36
3.3.4 Single Channel Source Clocked Signal Group Routing.........................................37
3.3.5 Single Channel Chip Select Routing......................................................................38
3.3.6 Single Channel Clock Enable Routing...................................................................39
3.3.7 Single Channel DC Biasing Signals.......................................................................40
3.3.7.1 Single Channel Receive Enable Signal (RCVEN#) ...............................40
3.3.7.2 Single Channel DDRCOMP...................................................................41
3.3.7.3 Single Channel DDRVREF and ODTCOMP..........................................41
3.3.7.4 Single Channel DDRCVO......................................................................41
3.3.8 Single Channel DDR Signal Termination and Decoupling.....................................42
3.3.9 2.5 V Decoupling Requirements............................................................................42

4Platform Design Guide Addendum
Contents
Figures
1 Uni-processor System Bus Topology.........................................................................................10
2 Topology for Asynchronous GTL+ Signals Driven by the Processor..........................................15
3 FERR# Routing Topology for Low Voltage Intel®Xeon™ Processors.......................................16
1 Recommended THERMTRIP# Circuit........................................................................................16
4 Topology for Asynchronous GTL+ Signals Driven by the Chipset..............................................17
5 INIT# Routing Topology for a Uni-processor System.................................................................18
6 Voltage Translator Circuit...........................................................................................................18
7 BR[3:0]# Connection for UP Configuration.................................................................................19
8 DIMM Connector Styles Supported............................................................................................22
9 1-DIMM per Channel Implementation.........................................................................................23
10 2-DIMMs per Channel Implementation.......................................................................................23
11 Dual Channel 2-DIMM Command Clock Topology.....................................................................26
12 1-DIMM Per Channel Decoupling...............................................................................................29
13 2-DIMMs Per Channel Decoupling.............................................................................................30
14 Single Channel 2-DIMM Implementation....................................................................................31
15 Single Channel 4-DIMM Implementation....................................................................................31
16 Single Channel Source Synchronous Topology DIMM Solution ................................................35
17 Trace Length Matching Requirements for Single Channel Source Synchronous Routing.........35
18 Single Channel 2-DIMM Command Clock Topology..................................................................36
19 SIngle Channel Source Clocked Signal Topology......................................................................37
20 Single Channel Chip Select Topology........................................................................................38
21 Single Channel CKE Topology...................................................................................................39
22 Single Channel Receive Enable Signal Routing Guidelines.......................................................40
23 Single Channel DDRCOMP Resistive Compensation................................................................41
24 Single Channel DDRCVO Single Channel Routing Guidelines..................................................42
25 Single Channel 2-DIMM Decoupling ..........................................................................................43
26 Single Channel 4-DIMM Decoupling ..........................................................................................44
Tables
1 Reference Documents..................................................................................................................7
2 System Bus Signal Groups...........................................................................................................9
3 Uni-processor System Bus Routing Summary ...........................................................................10
4 2X and 4X Signal Groups...........................................................................................................11
5 Source Synchronous Signals and Associated Strobes ..............................................................11
6 Common Clock Signals ..............................................................................................................13
7 Asynchronous GTL+ and Miscellaneous Signals.......................................................................14
8 Dual Channel Source Synchronous Signal Group Routing Guidelines......................................24
9 Dual Channel Command Clock Pair Routing Guidelines ...........................................................25
10 Dual Channel Source Clocked Signal Group Routing Guidelines..............................................26
11 Dual Channel Chip Select Routing Guidelines...........................................................................27
12 Dual Channel Clock Enable Routing Guidelines ........................................................................28
13 Channel B Signal Terminations..................................................................................................32
14 Single Channel DQ/CB to DQS Mapping ...................................................................................32
15 Single Channel Source Synchronous Signal Group Routing Guidelines ...................................34
16 Single Channel Command Clock Pair Routing Guidelines.........................................................36

Platform Design Guide Addendum 5
Contents
17 Single Channel Source Clocked Signal Group Routing Guidelines............................................37
18 Single Channel Chip Select Routing Guidelines.........................................................................38
19 Single Channel Clock Enable Routing Guidelines......................................................................39
20 Single Channel Receive Enable Routing Guidelines..................................................................40
21 DDRCOMP Routing Guidelines..................................................................................................41
22 DDRCVO Routing Guidelines.....................................................................................................42
Revision History
Date Revision Description
July 2003 -004 Updated memory interface routing information and added Low
Voltage Intel®XeonTM processor information.
January 2003 -003 Updated and expanded memory interface routing information.
Added E7501 chipset information.
June 2002 -002 Document Update
January 2002 -001 Initial Release

6Platform Design Guide Addendum
Contents
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Intel®Xeon™ Processor and Intel®E7500/E7501 Chipset Compatible Platform
Platform Design Guide Addendum 7
1.0 Introduction
This document is an addendum to the Intel®Xeon™ Processor and Intel®E7500/E7501 Chipset
Compatible Platform Design Guide. It contains applied computing-specific guidelines, such as uni-
processor design guidelines, angled Double Data Rate (DDR) guidelines and single channel DDR
guidelines.
Carefully follow the design information and recommendations provided in this document. These
design guidelines have been developed to ensure maximum flexibility for system designers while
reducing the risk of board-related issues.
Note that the guidelines recommended in this document are based on experience and preliminary
simulation work done at Intel.
1.1 Reference Documentation
Table 1. Reference Documents (Sheet 1 of 2)
Document Location
Intel®E7501 Chipset Memory Controller Hub (MCH)
Datasheet http://developer.intel.com/design/chipsets/datashts/
251927.htm
Intel®Xeon™ Processor and Intel®E7500/E7501
Chipset Compatible Platform Design Guide http://developer.intel.com/design/chipsets/designex/
251929.htm
Intel®Xeon™ Processor with 512 KB L2 Cache and
Intel E7500 Chipset Platform Design Guide http://developer.intel.com/design/chipsets/e7500/
guides/298649.htm
Intel®Xeon™ Processor with 512 KB L2 Cache at
1.80 GHz to 2.40 GHz Datasheet http://developer.intel.com/design/Xeon/datashts/
298642.htm
Intel®E7500 Chipset Memory Controller Hub (MCH)
Datasheet http://developer.intel.com/design/chipsets/e7500/
datashts/290730.htm
Intel®82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2)
Datasheet http://developer.intel.com/design/chipsets/e7500/
datashts/290732.htm
Intel 82801CA I/O Controller Hub 3 (ICH-3) Datasheet http://developer.intel.com/design/chipsets/e7500/
datashts/290733.htm
Intel®82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2)
Specification Update http://www.intel.com/design/chipsets/e7500/
specupdt/290735.htm
Intel®82801CA I/O Controller Hub 3 (ICH3-S)
Specification Update http://www.intel.com/design/chipsets/e7500/
specupdt/290739.htm
603-Pin Socket Design Guidelines http://developer.intel.com/design/Xeon/guides/
249672.htm
VRM 9.1 DC-DC Converter Design Guidelines http://developer.intel.com/design/Xeon/guides/
298646.htm
Intel®Xeon™ Processor Voltage Regulator Down
(VRD) Design Guidelines http://developer.intel.com/design/Xeon/guides/
298644.htm
Intel®Xeon™ Processor with 512 KB L2 Cache
System Compatibility Guidelines http://developer.intel.com/design/Xeon/guides/
298645.htm
Intel®Xeon™ Processor Thermal Design Guidelines http://developer.intel.com/design/Xeon/guides/
298348.htm
Intel®E7500 Chipset Thermal and Mechanical Design
Guidelines http://developer.intel.com/design/chipsets/e7500/
guides/298647.htm

Intel®Xeon™ Processor and Intel®E7500/E7501 Chipset Compatible Platform
8Platform Design Guide Addendum
Intel®Xeon™ Processor Thermal Solution Functional
Specifications http://developer.intel.com/design/Xeon/applnots/
249673.htm
Intel®Xeon™ Processor with 512 KB L2 Cache
Thermal Models http://developer.intel.com/design/Xeon/devtools/
Intel®Xeon™ Processor with 512 KB L2 Cache
Mechanical Model in IGES http://developer.intel.com/design/Xeon/devtools/
Intel®Xeon™ Processor with 512 KB L2 Cache
Mechanical Model in ProE* Format http://developer.intel.com/design/Xeon/devtools/
AP-728 Intel ® ICH Family Real Time Clock (RTC)
Accuracy and Considerations Under Test Conditions http://developer.intel.com/design/chipsets/applnots/
292276.htm
ITP700 Debug Port Design Guide http://developer.intel.com/design/Xeon/guides/
249679.htm
Intel®Xeon™ Processor with 512 KB L2 Cache Signal
Integrity Models http://developer.intel.com/design/Xeon/devtools
PCI Bus Power Management Interface Specification,
Revision 1.1 http://www.pcisig.com/specifications/conventional/
pci_bus_power_management_interface
PCI Hot Plug Specification, Revision 1.1 http://www.pcisig.com/specifications/conventional/
pci_hot_plug
PCI Local Bus Specification, Revision 2.2 http://www.pcisig.com/specifications/conventional/
conventional_pci
PCI-PCI Bridge Architecture Specification, Revision
1.1 http://www.pcisig.com/specifications/conventional/
pci_to_pci_bridge_architecture
PCI Standard Hot-Plug Controller and Subsystem
Specification, Revision 1.0 http://www.pcisig.com/specifications/conventional/
pci_hot_plug
PCI-X Specification, Revision 1.0a http://www.pcisig.com/specifications/pcix_20/pci_x/
System Management Bus Specification (SMBus),
Revision 1.1 http://www.sbs-forum.org/
Universal Serial Bus Specification, Revision 1.1 http://www.usb.org/developers/docs/
Low Voltage Intel®XeonTM processor at 1.6 GHz and
2.0 GHz Datasheet http://www.intel.com/design/intarch/datashts/
273766.htm
Intel®XeonTM processor with 533 MHz System Bus at
2.0 GHz to 2.8 GHz Datasheet http://www.intel.com/design/xeon/datashts/
252135.htm
Low Voltage Intel®XeonTM processor for Embedded
Applications Thermal Design Guidelines http://www.intel.com/design/intarch/designgd/
273764.htm
Table 1. Reference Documents (Sheet 2 of 2)
Document Location

Intel®Xeon™ Processor and Intel®E7500/E7501 Chipset Compatible Platform
Platform Design Guide Addendum 9
2.0 Uni-processor System Bus Routing Guidelines
This section covers the system bus source synchronous (data, address, and associated strobes) and
common clock signal routing for Intel®Xeon™ processor with 512 KB L2 cache (400/533 MHz
FSB)/Low Voltage Intel®Xeon™ processor (400 MHz FSB) and Intel®E7500/E7501 chipset-
based systems, in a uni-processor (UP) configuration. Table 2 lists the signals and their
corresponding signal types.
Figure 1 describes the uni-processor system bus topology.
Table 2. System Bus Signal Groups
Signal Group Type Signals
AGTL+ Common Clock Input Synchronous to BCLK BPRI#, BR[3:1]#1,2, DEFER#, RESET#1,
RS[2:0]#, RSP#, TRDY#
AGTL+ Common Clock I/O Synchronous to BCLK
ADS#, AP[1:0]#, BINIT#3, BNR#3,
BPM[5:0]#1, BR0#1, DBSY#, DP[3:0]#,
DRDY#, HIT#3, HITM#3, LOCK#,
MCERR#3
AGTL+ Source Synchronous I/O:
4X Group Synchronous to associated strobe D[63:0]#, DBI[3:0]#
AGTL+ Source Synchronous I/O:
2X Group Synchronous to associated strobe A[35:3]#4, REQ[4:0]#
AGTL+ Strobes Synchronous to BCLK
[1:0] ADSTB[1:0]#, DSTBN[3:0]#, DSTBP[3:0]#
Async GTL+ Input1Asynchronous A20M#, IGNNE#, INIT#4, LINT0/INTR,
LINT1/ NMI, PWRGOOD, SMI#4, SLP#,
STPCLK#
Async GTL+ Output1Asynchronous FERR#, IERR#, THERMTRIP#,
PROCHOT#7
System Bus Clock Clock BCLK0, BCLK1
TAP Input6Synchronous to TCK TCK, TDI, TMS, TRST#
TAP Output6Synchronous to TCK TDO
SMBus Interface1Synchronous to SM_CLK SM_EP_A[2:0], SM_TS_A[1:0], SM_DAT,
SM_CLK, SM_ALERT#, SM_WP
Power/Other Power/Other
GTLREF[3:0], COMP[1:0], OTDEN,
RESERVED, SKTOCC#, TESTHI[6:0],
VID[4:0], VCC_CPU, SM_VCC5, VCCA,
VSSA, VCCIOPLL, VSS, VCCSENSE,
VSSSENSE
NOTES:
1. These signals do not have on-die termination on the processor. They must be terminated properly on the
system board. If the signal is not connected, it must be pulled to the appropriate voltage level through a 1
kΩ ± 5% resistor.
2. Xeon processors use only BR0# and BR1#.
3. These signals are ‘wired-OR’ signals and may be driven simultaneously by multiple agents. For further
details on how to implement wired-OR signals, refer to the routing guidelines in Section 2.2.1.
4. The value of these pins driving the active edge of RESET# determine processor configuration options.
5. SM_VCC has critical power sequencing requirements.
6. Terminations and routing for TAP signals and all debug port signals are found in the ITP700 Debug Port
Design Guide.
7. PROCHOT# is input/output on Low Voltage Intel® Xeon™ processor D-stepping and beyond.

Intel®Xeon™ Processor and Intel®E7500/E7501 Chipset Compatible Platform
10 Platform Design Guide Addendum
Refer to Table 3 for a summary of the uni-processor system bus routing recommendations. Use this
as a quick reference only. The following sections provide more information for each parameter.
Intel strongly recommends simulation of all signals to ensure that setup and hold times are met.
Figure 1. Uni-processor System Bus Topology
A9044-01
Processor MCH
Pad
Length L1 = 3.5 - 10"
Pad
Note: Package trace
Motherboard PCB trace
Table 3. Uni-processor System Bus Routing Summary
Parameter Platform Routing Guidelines
Trace width/spacing 5/15 mils
4X signal group line lengths 3.5“– 10“pin-to-pin
Length must be added to the system board trace between agents to
compensate for the stub created by the processor package
DSTBn/p[3:0]# line lengths DSTB# signals should follow the same routing rules as the data signals
A 25 mil spacing should be maintained around each strobe signal (between
DSTBp# and DSTBn#, and any other signal.)
2X signal group line lengths Address signals should follow the same routing rules as the data signals.
ADSTB[1:0]# line lengths ADSTB# signals should follow the same routing rules as the DSTB# signals.
Common clock signal line
lengths Common clock signals should follow the same routing rules as the data signals, however no length compensation is necessary.
Topology The processor must have on-die termination enabled.
Routing priorities All signals within the same strobe group must be routed on same layer for the
entire length of the bus.
Reference plane requirements
Ground reference only.
Avoid changing layers when routing system bus signals.
If a layer change must occur,use vias connecting the two reference planes to
provide a low impedance path for the return current. Vias should be as close
as possible to the signal via.
System board Impedance 50 Ω ± 10%

Intel®Xeon™ Processor and Intel®E7500/E7501 Chipset Compatible Platform
Platform Design Guide Addendum 11
2.1 Routing Guidelines for the 2X and 4X Signal Groups
The 4X group of signals uses four times the frequency of the base clock, or 400 MHz. The 2X
group uses twice the frequency of the base clock, or 200 MHz. The 2X and 4X signals are listed in
Table 4. Table 5 lists the 2X and 4X signals with their associated strobes.
Routing guidelines for the 2X and 4X signal groups are given below:
•Trace impedance = 50 Ω± 10%
•Route traces using 5/15 mil spacing
•Route all traces at least 25 mils away from the strobes
•Route all traces with at least 50% of the trace width directly over the reference plane for short
distances only when needed in the interposer socket region.
•Route signals and their associated strobes on the same layer for the entire length of the bus.
•A strobe and its complement must be routed within 25 mils of the same length over the entire
length of the buses.
•All 2X and 4X signals of the same group (refer to Table 5) must be routed within ±25 mils of
the same length between the agents and within ±50 mils of the entire length of the bus.
•Total bus length must not exceed 10”.
•Trace length matching is required. Please contact your Intel field representative for a length
matching spreadsheet.
Trace length matching is required within each source synchronous group to compensate for the
package trace length differences between data signals and the associated strobe. This will balance
the strobe-to-signal skew in the middle of the setup and hold window. Figure 1 shows how to
implement trace length matching. An example of trace length matching is given in Equation 1.
Table 4. 2X and 4X Signal Groups
2X Group 4X Group
HA[35:3]#
REQ[4:0]# HD[63:0]# DBI[3:0]#
Table 5. Source Synchronous Signals and Associated Strobes
Signals Associated Strobe
REQ[4:0]#, HA[16:3]# ADSTB0#
HA[35:17]# ADSTB1#
HD[15:0]#, DBI0# DSTBP0#, DSTBN0#
HD[31:16]#, DBI1# DSTBP1#, DSTBN1#
HD[47:32]#, DBI2# DSTBP2#, DSTBN2#
HD[63:48]#, DBI3# DSTBP3#, DSTBN3#

Intel®Xeon™ Processor and Intel®E7500/E7501 Chipset Compatible Platform
12 Platform Design Guide Addendum
2.1.1 Design Recommendations
Below are the design recommendations for the data, address, strobes, and common clock signals.
For the following discussion, the pad is defined as the attach point of the silicon pad to the package
substrate.
DATA:
•The pin to pin distance from the processor to the chipset should be between 3.5" to 10" (i.e.,
3.5" < L1 < 10"). Data signals of the same source synchronous group should be routed to the
same pad to pad length within ± 100 mils of the associated strobes. As a result, additional
traces will be added to some data nets on the system board in order for all trace lengths within
the same data group to be the same length (± 100 mils) from the pad of the processor to the pad
of the chipset. This length compensation will result in minimizing the source synchronous
skew that exists on the system bus. Without the length compensation the flight times between
a data signal and its strobe is different, which results in an inequity between the setup and hold
times.
Equation 1. Calculating Package Delta Addition to System Board Length for UP Systems
deltanet,strobe = (cpu_pkglennet - cpu_pkglenstrobe†) + (chipset_pkglennet - chipset_pkglenstrobe)
† Strobe package length is the average of the strobe pair.
ADDRESS:
•Address signals follow the same rules as data signals except they should be routed to the same
pad to pad length within ±200 mils of the associated strobes. Address signals may change
layers if the reference plane remains Vss and as long as the layers for a given group are all of
the same configuration (all stripline or all microstrip).
STROBE:
•A strobe and its complement should be routed to a length equal to their corresponding data
group's median pad-to-pad length ±25 mils. This causes the strobe to be received closer to the
center of the data pulse, which results in reasonably comparable setup and hold times. A strobe
and its complement (xSTBp/n#) should be routed to ±25 mils of the same length. It is
recommended to simulate skew in order to determine the length that best centers the strobe for
a given system.
COMMON CLOCK:
•Common clock signals should be routed to a minimum pin-to-pin system board length of 6"
and a maximum motherboard length of 10".

Intel®Xeon™ Processor and Intel®E7500/E7501 Chipset Compatible Platform
Platform Design Guide Addendum 13
2.2 Routing Guidelines for Common Clock Signals
Table 6 lists the common clock signals.
Routing guidelines for the source synchronous signal group are given below:
•Trace impedance = 50 Ω±10%
•Route traces using 5/15 mil spacing
•Keep signals on the same layer for the entire length of the bus
•Route traces with at least 50% of the trace width directly over a reference plane
•Total bus length must not exceed 10"
2.2.1 Wired-OR Signals
There are five wired-OR signals on the system bus. These signals are HIT#, HITM#, MCERR#,
BINIT#, and BNR#. These signals differ from the other front-side bus signals in that more than one
agent can be driving the signal at the same time. Timing and signal integrity must be met for the
case where one agent is driving, all agents are driving, or any combination of agents are driving.
The wired-OR signals should follow the same routing rules as the common clock signals. Intel
recommends that simulations for these signals be performed for a given system.
Table 6. Common Clock Signals
Signal Type Signals
AGTL+ Common Clock Input
BPRI#
BR[3:1]#
DEFER#
RESET#
RS[2:0]#
RSP#
TRDY#
AGTL+ Common Clock I/O
ADS#
AP[1:0]#
BINIT#
BNR#
BPM[5:0]#
BR0#
DBSY#
DP[3:0]#
DRDY#
HIT#
HITM#
LOCK#
MCERR#

Intel®Xeon™ Processor and Intel®E7500/E7501 Chipset Compatible Platform
14 Platform Design Guide Addendum
2.3 Routing Guidelines for Asynchronous GTL+ and
Miscellaneous Signals
This section provides routing guidelines for the signals listed in Table 7.
Table 7. Asynchronous GTL+ and Miscellaneous Signals
Signal Name Type CPU I/O Type Driven by Received by
A20M# Async GTL+ I ICH3-S Processor
BINIT# AGTL+ I/O Processor Processor
BR[3:1]# AGTL+ I Processor Processor
BR0# AGTL+ I/O Processor/MCH Processor/Chipset
COMP[1:0] Analog I Pull-down Processor
FERR# Async GTL+ O Processor Chipset
IERR# Async GTL+ O Processor External Logic
IGNNE# Async GTL+ I ICH3-S Processor
INIT# Async GTL+ I ICH3-S Processor
LINT[1:0] Async GTL+ I ICH3-S Processor
ODTEN Other I Pull-up/Pull-down Processor
PROCHOT# Async GTL+ O Processor External Logic
PWRGOOD Async GTL+ I External Logic Processor
SLP# Async GTL+ I ICH3-S Processor
SM_ALERT# SMBUS (3.3 V) O Processor/Controller Controller
SM_CLK SMBUS (3.3 V) I/O Processor/Controller Processor/Controller
SM_DAT SMBUS (3.3 V) I/O Processor/Controller Processor/Controller
SM_EP_A[2:0] SMBUS (3.3 V) I Pull-up/Pull-down Processor
SM_TS_A[1:0] SMBUS (3.3 V) I Pull-up/Pull-down Processor
SM_WP SMBUS (3.3 V) I External Logic Processor
SMI# Async GTL+ I ICH3-S Processor
STPCLK# Async GTL+ I ICH3-S Processor
THERMTRIP# Async GTL+ O Processor External Logic
VCCA Power I Pull-up/Pull-down Processor
VCCIOPLL Power I Pull-up/Pull-down Processor
VCCSENSE Other O Processor Voltage Regulator
VID[4:0] Other O Processor Voltage Regulator
GTLREF Power I Pull-up/Pull-down Processor
VSSA Power I Pull-up/Pull-down Processor

Intel®Xeon™ Processor and Intel®E7500/E7501 Chipset Compatible Platform
Platform Design Guide Addendum 15
2.3.1 Asynchronous GTL+ Signals Driven by the Processor
Follow the topology shown in Figure 2 when routing FERR#, IERR#, PROCHOT# and
THERMTRIP#. Note that FERR# is the only signal in this group that connects the processors to the
ICH3-S. IERR#, PROCHOT# and THERMTRIP# connect to other motherboard logic (such as the
Baseboard Management Controller) and may need voltage translation logic, depending on the
motherboard receiver logic devices used. Do not route a stub when routing to the processors.
2.3.1.1 Voltage Translation for FERR#
A voltage translator circuit is required for the FERR# signal when VCC_CPU is less than 1.3 V, as
it is for the Low Voltage Intel®Xeon™ Processor. The required routing topology for FERR# is
given in Figure 3. Figure 6 shows the voltage translator circuit.
Figure 2. Topology for Asynchronous GTL+ Signals Driven by the Processor
A9045-01
56Ω ± 5% 56Ω ± 5%
Processor
0
3 inches max 3 inches max1 to 12 inches
VCC_CPU
Intel®
ICH3-S
or other
Logic
Note: Trace Zo - 50Ω
Trace Spacing = 10 ml
VCC_CPU

Intel®Xeon™ Processor and Intel®E7500/E7501 Chipset Compatible Platform
16 Platform Design Guide Addendum
2.3.1.2 Proper THERMTRIP# Usage
To protect the processors from damage in over-temperature situations, power to the processor core
must be removed within 0.5 seconds of the assertion of the THERMTRIP#. If power is applied to a
processor when no thermal solution is attached, normal leaking currents causes the die temperature
to rapidly rise to levels at which permanent silicon damage is possible. This high temperature
causes THERMTRIP# to go active. Use dual termination on the THERMTRIP# signal. Each
processor’s THERMTRIP# can be routed to its own receiver, or they can be wire-OR’d together. If
routed separately, each signal must be terminated at the receiver end only. All power supply
sources to all processors must be disabled when any install processor signals THERMTRIP#. In the
reference schematic, the 74AHC74 flip-flop latches the THERMTRIP# signal HIGH after a
PWRGOOD assertion, and LOW after a THERMTRIP# assertion. The recommended
THERMTRIP# circuit is shown in Figure 1.
Figure 3. FERR# Routing Topology for Low Voltage Intel®Xeon™Processors
NOTE:
1. Refer to Figure 6 for voltage translator information.
A9046-01
56Ω56Ω
Processor
0
3 inches max 3 inches max1 to 12 inches
Voltage
Translator
(1)
ICH3-S
(FERR#)
VCC_CPU VCC_CPU
Figure 1. Recommended THERMTRIP# Circuit
A9844-01
74AHC74
VCC=3VSBY
D
Q#
Q
SET
CLR
3VSBY
VCC_CPU
THERMTRIP# THERM_EN to VR
1 KΩ10 KΩ
62 Ω3904
3904
1 KΩ
100 KΩ
3.3 KΩ
12 V
1 KΩ

Intel®Xeon™ Processor and Intel®E7500/E7501 Chipset Compatible Platform
Platform Design Guide Addendum 17
2.3.2 Asynchronous GTL+ Signals Driven by the Chipset
Follow the topology shown in Figure 4 when routing A20M#, IGNNE#, INIT#, NMI, INTR,
CPUSLP#, SMI#, STPCLK#, LINIT[1:0] and PWRGOOD.
2.3.2.1 Voltage Translation for INIT#
A voltage translator circuit is required for the INIT# signal for all platforms that use FWH. The
required routing topology for INIT# is given in Figure 5. Do not route a stub when routing to the
processors. Figure 6 shows the voltage translator circuit.
Figure 4. Topology for Asynchronous GTL+ Signals Driven by the Chipset
A9047-02
200Ω ± 5%
Processor
0
3 inches max 1 to 12 inches
ICH3-S
Note: Trace Zo - 50Ω
Trace Spacing = 10 ml
VCC_CPU

Intel®Xeon™ Processor and Intel®E7500/E7501 Chipset Compatible Platform
18 Platform Design Guide Addendum
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2.3.3 BR[3:0] Routing Guidelines for Uni-processor Designs
Connect BR[3:0] as shown in Figure 7. The total bus length must be less than 10". The agent-to-
Rpu stub must be 1" or shorter.
Note: BR3#, BR2# and BR1# are not used and pulled to VCC_CPU.
Figure 5. INIT# Routing Topology for a Uni-processor System
NOTE: 1. Refer to Figure 6 for voltage translator information.
Figure 6. Voltage Translator Circuit
A9048-01
200Ω
Processor
0
3 inches max 2 inches
max
1 to 12 inches
Intel
®
ICH3-S Voltage
Translator
(1)
FWH
VCC_CPU
From_Driver
To_Receiver
3904
3904
Vcc_of_Receiver
470 Ω
+- 5%
300 Ω
+- 5%
470 Ω
+- 5%
T1
T2
VT BOX
T1 = 10" max
T2 = 3" max
Note: T1 and T2 must be referenced to ground

Intel®Xeon™ Processor and Intel®E7500/E7501 Chipset Compatible Platform
Platform Design Guide Addendum 19
Figure 7. BR[3:0]# Connection for UP Configuration
A9049-01
Processor
0
BR0# BR1# BR2# BR3#
MCH
RTRpu
Note: Rpu = RT = 50Ω ± 5%
VCC_CPU

Intel®Xeon™ Processor and Intel®E7500/E7501 Chipset Compatible Platform
20 Platform Design Guide Addendum