Intel USB930HxADBD User manual

USB930HxADBD
Adapter Board
User’s Manual
April 1997

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obtained from:
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or call 1-800-879-4683
Copyright © INTEL CORPORATION, 1996, 1997

i
CONTENTS
CONTENTS
1.0 INTRODUCTION .............................................................................................................. 1
2.0 INSTALLATION ................................................................................................................ 1
2.1 Installing the Adapter Board .........................................................................................1
2.2 Installing the new EPROM ...........................................................................................4
3.0 BOARD LAYOUT.............................................................................................................. 5
4.0 FEATURES....................................................................................................................... 5
4.1 CPU Foot Print .............................................................................................................5
4.2 External Clock Oscillator/Crystal ..................................................................................5
4.3 Test Points ...................................................................................................................6
4.4 Jumpers .......................................................................................................................6
4.5 Evaluation Board Interface ...........................................................................................6
4.6 Serial Communications ................................................................................................6
4.6.1 Using the External Serial Port .................................................................................7
4.6.2 Using the Internal Serial Port ..................................................................................7
5.0 8X930XX ADAPTER BOARD SCHEMATICS .................................................................. 7
FIGURES
8X930 MICROCONTROLLER LOCATION ...................................................................................2
ADAPTER BOARD ORIENTATION ..............................................................................................3
EPROM ORIENTATION ...............................................................................................................4
ADAPTER BOARD LAYOUT ........................................................................................................5

1
1.0 INTRODUCTION
This manual describes how to connect the USB930HxADBD daughter card to the 8x930 Family
USB Evaluation Board Rev B. The 8x930Hx chip supports one upstream USB port and four
downstream USB ports.
NOTE
Due to pin incompatibilities, this daughter card can be used with the four-port
8x930 Family USB Evaluation Board Rev B only.
2.0 INSTALLATION
2.1 Installing the Adapter Board
1. Remove the 8x930Ax device installed on the 8x930 Family USB Evaluation Board Rev B
from the U3 socket prior to installing the adapter board. Refer to Figure 1 for the location
of socket U3
2. Place the adapter on the evaluation board, ensuring that the connectors are properly
aligned, and press the adapter onto the evaluation board until the connectors are fully
engaged. Refer to Figure 2 for the correct orientation for the adapter board.

USB930HXADBD ADAPTER BOARD USER’S GUIDE
2
Figure 1. 8x930 Microcontroller Location
8x930 Family EVAL BD REV B
UART Serial I/O
U10
U17
C1
F1
P10 P8
U18
JW22
J1J2 P9
Low
Full
VR1
GND
+5V
TP1
P7
U3
1P6
39 40
RESET
U15
JW1
SRAM Only
SOCKET A
U1
A5525-01
P12V
JW3
1
P5
49 50
TP3
2
I/O Expansion
S3 S2
S1
RP4
RP3
U8
U13U12U11
JW19
INT0
JW20
INT1
INT SOF
UPSTREAM
PORT
2
RP5
RP2
RP1
U6U5
Page
Non-Page
JW15
JW14
JW8
P5V
A12*
SOCKET B
U2
U14
U7 JW16
TP 19
TP
18
DM4
DP4
TP 17
TP
16
DM3
DP3
TP 15
TP
14
GND TP2
Port1/5
Port2
Port3
Port4
JW21
1
39 40
2
TP8
U9
+
U4
Q1
JW4
TP4
TP5
Y1
TP9
JW17
U16
TP10
TP7
TP11
JW18
JW13
JW6 JW5
JW2
JW7
TP6
Socket Justify
11
1-2 1-2 2-3 12 MHz12
1-2 2-3 2-3 6 MHz1.5
2-3 2-3 1-2 3 MHz
1.5
PLL2 PLL1 PLL0 Data Freq
(PLL1)
(PLL2)
JW12 (PLL0)
JW10
JW11
A12
JW9
TP 13
TP
12
DM2
DP2
DM1
DP1
TP
20
JW23
GND
1
GND GND
TP
21
REMOVE
microcontroller
in socket U3

3
USB930HXADBD ADAPTER BOARD USER’S GUIDE
Figure 2. Adapter Board Orientation
8x930 Family EVAL BD REV B
UART Serial I/O
U10
U17
C1
F1
P10 P8
U18
JW22
J1J2 P9
Low
Full
VR1
GND
+5V
TP1
P7
U3
1P6
39 40
RESET
U15
JW1
SRAM Only
SOCKET A
U1
A5527-01
P12V
JW3
1
P5
49 50
TP3
2
I/O Expansion
S3 S2
S1
RP4RP3
U8
U13U12U11
JW19
INT0
JW20
INT1
INT SOF
UPSTREAM
PORT
2
RP5
RP2
RP1
U6U5
Page
Non-Page
JW15
JW14
JW8
P5V
A12
*
SOCKET B
U2
U14
U7 JW16
TP 19
TP
18
DM4
DP4
TP 17
TP
16
DM3
DP3
TP 15
TP
14
GND TP2
Port1/5
Port2
Port3
Port4
JW21
1
39 40
2
TP8
U9
+
U4
Q1
JW4
TP4
TP5
Y1
TP9
JW17
U16
TP10
TP7
TP11
JW18
JW13
JW6 JW5
JW2
JW7
TP6
Socket Justify
11
1-2 1-2 2-3 12 MHz12
1-2 2-3 2-3 6 MHz1.5
2-3 2-3 1-2 3 MHz
1.5
PLL2 PLL1 PLL0 Data Freq
(PLL1)
(PLL2)
JW12 (PLL0)
JW10
JW11
A12
JW9
TP 13
TP
12
DM2
DP2
DM1
DP1
TP
20
JW23
GND
1
GND GND
TP
21
P7
P6
39 40
2
Y1
1-2 1-2 2-3 1212 1-2 2-3 2-3 61.5 2-3 2-3 1-2 31.5
PLL2 PLL1 PLL0 Data Freq
1
3940
2
1
10µ
16v
U1
U2

USB930HXADBD ADAPTER BOARD USER’S GUIDE
4
2.2 Installing the new EPROM
If an EPROM is included in the upgrade package, you must use it to replace the EPROM that is
installed in Socket A of the evaluation board. This upgraded EPROM has the same pinout as the
original, however, it contains new RISM (Reduced Instruction Set Monitor) code. No jumper
changes are required.
NOTE
Socket A can accept either a 32K, 64K, or 128K EPROM. Because of this,
when you install the 32K EPROM provided by Intel there will be four holes
left open by the notch. See Figure 3 for the correct orientation of the EPROM.
Figure 3. EPROM Orientation
8x930 Family EVAL BD REV B
SRA
SOCKET A
U1
A5528-01
P12V
JW3
1
P5
49 50
I/O Expansion
S1
RP3
U13U12
U11
JW19
INT0
JW20
INT1
INT SOF
2
RP5
RP2
RP1
U6U5
Page
Non-Page
JW15
JW14
JW8
P5V
A12
*
SOCKE
U2
U14
U7 J
TP
16
TP 15
TP
14
GND TP2
Port1/5
Port2
Port3
JW21
Socket Justify
A12
JW9
TP 13
TP
12
DM2
DP2
DM1
DP1
Leave 4 holes
by notch OPEN

5
USB930HXADBD ADAPTER BOARD USER’S GUIDE
3.0 BOARD LAYOUT
Figure 4 shows the layout of the board and the major components.
Figure 4. Adapter Board Layout
4.0 FEATURES
4.1 CPU Foot Print
The Adapter Board has the foot print for a 68-pin PLCC socket to match the pinout of the
8x930Hx.
4.2 External Clock Oscillator/Crystal
Theboardprovides space for acrystal anda capacitor touse the internal oscillatorof the 8x930Hx
and also contains a clock oscillator that produces an independent external clock source for the
8x930Hx. Only one clock source can be used at a time. By default the clock oscillator is used and
the crystal and capacitor are not populated. To use the internal oscillator, you must cut Jumper
JW1 and install the appropriate crystal and capacitor.
A5526-01
3"
3"
Top View
Side View
Interfaces to 82930
USBM Eval Board
P7
P6
39 40
2
Y1
1-2 1-2 2-3 1212
1-2 2-3 2-3 61.5
2-3 2-3 1-2 31.5
PLL2 PLL1 PLL0 Data Freq
1
39 40
2
1
10µ
16v
U2
U1

USB930HXADBD ADAPTER BOARD USER’S GUIDE
6
4.3 Test Points
The board contains test points for CLK12MHZ, XTAL2, and AVCC.
4.4 Jumpers
The board contains jumpers to allow the 8x930Hx device to be reconfigured.Three 3-pin jumpers
are used to select the core operating frequency and the USB data rate. Figure 1 illustrates jumper
configurations:
JW1 allows the clock oscillator to be disconnected from the 8x930Hx so that a crystal can be
used. To install your own crystal, you must eithercut JW1or remove theexisting clock oscillator.
NOTE
When selecting 1.5Mbps with a 3MHz core, a 6MHz crystal must be installed
on the board.
4.5 Evaluation Board Interface
The 8x930Hx Adapter Board interfaces to the 8x930 Family Evaluation. Board. Rev B through
two 40-pin female headers. The headers are surface mounted on the solder side of the board. The
interface is “duplicated” physically and electrically on the component side of the board to allow
probing access.
4.6 Serial Communications
The adapter board contains the new 8x930Hx USB chip. This device has a default start-up inter-
nal frequency of 3 MHz. You can change this frequency to 12 MHz by clearing the LC bit located
in the PCON register. You can switch back to 3 MHz by setting the LC bit. Readers are encour-
aged to consult the 8x930Ax, 8x930Hx Universal Serial Bus Microcontroller User’s Manual
(order number 272949) for more information on this subject.
Table 1. Jumper Configuration
PLL2 JW4 PLL1 JW3 PLL0 JW2 USB Data
Rate Core Frequency XTAL1
2-3 2-3 1-2 1.5 Mbps 3 MHz 6 MHz
1-2 2-3 2-3 1.5 Mbps 6 MHz 12 MHz
1-2 1-2 2-3 12 Mbps 12 MHz 12 MHz

7
USB930HXADBD ADAPTER BOARD USER’S GUIDE
The flexibility of frequency changes for power saving has a direct impact on baud rate and serial
communication. To allow debugging sessions without risk of board-PC communication loss, a
number of changes have been added to the RISM code. To establish communication between the
evaluation board and the debugger (Keil, PLC, or Tasking software) use either the external serial
link (recommended) or the internal serial link.
4.6.1 Using the External Serial Port
You are encouraged strongly to use the external serial port to communicate with the debugger
environment.When this serial port is used,the baud rate is 19200(makesure you set the debugger
software to use the same rate) and all internal timers are available. The internal serial port is then
free and can be used by your application. One interrupt (intr0), however, is used by the UART
and cannot be used. The priority should not be changed.
The external serial port is labeled “UART” on the board To enable this port, set the UARTC
switch to the “ON” position.
When using this port, you can set or clear the LC bit using the SETB and CLR instructions. There
are no restrictions to your code.
4.6.2 Using the Internal Serial Port
The use of the internal serial port to communicate with the debugger is not recommended. When
you use this serial port, the baud rate is fixed at 9600 (you must set the debugger software to use
the same rate) and timer-two is used by the RISM to generate the baud rate, making this timer
unavailable for your application. The internal serial port is no longer available since it used to
communicate with the debugger. Do not change the interrupt priority. The external interrupts,
intr0 and intr1, are both available.
When using this port, you can still set or clear the LC bit. However, you cannotuse the SETB and
CLR instructions to do. So you must use an extended call to a routine inside the RISM that sets
or clears the bit. Instead of using “SETB LC” you must use “ECALL 0FF0083” and instead of
using “CLR LC” use “ECALL 0FF008B”.
5.0 8X930XX ADAPTER BOARD SCHEMATICS
The pages that follow provide you with schematics for the adapter board. These files are also
available on the Intel World-Wide Web sit at www.intel.com.

USB930HXADBD ADAPTER BOARD USER’S GUIDE
8

1 2 3 4 56
A B C D
6
54321
D
C B A
DWG No. Rev
SheetDrawn by Date
Size
USB930HxADBD Adapter Bd.
FCSM No.
Although Intelhas verified this design to be functional, Intel assumes no responsibility for any errors which may appear in the design. Intel reserves the right to modify this design without notice.
Intel Corporation
2
CEG System EngineeringBoards and ASICs 5000 W. Chandler Blvd. Chandler, AZ 85226
0001 A
11:13:132-Apr-1997
B
HELSCON.SCH CMJ of 2
File
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
1 3 5 7 9
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
P6
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
1 3 5 7 9
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
J7
DP0 DM0 DP1 DM1 DP3 DP2 DM3 DM2
EA* ALE PSEN*
P5V P5V
RESET
P2.7 P2.6P2.5 P2.4
P2.2 P2.0
P2.3 P2.1
P0.7 P0.5 P0.6
P0.4 P0.2 P0.0
P0.3 P0.1
P3.0 P3.2 P3.4 P3.6
P3.1 P3.3 P3.5 P3.7
P1.0 P1.2 P1.4 P1.6
P1.1 P1.3 P1.5 P1.7
OVRI*
SOF*
UPWEN*
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
1 3 5 7 9
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
J6
P2.7 P2.6P2.5 P2.4
P2.2 P2.0
P2.3 P2.1
P0.7 P0.5 P0.6
P0.4 P0.2 P0.0
P0.3 P0.1
P3.0 P3.2 P3.4 P3.6
P3.1 P3.3 P3.5 P3.7
P1.0 P1.2 P1.4 P1.6
P1.1 P1.3 P1.5 P1.7
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
1 3 5 7 9
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
P7
DP0 DM0 DP1 DM1 DP3 DP2 DM3 DM2
EA* ALE PSEN*
P5V P5V
RESET
DP0 DM0 DP1 DP3 DP2 DM1 DM3 DM2 OVRI*
OVRI*
SOF*
UPWEN* UPWEN*
P5V P5V
RESET SOF* PSEN* EA* ALE
EA* ALE PSEN* SOF*
P0.[0:7] P3.[0:7] P1.[0:7] P2.[0:7]
AVCC
AVCC
AVCC AVCC
DP4 DM4 DP4
DM4
DP4 DM4

1 2 3 4 56
A B C D
6
54321
D
C B A
DWG No. Rev
SheetDrawn by Date
Size
USB930HxADBD Adapter Bd.
FCSM No.
Although Intelhas verified this design to be functional, Intel assumes no responsibility for any errors which may appear in the design. Intel reserves the right to modify this design without notice.
Intel Corporation
1
CEG System EngineeringBoards and ASICs 5000 W. Chandler Blvd. Chandler, AZ 85226
0001 A
11:13:332-Apr-1997
B
HELSSOC.SCH CMJ of 2
File
P2.[0:7] P0.[0:7]
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6
P3.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RESET
NC
1
GND
4OUT 5
VCC 8
U1
12.000 MHz
Clock Osc.
Y1
12.000 MHz
C1 30 pF C2
30 pF
P5V
1 2
JW1
P5V
CLK12MHZ
1
TP1
1
TP2
PLLSEL2
C3
0.1 uF
13
2
JW2
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
C7 1 uF
ECAP
PSEN* ALE EA* EA*
ALE PSEN*
P3.[0:7] P1.[0:7]
RESET
1
TP3
C4 0.1 uF C5
0.1 uF C6
0.1 uF
XTAL1
XTAL2
P5V
DP4 DM4 DP1 DM1 DP0 DP3 DM0 DM3 DM2 DP2
DP1 DM1 DP0 DM0 DP3 DM3 DP2 DM2
C8 10 uF
P5V
AVCC
AVCC
DP4 DM4 UPWEN*
UPWEN*
A15/P2.7 2
Vss 1
A14/P2.6 3
A13/P2.5 4
A12/P2.4 5
A11/P2.3 6
A10/P2.2 7
A9/P2.1 8
A8/P2.0 9
AD7/P0.7
10
AD6/P0.6
11
AD5/P0.5
12
AD4/P0.4
13
AD3/P0.3
14
AD2/P0.2
15
AD1/P0.1
16
AD0/P0.0
17
Vssp
18
Vccp
19
P3.0/RXD
20
P3.1/TXD
21
P3.2/INT0#
22
P3.3/INT1#
23
P3.4/T0
24
P3.5/T1
25
P3.6/WR#
26
A16/P3.7/RD#
27
P1.0/T2
28
P1.1/T2EX
29
P1.2/ECI
30
P1.3/CEX0
31
P1.4/CEX1
32
P1.5/CEX2
33
P1.6/CEX3/WAIT#
34
A17/P1.7/CEX4/WCLK
35
Vcc
36
Vss
37
XTAL1
38
XTAL2
39
AVcc
40
RESET
41
PLLSEL1
42
PLLSEL2
43
PLLSEL0 44
DM2 45
DP2 46
Reserved 47
DM3 48
DP3 49
SOF# 50
Vccp 51
Vssp 52
ECAP 53
DM0 54
DP0 55
Reserved 56
DM1 57
DP1 58
DM5 59
DP5 60
OVRI# 61
UPWEN# 62
Reserved 63
Reserved 64
PSEN# 65
ALE 66
EA# 67
Vcc 68
U2
HELSINKI
13
2
JW3
13
2
JW4
PLLSEL1
PLLSEL0
PLLSEL2 PLLSEL1 PLLSEL0 USB data rate Core frequency XTAL1 2-3 2-3 1-2 1.5 Mbps 3MHz 6MHz 1-2 2-3 2-3 1.5 Mbps 6MHz 12 MHz 1-2 1-2 2-3 12 Mbps 12 MHz 12 MHz
OVRI* OVRI*
SOF* SOF*
AVCC
C9 0.1 uF