Intel 810A3 Guide

Intel®810A3 Chipset Platform
Design Guide
July 2000
Order Number: 298186-002

Intel®810A3 Chipset Design Guide
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Copyright © Intel Corporation, 2000
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Intel®810A3 Chipset Design Guide iii
Contents
1 Introduction................................................................................................................1-1
1.1 About This Design Guide..............................................................................1-1
1.1.1 Terminology and Definitions ............................................................1-2
1.1.2 References.......................................................................................1-7
1.2 System Overview..........................................................................................1-7
1.2.1 Graphics and Memory Controller Hub (GMCH)...............................1-8
1.2.2 I/O Controller Hub (82801AA ICH)...................................................1-9
1.2.3 System Configurations.....................................................................1-9
1.3 Platform Initiatives.......................................................................................1-10
1.3.1 Hub Interface .................................................................................1-10
1.3.2 Manageability.................................................................................1-10
1.3.3 AC’97.............................................................................................1-11
1.3.4 Low Pin Count (LPC) Interface ......................................................1-12
2 PGA370 Processor Design Guidelines......................................................................2-1
2.1 Electrical Differences for Flexible PGA370 Designs.....................................2-1
2.2 PGA370 Socket Definition Details ................................................................2-2
2.2.1 Processor Pin Definition Comparison ..............................................2-3
2.2.2 Layout Guidelines for Intel®Pentium®III Processors......................2-4
2.2.3 Undershoot/Overshoot Requirements .............................................2-9
2.2.4 BSEL[1:0] Implementation for PGA370 Designs .............................2-9
2.2.5 CLKREF Circuit Implementation....................................................2-10
2.2.6 Undershoot/Overshoot Requirements ...........................................2-10
2.2.7 Connecting RESET# and RESET2# on a Flexible
PGA370 Design.............................................................................2-11
2.2.8 Reset Strapping Options................................................................2-11
2.2.9 Voltage Regulation Differences .....................................................2-12
2.2.10 Decoupling Guidelines for Flexible PGA370 Designs....................2-12
2.2.11 Thermal/EMI Differences...............................................................2-13
2.2.12 Debug Port Changes .....................................................................2-14
3 SC242 Processor Design Guidelines.........................................................................3-1
3.1 Intel®Pentium®III Processors Layout Guidelines........................................3-1
3.2 Determine General Topology and Layout.....................................................3-3
3.3 Solution Space..............................................................................................3-3
3.4 Minimizing Crosstalk.....................................................................................3-4
3.5 Motherboard Layout Rules for Non-AGTL+ (CMOS) Signals.......................3-4
3.6 THRMDP and THRMDN...............................................................................3-5
3.7 Additional Considerations.............................................................................3-5
3.8 Motherboard Frequency Select for SC242 Designs .....................................3-6
3.9 S.E.C.C. 2 Grounding Retention Mechanism (GRM)....................................3-7
3.9.1 Motherboard Interfaces....................................................................3-7
4 Layout and Routing Guidelines..................................................................................4-1
4.1 General Recommendations..........................................................................4-1
4.2 Nominal Board Stackup................................................................................4-1
4.3 Component Quadrant Layouts......................................................................4-2
4.4 Intel®810A3 Chipset Component Placement...............................................4-4

iv Intel®810A3 Chipset Design Guide
4.5 System Memory Layout Guidelines..............................................................4-5
4.5.1 System Memory Solution Space......................................................4-5
4.5.2 System Memory Routing Example...................................................4-6
4.5.3 System Memory Connectivity ..........................................................4-7
4.6 Display Cache Interface................................................................................4-7
4.6.1 Display Cache Solution Space ........................................................4-8
4.7 Hub Interface................................................................................................4-9
4.7.1 Data Signals ..................................................................................4-10
4.7.2 Strobe Signals ...............................................................................4-10
4.7.3 HREF Generation/Distribution .......................................................4-10
4.7.4 Compensation................................................................................4-11
4.8 Ultra ATA/66 ...............................................................................................4-12
4.8.1 IDE Routing Guidelines .................................................................4-12
4.8.2 Ultra ATA/66 Detection..................................................................4-15
4.9 AC’97..........................................................................................................4-18
4.9.1 Audio/Modem Riser Card (AMR)...................................................4-18
4.9.2 AC’97 Routing................................................................................4-19
4.9.3 Motherboard Implementation.........................................................4-21
4.10 USB ............................................................................................................4-22
4.11 IOAPIC (I/O Advanced Programmable Interrupt Controller).......................4-23
4.12 PCI..............................................................................................................4-24
4.13 RTC ............................................................................................................4-24
4.13.1 RTC Crystal ...................................................................................4-24
4.13.2 External Capacitors .......................................................................4-25
4.13.3 RTC Layout Considerations...........................................................4-26
4.13.4 RTC External Battery Connection..................................................4-26
4.13.5 RTC External RTCRESET Circuit..................................................4-27
4.13.6 VBIAS DC Voltage and Noise Measurements..............................4-27
4.14 Processor PLL Filter Recommendation......................................................4-28
4.14.1 Processor PLL Filter Recommendation.........................................4-28
4.14.2 Topology........................................................................................4-28
4.14.3 Filter Specification .........................................................................4-28
4.14.4 Recommendation for Intel Platforms..............................................4-30
4.14.5 Custom Solutions...........................................................................4-31
4.15 RAMDAC/Display Interface ........................................................................4-32
4.15.1 Reference Resistor (Rset) Calculation...........................................4-33
4.15.2 RAMDAC Board Design Guidelines...............................................4-33
4.16 DPLL Filter Design Guidelines....................................................................4-35
4.16.1 Filter Specification .........................................................................4-36
4.16.2 Recommended Routing/Component Placement............................4-37
4.16.3 Example LC Filter Components.....................................................4-37
5 Advanced System Bus Design ..................................................................................5-1
5.1 AGTL+ Design Guidelines............................................................................5-1
5.1.1 Initial Timing Analysis ......................................................................5-2
5.1.2 Determine General Topology, Layout, and Routing Desired...........5-3
5.1.3 Pre-Layout Simulation .....................................................................5-3
5.1.4 Place and Route Board....................................................................5-5
5.1.5 Post-Layout Simulation....................................................................5-7
5.1.6 Validation.........................................................................................5-8
5.2 Theory.........................................................................................................5-10
5.2.1 AGTL+ ...........................................................................................5-10

Intel®810A3 Chipset Design Guide v
5.2.2 Timing Requirements.....................................................................5-10
5.2.3 Cross-Talk Theory .........................................................................5-11
5.3 More Details and Insight.............................................................................5-13
5.3.1 Textbook Timing Equations ...........................................................5-13
5.3.2 Effective Impedance and Tolerance/Variation ...............................5-14
5.3.3 Power/Reference Planes, PCB Stackup, and High
Frequency Decoupling...................................................................5-14
5.3.4 Clock Routing.................................................................................5-17
5.4 Definitions of Flight Time Measurements/Corrections and Signal Quality..5-18
5.4.1 VREF Guardband............................................................................5-18
5.4.2 Ringback Levels.............................................................................5-18
5.4.3 Overdrive Region...........................................................................5-18
5.4.4 Flight Time Definition and Measurement.......................................5-19
5.5 Conclusion..................................................................................................5-19
6 Clocking.....................................................................................................................6-1
6.1 Clock Generation..........................................................................................6-1
6.2 Clock Architecture.........................................................................................6-2
6.3 Clock Routing Guidelines..............................................................................6-3
6.4 Capacitor Sites..............................................................................................6-6
6.5 Clock Power Decoupling Guidelines.............................................................6-6
7 System Design Considerations..................................................................................7-1
7.1 Power Delivery..............................................................................................7-1
7.1.1 Intel®810A3 Chipset Power Delivery ..............................................7-1
7.1.2 LED Indicator for S0-S5 States........................................................7-5
7.2 Decoupling Guidelines..................................................................................7-6
7.2.1 VccCORE Decoupling........................................................................7-6
7.2.2 Phase Lock Loop (PLL) Decoupling ................................................7-6
7.2.3 82810A3 GMCH Decoupling Guidelines..........................................7-7
7.2.4 Ground FloodPlanes........................................................................7-8
7.3 Thermal Design Power .................................................................................7-8
7.4 Power Sequencing........................................................................................7-9
8 Design Checklist........................................................................................................8-1
8.1 Design Review Checklist ..............................................................................8-1
8.1.1 Design Checklist Summary..............................................................8-1
8.2 Pullup and Pulldown Resistor Values.........................................................8-15
8.3 RTC.............................................................................................................8-16
8.4 Power Management Signals.......................................................................8-16
8.4.1 Power Button Implementation........................................................8-18
9 Third-Party Vendor Information..................................................................................9-1
A PCI Devices/Functions/Registers/Interrupts.............................................................A-1

vi Intel®810A3 Chipset Design Guide
Figures
1-1 Intel®810A3 Chipset ....................................................................................1-9
1-2 AC'97 with Audio and Modem Codec Connections....................................1-12
2-1 Topology for 370-Pin Socket Designs with Single Ended
Termination (SET) ........................................................................................2-6
2-2 Routing for THRMDP and THRMDN ............................................................2-8
2-3 BSEL[1:0] Circuit Implementation for PGA370 Designs...............................2-9
2-4 Examples for CLKREF Divider Circuit ........................................................2-10
2-5 RESET# Schematic for PGA370 Designs ..................................................2-11
2-6 Capacitor Placement on the Motherboard..................................................2-12
2-7 TAP Connector Comparison.......................................................................2-14
3-1 Intel®Pentium®III Uni-Processor Configuration ..........................................3-3
3-2 Routing for THRMDP and THRMDN ............................................................3-5
3-3 System Bus Frequency Selection Topology for SC242................................3-6
3-4 Hole Locations and Keep-out Zones for Support Components....................3-7
3-5 Detailed Drawing of Minimum Ground Pad Size and Location.....................3-8
4-1 Nominal Board Stackup................................................................................4-2
4-2 GMCH Quadrant Layout (topview) ...............................................................4-2
4-3 ICH 241-uBGA Quadrant Layout (topview) ..................................................4-3
4-4 uATX Placement Example for PGA370 Processors.....................................4-4
4-5 System Memory Topologies.........................................................................4-5
4-6 System Memory Routing Example ...............................................................4-6
4-7 System Memory Connectivity .......................................................................4-7
4-8 Display Cache (Topology 1) .........................................................................4-7
4-9 Display Cache (Topology 2) .........................................................................4-8
4-10 Display Cache (Topology 3) .........................................................................4-8
4-11 Display Cache (Topology 4) .........................................................................4-9
4-12 Hub Interface Signal Routing Example.........................................................4-9
4-13 Single Hub Interface Reference Divider Circuit ..........................................4-11
4-14 Locally Generated Hub Interface Reference Dividers ................................4-11
4-15 IDE Min/Max Routing and Cable Lengths...................................................4-12
4-16 Ultra ATA/66 Cable.....................................................................................4-13
4-17 Resistor Schematic for Primary IDE Connectors........................................4-14
4-18 Resistor Schematic for Secondary IDE Connectors...................................4-14
4-19 Host-Side IDE Cable Detection ..................................................................4-16
4-20 Host-Side IDE Cable Detection ..................................................................4-17
4-21 Host-Side IDE Cable Detection ..................................................................4-17
4-22 Tee Topology AC'97 Trace Length Requirements for ATX ........................4-20
4-23 Daisy-Chain Topology AC'97 Trace Length Requirements for ATX...........4-20
4-24 USB Data Signals.......................................................................................4-23
4-25 PCI Bus Layout Example for 4 PCI Connectors.........................................4-24
4-26 External Circuitry for the ICH RTC..............................................................4-25
4-27 A Diode Circuit to Connect RTC External Battery ......................................4-26
4-28 RTCRESET External Circuit for the ICH RTC ............................................4-27
4-29 Filter Topology............................................................................................4-28
4-30 Filter Specification ......................................................................................4-29
4-31 Using Discrete R.........................................................................................4-30
4-32 No Discrete R .............................................................................................4-31
4-33 Core Reference Model................................................................................4-31
4-34 Schematic of RAMDAC Video Interface .....................................................4-32

Intel®810A3 Chipset Design Guide vii
4-35 RAMDAC Component and Routing Guidelines ..........................................4-34
4-36 Recommended RAMDAC Reference Resistor Placement and
Connections................................................................................................4-35
4-37 Recommended LC Filter Connection..........................................................4-36
4-38 Frequency Response (see Table 4-13).......................................................4-38
5-1 PICD[1,0] Uni-Processor Topology...............................................................5-7
5-2 Test Load vs. Actual System Load ...............................................................5-9
5-3 Aggressor and Victim Networks..................................................................5-11
5-4 Transmission Line Geometry: (A) Microstrip (B) Stripline...........................5-11
5-5 One Signal Layer and One Reference Plane..............................................5-15
5-6 Layer Switch with One Reference Plane ....................................................5-15
5-7 Layer Switch with Multiple Reference Planes (same type).........................5-15
5-8 Layer Switch with Multiple Reference Planes.............................................5-16
5-9 One Layer with Multiple Reference Planes.................................................5-16
5-10 Overdrive Region and VREF Guardband.....................................................5-19
5-11 Rising Edge Flight Time Measurement.......................................................5-19
6-1 Intel®810A3 Chipset Clock Architecture ......................................................6-2
6-2 Different Topologies for the Clock Routing Guidelines .................................6-5
6-3 Example of Capacitor Placement Near Clock Input Receiver.......................6-6
7-1 Intel®810A3 Chipset Power Delivery Architecture.......................................7-2
7-2 82810A3 GMCH Power Plane Decoupling...................................................7-8
7-3 G3-S0 Transistion.........................................................................................7-9
7-4 S0-S3-S0 Transition....................................................................................7-10
7-5 S0-S5-S0 Transition....................................................................................7-11
8-1 Pullup Resistor Example.............................................................................8-15
8-2 PWRGOOD and PWROK Logic .................................................................8-17

viii Intel®810A3 Chipset Design Guide
Tables
2-1 Platform Pin Definition Comparison for Single Processor Designs ..............2-2
2-2 Processor Pin Definition Comparison...........................................................2-3
2-3 Intel®Pentium®III Processor and GMCH AGTL+ Parameters for
Example Calculations ...................................................................................2-4
2-4 Example TFLT_MIN Calculations FOR 100 MHz Bus.....................................2-5
2-5 Example TFLT_MIN Calculations (Frequency Independent)...........................2-5
2-6 Segment Descriptions and Lengths for Figure 2-1 .......................................2-6
2-7 Trace Width (Space Guidelines)...................................................................2-6
2-8 Routing Guidelines for Non-AGTL+ Signals.................................................2-8
2-9 Example Resistor Values for CLKREF Divider Circuit (3.3V Source).........2-10
3-1 Intel®Pentium®III Processor and GMCH AGTL+ Parameters for
Example Calculations ...................................................................................3-1
3-2 Example TFLT_MAX Calculations for 100 MHz Bus .......................................3-2
3-3 Example TFLT_MIN Calculations (Frequency Independent)...........................3-2
3-4 Segment Descriptions and Lengths for Figure 3-2 ......................................3-3
3-5 Trace Width:Space Guidelines .....................................................................3-3
3-6 Routing Guidelines for Non-AGTL+ Signals.................................................3-4
4-1 System Memory Routing ..............................................................................4-5
4-2 Display Cache Routing (Topology 1)............................................................4-8
4-3 Display Cache Routing (Topology 2)............................................................4-8
4-4 Display Cache Routing (Topology 3)............................................................4-8
4-5 Display Cache Routing (Topology 4)............................................................4-9
4-6 AC’97 Configuration Combinations.............................................................4-18
4-7 Recommended USB Trace Characteristics................................................4-23
4-8 Inductor.......................................................................................................4-30
4-9 Capacitor ....................................................................................................4-30
4-10 Resistor.......................................................................................................4-30
4-11 DPLL LC Filter Component Example..........................................................4-37
4-12 Additional DPLL LC Filter Component Example.........................................4-38
4-13 Resistance Values for Frequency Response Curves (see Figure 4-38).....4-39
5-1 Trace Width Space Guidelines.....................................................................5-6
5-2 Host Clock Routing.......................................................................................5-6
6-1 Intel®810A3 Chipset Clocks.........................................................................6-1
6-2 Group Skew and Jitter Limits at the Pins of the Clock Chip .........................6-3
6-3 Signal Group and Resistor............................................................................6-3
6-4 Layout Dimensions .......................................................................................6-4
7-1 Intel®810A3 Chipset Power Map.................................................................7-3
7-2 Intel®810A3 Chipset Voltage Regulator Specifications ...............................7-4
7-3 Power Sequencing Timing Definitions........................................................7-12
8-1 AGTL+ Connectivity Checklist for 370-Pin Socket Processors.....................8-2
8-2 CMOS Connectivity Checklist for 370-Pin Socket Processors.....................8-3
8-3 TAP Checklist for a 370-Pin Socket Processor ...........................................8-3
8-4 Miscellaneous Checklist for 370-Pin Socket Processors..............................8-4
8-5 AGTL+ Connectivity Checklist for SC242 Processors..................................8-5
8-6 CMOS Connectivity Checklist for SC242 Processors...................................8-6
8-7 TAP Checklist for SC242 Processors...........................................................8-6
8-8 Miscellaneous Checklist for SC242 Processors...........................................8-6
8-9 Special Consideration Checklist...................................................................8-7
8-10 Clock Generator Checklist............................................................................8-7

Intel®810A3 Chipset Design Guide ix
8-11 ICH Checklist................................................................................................8-8
8-12 ICH Checklist................................................................................................8-9
8-13 GMCH Checklist .........................................................................................8-10
8-14 System Memory Checklist ..........................................................................8-10
8-15 Display Cache Checklist.............................................................................8-11
8-16 LPC Super I/O Checklist.............................................................................8-11
8-17 IDE Checklist ..............................................................................................8-11
8-18 Clock Generator Checklist..........................................................................8-12
8-19 FWH Flash BIOS Checklist.........................................................................8-12
8-20 PCI Bus Checklist.......................................................................................8-12
8-21 USB / Keyboard / Mouse Checklist.............................................................8-13
8-22 AC’97 Checklist...........................................................................................8-13
8-23 Power Delivery Checklist............................................................................8-14
9-1 Super I/O.......................................................................................................9-1
9-2 Clock Generation..........................................................................................9-1
9-3 Memory Vendors...........................................................................................9-1
9-4 Voltage Regulator Vendors...........................................................................9-1
9-5 Flat Panel......................................................................................................9-1
9-6 TV-Out ..........................................................................................................9-2
9-7 Software DVD...............................................................................................9-2
9-8 AC’97............................................................................................................9-2
9-9 TMDS Transmitters.......................................................................................9-3
9-10 TV Encoders.................................................................................................9-3
9-11 Combo TMDS Transmitters/TV Encoders ....................................................9-3
9-12 LVDS Transmitter .........................................................................................9-3
A-1 PCI Devices and Functions..........................................................................A-1
A-2 PCI Devices and Registers..........................................................................A-1
A-3 PCI Devices and Interrupts..........................................................................A-2

xIntel®810A3 Chipset Design Guide
Revision History
Revision Description Date
001 Initial Release April 2000
002 •Minor edits throughout for clarity
•Added Section 7.2.4, Ground Flood Plane July 2000