Intel 810A3 Guide

Intel®810A3 Chipset Platform
Design Guide
July 2000
Order Number: 298186-002

Intel®810A3 Chipset Design Guide
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
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Intel may make changes to specifications and product descriptions at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
The Intel®810A3 Chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.
Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and
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Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by:
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Copyright © Intel Corporation, 2000
*Third-party brands and names are the property of their respective owners.

Intel®810A3 Chipset Design Guide iii
Contents
1 Introduction................................................................................................................1-1
1.1 About This Design Guide..............................................................................1-1
1.1.1 Terminology and Definitions ............................................................1-2
1.1.2 References.......................................................................................1-7
1.2 System Overview..........................................................................................1-7
1.2.1 Graphics and Memory Controller Hub (GMCH)...............................1-8
1.2.2 I/O Controller Hub (82801AA ICH)...................................................1-9
1.2.3 System Configurations.....................................................................1-9
1.3 Platform Initiatives.......................................................................................1-10
1.3.1 Hub Interface .................................................................................1-10
1.3.2 Manageability.................................................................................1-10
1.3.3 AC’97.............................................................................................1-11
1.3.4 Low Pin Count (LPC) Interface ......................................................1-12
2 PGA370 Processor Design Guidelines......................................................................2-1
2.1 Electrical Differences for Flexible PGA370 Designs.....................................2-1
2.2 PGA370 Socket Definition Details ................................................................2-2
2.2.1 Processor Pin Definition Comparison ..............................................2-3
2.2.2 Layout Guidelines for Intel®Pentium®III Processors......................2-4
2.2.3 Undershoot/Overshoot Requirements .............................................2-9
2.2.4 BSEL[1:0] Implementation for PGA370 Designs .............................2-9
2.2.5 CLKREF Circuit Implementation....................................................2-10
2.2.6 Undershoot/Overshoot Requirements ...........................................2-10
2.2.7 Connecting RESET# and RESET2# on a Flexible
PGA370 Design.............................................................................2-11
2.2.8 Reset Strapping Options................................................................2-11
2.2.9 Voltage Regulation Differences .....................................................2-12
2.2.10 Decoupling Guidelines for Flexible PGA370 Designs....................2-12
2.2.11 Thermal/EMI Differences...............................................................2-13
2.2.12 Debug Port Changes .....................................................................2-14
3 SC242 Processor Design Guidelines.........................................................................3-1
3.1 Intel®Pentium®III Processors Layout Guidelines........................................3-1
3.2 Determine General Topology and Layout.....................................................3-3
3.3 Solution Space..............................................................................................3-3
3.4 Minimizing Crosstalk.....................................................................................3-4
3.5 Motherboard Layout Rules for Non-AGTL+ (CMOS) Signals.......................3-4
3.6 THRMDP and THRMDN...............................................................................3-5
3.7 Additional Considerations.............................................................................3-5
3.8 Motherboard Frequency Select for SC242 Designs .....................................3-6
3.9 S.E.C.C. 2 Grounding Retention Mechanism (GRM)....................................3-7
3.9.1 Motherboard Interfaces....................................................................3-7
4 Layout and Routing Guidelines..................................................................................4-1
4.1 General Recommendations..........................................................................4-1
4.2 Nominal Board Stackup................................................................................4-1
4.3 Component Quadrant Layouts......................................................................4-2
4.4 Intel®810A3 Chipset Component Placement...............................................4-4

iv Intel®810A3 Chipset Design Guide
4.5 System Memory Layout Guidelines..............................................................4-5
4.5.1 System Memory Solution Space......................................................4-5
4.5.2 System Memory Routing Example...................................................4-6
4.5.3 System Memory Connectivity ..........................................................4-7
4.6 Display Cache Interface................................................................................4-7
4.6.1 Display Cache Solution Space ........................................................4-8
4.7 Hub Interface................................................................................................4-9
4.7.1 Data Signals ..................................................................................4-10
4.7.2 Strobe Signals ...............................................................................4-10
4.7.3 HREF Generation/Distribution .......................................................4-10
4.7.4 Compensation................................................................................4-11
4.8 Ultra ATA/66 ...............................................................................................4-12
4.8.1 IDE Routing Guidelines .................................................................4-12
4.8.2 Ultra ATA/66 Detection..................................................................4-15
4.9 AC’97..........................................................................................................4-18
4.9.1 Audio/Modem Riser Card (AMR)...................................................4-18
4.9.2 AC’97 Routing................................................................................4-19
4.9.3 Motherboard Implementation.........................................................4-21
4.10 USB ............................................................................................................4-22
4.11 IOAPIC (I/O Advanced Programmable Interrupt Controller).......................4-23
4.12 PCI..............................................................................................................4-24
4.13 RTC ............................................................................................................4-24
4.13.1 RTC Crystal ...................................................................................4-24
4.13.2 External Capacitors .......................................................................4-25
4.13.3 RTC Layout Considerations...........................................................4-26
4.13.4 RTC External Battery Connection..................................................4-26
4.13.5 RTC External RTCRESET Circuit..................................................4-27
4.13.6 VBIAS DC Voltage and Noise Measurements..............................4-27
4.14 Processor PLL Filter Recommendation......................................................4-28
4.14.1 Processor PLL Filter Recommendation.........................................4-28
4.14.2 Topology........................................................................................4-28
4.14.3 Filter Specification .........................................................................4-28
4.14.4 Recommendation for Intel Platforms..............................................4-30
4.14.5 Custom Solutions...........................................................................4-31
4.15 RAMDAC/Display Interface ........................................................................4-32
4.15.1 Reference Resistor (Rset) Calculation...........................................4-33
4.15.2 RAMDAC Board Design Guidelines...............................................4-33
4.16 DPLL Filter Design Guidelines....................................................................4-35
4.16.1 Filter Specification .........................................................................4-36
4.16.2 Recommended Routing/Component Placement............................4-37
4.16.3 Example LC Filter Components.....................................................4-37
5 Advanced System Bus Design ..................................................................................5-1
5.1 AGTL+ Design Guidelines............................................................................5-1
5.1.1 Initial Timing Analysis ......................................................................5-2
5.1.2 Determine General Topology, Layout, and Routing Desired...........5-3
5.1.3 Pre-Layout Simulation .....................................................................5-3
5.1.4 Place and Route Board....................................................................5-5
5.1.5 Post-Layout Simulation....................................................................5-7
5.1.6 Validation.........................................................................................5-8
5.2 Theory.........................................................................................................5-10
5.2.1 AGTL+ ...........................................................................................5-10

Intel®810A3 Chipset Design Guide v
5.2.2 Timing Requirements.....................................................................5-10
5.2.3 Cross-Talk Theory .........................................................................5-11
5.3 More Details and Insight.............................................................................5-13
5.3.1 Textbook Timing Equations ...........................................................5-13
5.3.2 Effective Impedance and Tolerance/Variation ...............................5-14
5.3.3 Power/Reference Planes, PCB Stackup, and High
Frequency Decoupling...................................................................5-14
5.3.4 Clock Routing.................................................................................5-17
5.4 Definitions of Flight Time Measurements/Corrections and Signal Quality..5-18
5.4.1 VREF Guardband............................................................................5-18
5.4.2 Ringback Levels.............................................................................5-18
5.4.3 Overdrive Region...........................................................................5-18
5.4.4 Flight Time Definition and Measurement.......................................5-19
5.5 Conclusion..................................................................................................5-19
6 Clocking.....................................................................................................................6-1
6.1 Clock Generation..........................................................................................6-1
6.2 Clock Architecture.........................................................................................6-2
6.3 Clock Routing Guidelines..............................................................................6-3
6.4 Capacitor Sites..............................................................................................6-6
6.5 Clock Power Decoupling Guidelines.............................................................6-6
7 System Design Considerations..................................................................................7-1
7.1 Power Delivery..............................................................................................7-1
7.1.1 Intel®810A3 Chipset Power Delivery ..............................................7-1
7.1.2 LED Indicator for S0-S5 States........................................................7-5
7.2 Decoupling Guidelines..................................................................................7-6
7.2.1 VccCORE Decoupling........................................................................7-6
7.2.2 Phase Lock Loop (PLL) Decoupling ................................................7-6
7.2.3 82810A3 GMCH Decoupling Guidelines..........................................7-7
7.2.4 Ground FloodPlanes........................................................................7-8
7.3 Thermal Design Power .................................................................................7-8
7.4 Power Sequencing........................................................................................7-9
8 Design Checklist........................................................................................................8-1
8.1 Design Review Checklist ..............................................................................8-1
8.1.1 Design Checklist Summary..............................................................8-1
8.2 Pullup and Pulldown Resistor Values.........................................................8-15
8.3 RTC.............................................................................................................8-16
8.4 Power Management Signals.......................................................................8-16
8.4.1 Power Button Implementation........................................................8-18
9 Third-Party Vendor Information..................................................................................9-1
A PCI Devices/Functions/Registers/Interrupts.............................................................A-1

vi Intel®810A3 Chipset Design Guide
Figures
1-1 Intel®810A3 Chipset ....................................................................................1-9
1-2 AC'97 with Audio and Modem Codec Connections....................................1-12
2-1 Topology for 370-Pin Socket Designs with Single Ended
Termination (SET) ........................................................................................2-6
2-2 Routing for THRMDP and THRMDN ............................................................2-8
2-3 BSEL[1:0] Circuit Implementation for PGA370 Designs...............................2-9
2-4 Examples for CLKREF Divider Circuit ........................................................2-10
2-5 RESET# Schematic for PGA370 Designs ..................................................2-11
2-6 Capacitor Placement on the Motherboard..................................................2-12
2-7 TAP Connector Comparison.......................................................................2-14
3-1 Intel®Pentium®III Uni-Processor Configuration ..........................................3-3
3-2 Routing for THRMDP and THRMDN ............................................................3-5
3-3 System Bus Frequency Selection Topology for SC242................................3-6
3-4 Hole Locations and Keep-out Zones for Support Components....................3-7
3-5 Detailed Drawing of Minimum Ground Pad Size and Location.....................3-8
4-1 Nominal Board Stackup................................................................................4-2
4-2 GMCH Quadrant Layout (topview) ...............................................................4-2
4-3 ICH 241-uBGA Quadrant Layout (topview) ..................................................4-3
4-4 uATX Placement Example for PGA370 Processors.....................................4-4
4-5 System Memory Topologies.........................................................................4-5
4-6 System Memory Routing Example ...............................................................4-6
4-7 System Memory Connectivity .......................................................................4-7
4-8 Display Cache (Topology 1) .........................................................................4-7
4-9 Display Cache (Topology 2) .........................................................................4-8
4-10 Display Cache (Topology 3) .........................................................................4-8
4-11 Display Cache (Topology 4) .........................................................................4-9
4-12 Hub Interface Signal Routing Example.........................................................4-9
4-13 Single Hub Interface Reference Divider Circuit ..........................................4-11
4-14 Locally Generated Hub Interface Reference Dividers ................................4-11
4-15 IDE Min/Max Routing and Cable Lengths...................................................4-12
4-16 Ultra ATA/66 Cable.....................................................................................4-13
4-17 Resistor Schematic for Primary IDE Connectors........................................4-14
4-18 Resistor Schematic for Secondary IDE Connectors...................................4-14
4-19 Host-Side IDE Cable Detection ..................................................................4-16
4-20 Host-Side IDE Cable Detection ..................................................................4-17
4-21 Host-Side IDE Cable Detection ..................................................................4-17
4-22 Tee Topology AC'97 Trace Length Requirements for ATX ........................4-20
4-23 Daisy-Chain Topology AC'97 Trace Length Requirements for ATX...........4-20
4-24 USB Data Signals.......................................................................................4-23
4-25 PCI Bus Layout Example for 4 PCI Connectors.........................................4-24
4-26 External Circuitry for the ICH RTC..............................................................4-25
4-27 A Diode Circuit to Connect RTC External Battery ......................................4-26
4-28 RTCRESET External Circuit for the ICH RTC ............................................4-27
4-29 Filter Topology............................................................................................4-28
4-30 Filter Specification ......................................................................................4-29
4-31 Using Discrete R.........................................................................................4-30
4-32 No Discrete R .............................................................................................4-31
4-33 Core Reference Model................................................................................4-31
4-34 Schematic of RAMDAC Video Interface .....................................................4-32

Intel®810A3 Chipset Design Guide vii
4-35 RAMDAC Component and Routing Guidelines ..........................................4-34
4-36 Recommended RAMDAC Reference Resistor Placement and
Connections................................................................................................4-35
4-37 Recommended LC Filter Connection..........................................................4-36
4-38 Frequency Response (see Table 4-13).......................................................4-38
5-1 PICD[1,0] Uni-Processor Topology...............................................................5-7
5-2 Test Load vs. Actual System Load ...............................................................5-9
5-3 Aggressor and Victim Networks..................................................................5-11
5-4 Transmission Line Geometry: (A) Microstrip (B) Stripline...........................5-11
5-5 One Signal Layer and One Reference Plane..............................................5-15
5-6 Layer Switch with One Reference Plane ....................................................5-15
5-7 Layer Switch with Multiple Reference Planes (same type).........................5-15
5-8 Layer Switch with Multiple Reference Planes.............................................5-16
5-9 One Layer with Multiple Reference Planes.................................................5-16
5-10 Overdrive Region and VREF Guardband.....................................................5-19
5-11 Rising Edge Flight Time Measurement.......................................................5-19
6-1 Intel®810A3 Chipset Clock Architecture ......................................................6-2
6-2 Different Topologies for the Clock Routing Guidelines .................................6-5
6-3 Example of Capacitor Placement Near Clock Input Receiver.......................6-6
7-1 Intel®810A3 Chipset Power Delivery Architecture.......................................7-2
7-2 82810A3 GMCH Power Plane Decoupling...................................................7-8
7-3 G3-S0 Transistion.........................................................................................7-9
7-4 S0-S3-S0 Transition....................................................................................7-10
7-5 S0-S5-S0 Transition....................................................................................7-11
8-1 Pullup Resistor Example.............................................................................8-15
8-2 PWRGOOD and PWROK Logic .................................................................8-17

viii Intel®810A3 Chipset Design Guide
Tables
2-1 Platform Pin Definition Comparison for Single Processor Designs ..............2-2
2-2 Processor Pin Definition Comparison...........................................................2-3
2-3 Intel®Pentium®III Processor and GMCH AGTL+ Parameters for
Example Calculations ...................................................................................2-4
2-4 Example TFLT_MIN Calculations FOR 100 MHz Bus.....................................2-5
2-5 Example TFLT_MIN Calculations (Frequency Independent)...........................2-5
2-6 Segment Descriptions and Lengths for Figure 2-1 .......................................2-6
2-7 Trace Width (Space Guidelines)...................................................................2-6
2-8 Routing Guidelines for Non-AGTL+ Signals.................................................2-8
2-9 Example Resistor Values for CLKREF Divider Circuit (3.3V Source).........2-10
3-1 Intel®Pentium®III Processor and GMCH AGTL+ Parameters for
Example Calculations ...................................................................................3-1
3-2 Example TFLT_MAX Calculations for 100 MHz Bus .......................................3-2
3-3 Example TFLT_MIN Calculations (Frequency Independent)...........................3-2
3-4 Segment Descriptions and Lengths for Figure 3-2 ......................................3-3
3-5 Trace Width:Space Guidelines .....................................................................3-3
3-6 Routing Guidelines for Non-AGTL+ Signals.................................................3-4
4-1 System Memory Routing ..............................................................................4-5
4-2 Display Cache Routing (Topology 1)............................................................4-8
4-3 Display Cache Routing (Topology 2)............................................................4-8
4-4 Display Cache Routing (Topology 3)............................................................4-8
4-5 Display Cache Routing (Topology 4)............................................................4-9
4-6 AC’97 Configuration Combinations.............................................................4-18
4-7 Recommended USB Trace Characteristics................................................4-23
4-8 Inductor.......................................................................................................4-30
4-9 Capacitor ....................................................................................................4-30
4-10 Resistor.......................................................................................................4-30
4-11 DPLL LC Filter Component Example..........................................................4-37
4-12 Additional DPLL LC Filter Component Example.........................................4-38
4-13 Resistance Values for Frequency Response Curves (see Figure 4-38).....4-39
5-1 Trace Width Space Guidelines.....................................................................5-6
5-2 Host Clock Routing.......................................................................................5-6
6-1 Intel®810A3 Chipset Clocks.........................................................................6-1
6-2 Group Skew and Jitter Limits at the Pins of the Clock Chip .........................6-3
6-3 Signal Group and Resistor............................................................................6-3
6-4 Layout Dimensions .......................................................................................6-4
7-1 Intel®810A3 Chipset Power Map.................................................................7-3
7-2 Intel®810A3 Chipset Voltage Regulator Specifications ...............................7-4
7-3 Power Sequencing Timing Definitions........................................................7-12
8-1 AGTL+ Connectivity Checklist for 370-Pin Socket Processors.....................8-2
8-2 CMOS Connectivity Checklist for 370-Pin Socket Processors.....................8-3
8-3 TAP Checklist for a 370-Pin Socket Processor ...........................................8-3
8-4 Miscellaneous Checklist for 370-Pin Socket Processors..............................8-4
8-5 AGTL+ Connectivity Checklist for SC242 Processors..................................8-5
8-6 CMOS Connectivity Checklist for SC242 Processors...................................8-6
8-7 TAP Checklist for SC242 Processors...........................................................8-6
8-8 Miscellaneous Checklist for SC242 Processors...........................................8-6
8-9 Special Consideration Checklist...................................................................8-7
8-10 Clock Generator Checklist............................................................................8-7

Intel®810A3 Chipset Design Guide ix
8-11 ICH Checklist................................................................................................8-8
8-12 ICH Checklist................................................................................................8-9
8-13 GMCH Checklist .........................................................................................8-10
8-14 System Memory Checklist ..........................................................................8-10
8-15 Display Cache Checklist.............................................................................8-11
8-16 LPC Super I/O Checklist.............................................................................8-11
8-17 IDE Checklist ..............................................................................................8-11
8-18 Clock Generator Checklist..........................................................................8-12
8-19 FWH Flash BIOS Checklist.........................................................................8-12
8-20 PCI Bus Checklist.......................................................................................8-12
8-21 USB / Keyboard / Mouse Checklist.............................................................8-13
8-22 AC’97 Checklist...........................................................................................8-13
8-23 Power Delivery Checklist............................................................................8-14
9-1 Super I/O.......................................................................................................9-1
9-2 Clock Generation..........................................................................................9-1
9-3 Memory Vendors...........................................................................................9-1
9-4 Voltage Regulator Vendors...........................................................................9-1
9-5 Flat Panel......................................................................................................9-1
9-6 TV-Out ..........................................................................................................9-2
9-7 Software DVD...............................................................................................9-2
9-8 AC’97............................................................................................................9-2
9-9 TMDS Transmitters.......................................................................................9-3
9-10 TV Encoders.................................................................................................9-3
9-11 Combo TMDS Transmitters/TV Encoders ....................................................9-3
9-12 LVDS Transmitter .........................................................................................9-3
A-1 PCI Devices and Functions..........................................................................A-1
A-2 PCI Devices and Registers..........................................................................A-1
A-3 PCI Devices and Interrupts..........................................................................A-2

xIntel®810A3 Chipset Design Guide
Revision History
Revision Description Date
001 Initial Release April 2000
002 •Minor edits throughout for clarity
•Added Section 7.2.4, Ground Flood Plane July 2000

1
Introduction

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Intel®810A3 Chipset Design Guide 1-1
Introduction
Introduction 1
This design guide provides motherboard design guidelines for Intel810A3 chipset systems.
These design guidelines have been developed to ensure maximum flexibility for board designers
while reducing the risk of board related issues. In addition to design guidelines, this document
discusses Intel810A3 chipset system design issues (e.g., thermal requirements).
The debug recommendations should be consulted when debugging an Intel810A3 chipset
system; however, the debug recommendations should be understood before completing board
design to ensure that the debug port, in addition to other debug features, will be implemented
correctly.
•Please note these earlier design guides are still current:
Intel®810 Chipset Design Guide, order number 290657, references the Intel®82810A2
chipset device for Intel®Celeron™ processor 66 MHz Front Side Bus designs.
Intel®810E Chipset Platform Design Guide, order number 290675, references the Intel®
82810E chipset device for the Intel®Pentium®III processor 100 MHz / 133 MHz Front Side
Bus designs.
1.1 About This Design Guide
This design guide is intended for hardware designers who are experienced with PC architectures
and board design. The design guide assumes that the designer has a working knowledge of the
vocabulary and practices of PC hardware design.
•Chapter 1, “Introduction”—This chapter introduces the designer to the organization and
purpose of this design guide, and provides a list of references of related documents. This
chapter also provides an overview of the Intel®810A3 chipset.
•Chapter 2, “PGA370 Processor Design Guidelines”—This chapter provides design guidelines
for the PGA370 processor including processor-specific layout guidelines.
•Chapter 3, “SC242 Processor Design Guidelines”—This chapter provides design guidelines
for the SC242 processor including processor-specific layout guidelines.
•Chapter 4, “Layout and Routing Guidelines”—This chapter provides a detailed set of
motherboard layout and routing guidelines, except for processor-specific layout guidelines.
The motherboard functional units are covered (e.g., chipset component placement, system bus
routing, system memory layout, display cache interface, hub interface, IDE, AC’97, USB,
interrupts, SMBUS, PCD, LPC/FWH Flash BIOS, and RTC). For the PGA370 processor
specific layout guidelines, refer to Chapter 2, “PGA370 Processor Design Guidelines”. For the
SC242 processor spcific layout guidelines, refer to Chapter 3, “SC242 Processor Design
Guidelines”.
•Chapter 5, “Advanced System Bus Design”—The goal of this chapter is to provide the system
designer with the information needed for the implementation of 133 MHz and 100 MHz
AGTL+ bus PCB layout.
•Chapter 6, “Clocking”— This chapter provides motherboard clocking guidelines (e.g., clock
architecture, routing, capacitor sites, clock power decoupling, and clock skew).
•Chapter 7, “System Design Considerations”— This chapter includes guidelines regarding
power deliver, decoupling, thermal, and power sequencing.
•Chapter 8, “Design Checklist”— This chapter provides a design review checklist. ATA/66
detection, calculation of pullup/pulldown resistors, minimizing RTC ESD, and power
management signals are also discussed.

Introduction
1-2 Intel®810A3 Chipset Design Guide
•Chapter 9, “Third-Party Vendor Information”—This chapter includes information regarding
various third-party vendors who provide products to support the Intel®810A3 chipset.
•Appendix A, “PCI Devices/Functions/Registers/Interrupts”—This appendix lists the PCI
devices and functions supported by the Intel®810A3 chipset. Also included are a list of
component PCI Vendor ID, Device ID, Revision ID, Class code, Sub-class code, and
Programming Interface code values. In addition, component APIC interrupt and ISA/PCI
IRQs are listed.
1.1.1 Terminology and Definitions
Term Definition
Aggressor A network that transmits a coupled signal to another network is called
the aggressor network.
AGTL+ The processor system bus uses a bus technology called AGTL+, or
Assisted Gunning Transceiver Logic. AGTL+ buffers are open-drain
and require pull-up resistors for providing the high logic level and
termination. The processor AGTL+ output buffers differ from GTL+
buffers with the addition of an active pMOS pull-up transistor to “assist”
the pull-up resistors during the first clock of a low-to-high voltage
transition. Additionally, the processor Single Edge Connector (S.E.C.)
cartridge contains 56 Ωpull-up resistors to provide termination at each
bus load.
Bus Agent A component or group of components that, when combined, represent a
single load on the AGTL+ bus.
Core power rail A power rail that is only on during full-power operation. These power
rails are on when the PSON signal is asserted to the ATX power supply.
The core power rails that are distributed directly from the ATX power
supply are: ±5V, ±12V and +3.3V.
Corner Describes how a component performs when all parameters that could
impact performance are adjusted to have the same impact on
performance. Examples of these parameters include variations in
manufacturing process, operating temperature, and operating voltage.
The results in performance of an electronic component that may change
as a result of corners include (but are not limited to): clock to output
time, output driver edge rate, output drive current, and input drive
current. Discussion of the “slow”corner would mean having a
component operating at its slowest, weakest drive strength performance.
Similar discussion of the “fast”corner would mean having a component
operating at its fastest, strongest drive strength performance. Operation
or simulation of a component at its slow corner and fast corner is
expected to bound the extremes between slowest, weakest performance
and fastest, strongest performance.

Intel®810A3 Chipset Design Guide 1-3
Introduction
Cross-talk The reception on a victim network of a signal imposed by aggressor
network(s) through inductive and capacitive coupling between the
networks.
•Backward Cross-talk - coupling which creates a signal in a victim
network that travels in the opposite direction as the aggressor’s
signal.
•Forward Cross-talk - coupling which creates a signal in a victim
network that travels in the same direction as the aggressor’s signal.
•Even Mode Cross-talk - coupling from multiple aggressors when all
the aggressors switch in the same direction that the victim is
switching.
•Odd Mode Cross-talk - coupling from multiple aggressors when all
the aggressors switch in the opposite direction that the victim is
switching.
Derived power rail A derived power rail is any power rail that is generated from another
power rail using an on-board voltage regulator. For example, 3.3VSB is
usually derived (on the motherboard) from 5VSB using a voltage
regulator.
Dual power rail A dual power rail is derived from different rails at different times
(depending on the power state of the system). Usually, a dual power rail
is derived from a standby supply during suspend operation and derived
from a core supply during full-power operation.
Edge Finger The cartridge electrical contact that interfaces to the SC242 connector.
Term Definition

Introduction
1-4 Intel®810A3 Chipset Design Guide
Flight Time Flight Time is a term in the timing equation that includes the signal
propagation delay, any effects the system has on the TCO of the driver,
plus any adjustments to the signal at thereceiver needed to guarantee the
setup time of the receiver.
More precisely, flight time is defined to be:
•The time difference between a signal at the input pin of a receiving
agent crossing VREF (adjusted to meet the receiver manufacturer’s
conditions required for AC timing specifications; i.e., ringback,
etc.), and the output pin of the driving agent crossing VREF if the
driver was driving the Test Load used to specify the driver’s AC
timings.
See Section for details regarding flight time simulation and
validation.
The VREF Guardband takes into account sources of noise that may
affect the way an AGTL+ signal becomes valid at the receiver. See
the definition of the VREF Guardband.
•Maximum and Minimum Flight Time - Flight time variations can
be caused by many different parameters. The more obvious causes
include variation of the board dielectric constant, changes in load
condition, cross-talk, VTT noise, VREF noise, variation in
termination resistance and differences in I/O buffer performance as
a function of temperature, voltage and manufacturing process.
Some less obvious causes include effects of Simultaneous
Switching Output (SSO) and packaging effects.
•The Maximum Flight Time is the largest flight time a network will
experience under all variations of conditions. Maximum flight time
is measured at the appropriate VREF Guardband boundary.
•The Minimum Flight Time is the smallest flight time a network
will experience under all variations of conditions. Minimum flight
time is measured at the appropriate VREF Guardband boundary.
For more information on flight time and the VREF Guardband, see the
Pentium®II Processor Developer’s Manual.
Full-power operation During full-power operation, all components on the motherboard remain
powered. Note that full-power operation includes both the full-on
operating state (S0) and the processor Stop Grant state (S1).
GTL+ GTL+ is the bus technology used by the Pentium Pro processor. This is
an incident wave switching, open-drain bus with pull-up resistors that
provide both the high logic level and termination. It is an enhancement
to the GTL (Gunning Transceiver Logic) technology. See the Pentium®
II Processor Developer’s Manual for more details of GTL+.
Network The trace of a Printed Circuit Board (PCB) that completes an electrical
connection between two or more components.
Network Length The distance between extreme bus agents on the network and does not
include the distance connecting the end bus agents to the termination
resistors.
Term Definition

Intel®810A3 Chipset Design Guide 1-5
Introduction
Overdrive Region Is the voltage range, at a receiver, located above and below VREF for
signal integrity analysis. See the Pentium®II Processor Developer’s
Manual for more details.
Overshoot Maximum voltage allowed for a signal at the processor core pad. See
each process’s Electrical, Mechanical, and Thermal Specification for
overshoot specification.
Pad A feature of a semiconductor die contained within an internal logic
package on the S.E.C cartridge substrate used to connect the die to the
package bond wires. A pad is only observable in simulation.
Pin A feature of a logic package contained within the S.E.C. cartridge used
to connect the package to an internal substrate trace.
Power rails An ATX power supply has 6 power rails: +5V, -5V, +12V, -12V,
+3.3V, +5VSB. In addition to these power rails, several other power
rails can be created with voltage regulators.
Ringback Ringback is the voltage that a signal rings back to after achieving its
maximum absolute value. Ringback may be due to reflections, driver
oscillations, etc. See the respective Processor’s Electrical, Mechanical,
and Thermal Specification for ringback specification.
Settling Limit Defines the maximum amount of ringing at the receiving pin that a
signal must reach before its next transition. See the respective
Processor’s Electrical, Mechanical, and Thermal Specification for
settling limit specification.
Setup Window Is the time between the beginning of Setup to Clock (TSU_MIN) and the
arrival of a valid clock edge. This window may be different for each
type of bus agent in the system.
Simultaneous
Switching Output
(SSO) Effects
Refers to the difference in electrical timing parameters and degradation
in signal quality caused by multiple signal outputs simultaneously
switching voltage levels (e.g., high-to-low) in the opposite direction
from a single signal (e.g., low-to-high) or in the same direction (e.g.,
high-to-low). These are respectively called odd-mode switching and
even-mode switching. This simultaneous switching of multiple outputs
creates higher current swings that may cause additional propagation
delay (or “pushout”), or a decrease in propagation delay (or “pull-in”).
These SSO effects may impact the setup and/or hold times and are not
always taken into account by simulations. System timing budgets should
include margin for SSO effects.
Standby power rail A power rail that in on during suspend operation (these rails are also on
during full-power operation). These rails are on at all times (when the
power supply is plugged into AC power). The only standby power rail
that is distributed directly from the ATX power supply is 5VSB (5V
Standby). There can be other standby rails that are created with voltage
regulators.
Stub The branch from the trunk terminating at the pad of an agent.
Suspend operation During suspend operation, power is removed from some components on
the motherboard. The customer reference board supports three suspend
states: processor Stop Grant (S1), Suspend-to-RAM (S3) and Soft-off
(S5).
Term Definition

Introduction
1-6 Intel®810A3 Chipset Design Guide
Suspend-To-RAM
(STR) In the STR state, the system state is stored in main memory and all unnecessary system logic is turned off. Only main memory and logic
required to wake the system remain powered.
Test Load Intel uses a 50 Ωtest load for specifying its components.
Trunk The main connection, excluding interconnect branches, terminating at
agent pads.
Undershoot Maximum voltage allowed for a signal to extend below VSS at the
processor core pad. See the respective Processor’s Electrical,
Mechanical, and Thermal Specification for undershoot specifications.
Victim A network that receives a coupled cross-talk signal from another
network is called the victim network.
VREF Guardband A guardband (DVREF) defined above and below VREF to provide a more
realistic model accounting for noise such as cross-talk, VTT noise, and
VREF noise.
Term Definition

Intel®810A3 Chipset Design Guide 1-7
Introduction
1.1.2 References
•Intel®82810 Chipset: Intel®82810/82810-DC100 Graphics and Memory Controller (GMCH)
Datasheet (Document Number: 290656)
•Intel®82801AA (ICH) and 82810AB (ICH0) I/O Controller Hub Datasheet
(Document Number: 290655)
•Intel®82802AB/AC FirmWare Hub (FWH) Datasheet (Document Number: 290658)
•Intel®Celeron Processor Datasheet (Document Number: 243658)
•Intel®Celeron Processor Specification Update (Document Number: 243748)
•Intel®810 Chipset Clock Synthesizer/Driver Specification
•PPGA 370 Power Delivery Guidelines
•Intel®Pentium®II Processor AGTL+ Guidelines (Document Number: 243330)
•Intel®Pentium®II Processor Power Distribution Guidelines (Document Number: 243332)
•Intel®Pentium®II Processor Developer's Manual (Document Number: 243341)
•Intel®Pentium

II Processor at 350MHz, 400MHz and 450MHz Datasheet (Document
Number: 243657)
•Intel®Pentium

II Processor Specification Update (Document Number: 243337)
•Intel®Pentium

III Processor Datasheet (Document Number: 244452)
•Intel®Pentium

III Processor Specification Update (Document Number: 244453)
•AP-907: Intel®Pentium

III Power Distribution Guidelines (Document Number: 245085)
•PCI Local Bus Specification, Revision 2.2
•Universal Serial Bus Specification, Revision 1.0
1.2 System Overview
The Intel810A3 chipset is the first generation Integrated Graphics chipset designed for the Intel
CeleronTM processor. The graphics accelerator architecture consists of dedicated multi-media
engines executing in parallel to deliver high performance 3D, 2D, and motion compensation video
capabilities. An integrated centralized memory arbiter allocates memory bandwidth to multiple
system agents to optimize system memory utilization. A new chipset component interconnect, the
hub interface, is designed into the Intel810A3 chipset to provide an efficient communication
channel between the memory controller hub and the I/O hub controller.
The Intel810A3 chipset architecture also enables a new security and manageability infrastructure
through the Firmware Hub component.
An ACPI compliant Intel810A3 chipset platform can support the Full-on (S0), Stop Grant (S1),
Suspend to RAM (S3), Suspend to Disk (S4), and Soft-off (S5) power management states. Through
the use of an appropriate LAN device, the Intel810A3 chipset also supports wake-on-LAN*for
remote administration and troubleshooting.
The Intel810A3 chipset architecture removes the requirement for the ISA expansion bus that was
traditionally integrated into the I/O subsystem of PCIsets/AGPsets. This removes many of the
conflicts experienced when installing hardware and drivers into legacy ISA systems. The
elimination of ISA provides true plug-and-play for the Intel810A3 chipset platform.

Introduction
1-8 Intel®810A3 Chipset Design Guide
Traditionally, the ISA interface was used for audio and modem devices. The addition of AC’97
allows the OEM to use software configurable AC’97 audio and modem coder/decoders (codecs)
instead of the traditional ISA devices.
The Intel810A3 chipset contains two core components:
•Host Controller
—82810A3 Graphics and Memory Controller Hub (GMCH)
—82810A3-DC100 Graphics and Memory Controller Hub (GMCH)
•I/O Controller Hub
—82801AA (ICH)
—82801AB (ICH0)
The GMCH integrates a 66/100MHz, P6 family system bus controller, integrated 2D/3D graphics
accelerator, 100 MHz SDRAM controller and a high-speed hub interface for communication with
the I/O Controller Hub (ICH). The integrates an Ultra ATA/33 (82801AB ICH0) or Ultra ATA/66
(82801AA ICH) controller, USB host controller, LPC interface controller, FWH Flash BIOS
interface controller, PCI interface controller, AC’97 digital controller and a hub interface for
communication with the GMCH.
The Intel®Celeron™processor PPGA is the next addition to the IntelCeleron™processor
product line. The Intel®Celeron™processor PPGA implements a Dynamic Execution micro-
architecture and executes MMXTM media technology instructions for enhanced media and
communication performance.
The Intel®Celeron™processor PPGA is based on a P6 family processor core, but is provided in a
Plastic Pin Grid Array (PPGA) package for use in low cost systems in the Basic PC market
segment. The Intel®Celeron™processor PPGA utilizes the AGTL+ system bus used by the
Pentium II processor with support limited to single processor-based systems. The Intel®Celeron™
processor PPGA includes an integrated 128 KB second level cache with separate 16K instruction
and 16K data level one caches. The second level cache is capable of caching 4 GB of system
memory.
1.2.1 Graphics and Memory Controller Hub (GMCH)
The GMCH provides the interconnect between the SDRAM and the rest of the system logic:
•421 Mini BGA
•Integrated Graphics controller
•230 MHz RAMDAC
•Support for IntelCeleron and IntelPentiumIII processors with a 66, or 100 MHz
system bus.
•100 MHz SDRAM interface supporting 64 MB/256 MB/512 MB with 16Mb/64Mb/128Mb
SDRAM technology
•Optional 100 MHz 4 MB Display Cache
•Downstream hub interface for access to the ICH
•TV-Out/Flat Panel Display support