iWave iW-RainboW-G17M Installation manual

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Cyclone V SoC Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
iW-RainboW-G17M
Cyclone V SoC Qseven SOM
Hardware User Guide

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Cyclone V SoC Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Document Revision History
Document Number
iW-PREDZ-UM-01-R1.0-REL1.0-Hardware
Revision
Date
Description
0.1
09th May 2014
Initial Version
1.0
23rd July 2014
Official Release Version
PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the intended recipient(s). Do
not read this document if you are not the intended recipient. Any review, use, distribution or disclosure by others
is strictly prohibited. If you are not the intended recipient (or authorized to receive for the recipient), you are
hereby notified that any disclosure, copying distribution or use of any of the information contained within this
document is STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.”

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Cyclone V SoC Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Disclaimer
iWave Systems reserves the right to change details in this publication including but not limited to any Product
specification without notice.
No warranty of accuracy is given concerning the contents of the information contained in this publication. To the
extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by
iWave Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or
inaccuracies in this document.
CPU and other major components used in this product may have several silicon errata associated with it. Under no
circumstances, iWave Systems shall be liable for the silicon errata and associated issues.
Trademarks
All registered trademarks and product names mentioned in this publication are used for identification purposes only.
Certification
iWave Systems Technologies Pvt. Ltd. is an ISO 9001:2008 Certified Company.
Warranty & RMA
Warranty support for Hardware: 1 Year from iWave or iWave's EMS partner.
For warranty terms, go through the below web link,
http://www.iwavesystems.com/support/warranty.html
For Return Merchandise Authorization (RMA), go through the below web link,
http://www.iwavesystems.com/support/rma.html
Technical Support
iWave Systems technical support team is committed to provide the best possible support for our customers so that
our Hardware and Software can be easily migrated and used.
For assistance, contact our Technical Support team at,
Email : [e-mail]
Website : www.iwavesystems.com
Address : iWave Systems Technologies Pvt. Ltd.
# 7/B, 29th Main, BTM Layout 2nd Stage,
Bangalore, Karanataka,
India –560076

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iWave Systems Technologies Pvt. Ltd.
Table of Contents
1. INTRODUCTION ............................................................................................................................................ 7
1.1 Purpose ............................................................................................................................................................. 7
1.2 Qseven SOM Overview ..................................................................................................................................... 7
1.3 List of Acronyms................................................................................................................................................ 7
1.4 Terminlogy Description..................................................................................................................................... 9
1.5 References ........................................................................................................................................................ 9
1.6 Important Note ............................................................................................................................................... 10
2. ARCHITECTURE AND DESIGN....................................................................................................................... 11
2.1 Cyclone V SoC Qseven SOM Block Diagram....................................................................................................11
2.2 Cyclone V SoC Qseven SOM Features............................................................................................................. 12
2.3 Cyclone V SoC..................................................................................................................................................14
2.4 Boot Switches.................................................................................................................................................. 15
2.4.1 Boot Media Switch ...................................................................................................................................... 16
2.4.2 Boot Clock Switch (Optional)....................................................................................................................... 16
2.4.3 Reset Switch ................................................................................................................................................16
2.5 Memory...........................................................................................................................................................17
2.5.1 HPS DDR3 SDRAM with ECC ........................................................................................................................17
2.5.2 HPS QSPI Flash.............................................................................................................................................17
2.5.3 HPS EEPROM (Optional)..............................................................................................................................17
2.5.4 FPGA DDR3 SDRAM..................................................................................................................................... 17
2.5.5 FPGA Configuration Flash (Optional) ..........................................................................................................17
2.6 Other Features ................................................................................................................................................18
2.6.1 RTC Controller .............................................................................................................................................18
2.6.2 HPS JTAG Header......................................................................................................................................... 18
2.6.3 FPGA JTAG Header ...................................................................................................................................... 20
2.6.4 FPGA AS Header (Optional).........................................................................................................................21
2.6.5 Power IN Connector (Optional) ...................................................................................................................22
2.7 Qseven PCB Edge Connector...........................................................................................................................23
2.7.1 Qseven Interfaces from HPS........................................................................................................................24
2.7.2 Qseven Interfaces from FPGA High Speed Transceiver ............................................................................... 25
2.7.3 Qseven Interfaces from FPGA ..................................................................................................................... 25
2.8 Expansion Connector ...................................................................................................................................... 37
2.8.1 Expansion Connector Interfaces from FPGA................................................................................................38
3. TECHNICAL SPECIFICATION.......................................................................................................................... 43
3.1 Electrical Characteristics .................................................................................................................................43
3.1.1 Power Input Requirement ...........................................................................................................................43
3.1.2 Power Input Sequencing.............................................................................................................................. 43
3.1.3 Power Consumption ....................................................................................................................................44
3.2 Environmental Characteristics ........................................................................................................................45
3.2.1 Environmental Specification........................................................................................................................45

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3.2.2 Heat Spreader ............................................................................................................................................. 45
3.2.3 RoHS Compliance ........................................................................................................................................46
3.2.4 Electrostatic Discharge................................................................................................................................ 46
3.3 Mechanical Characteristics .............................................................................................................................47
3.3.1 Qseven SOM Mechanical Dimensions......................................................................................................... 47
3.3.2 Guidelines to insert the Qseven SOM into Carrier board ............................................................................ 49
4. ORDERING INFORMATION .......................................................................................................................... 50
5. APPENDIX I................................................................................................................................................. 51
5.1 Cyclone V SoC Qseven SOM Silk Screen..........................................................................................................51
6. APPENDIX II................................................................................................................................................ 53
6.1 Cyclone V SoC Qseven SOM Development Platform ......................................................................................53

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List of Figures
Figure 1: Cyclone V SoC Qseven SOM Block Diagram..................................................................................................... 11
Figure 2: Cyclone V SoC Simplified Block Diagram.......................................................................................................... 14
Figure 3: Boot Switches................................................................................................................................................... 15
Figure 4: HPS JTAG Connector ........................................................................................................................................ 18
Figure 5: FPGA JTAG Connector ......................................................................................................................................20
Figure 6: FPGA AS Connector..........................................................................................................................................21
Figure 7: 2Pin Power Connector ..................................................................................................................................... 22
Figure 8: Qseven PCB Edge Connector............................................................................................................................23
Figure 9: Expansion Connector .......................................................................................................................................37
Figure 10: Qseven SOM Power Sequence....................................................................................................................... 44
Figure 11: Heat Spreader Dimensions ............................................................................................................................46
Figure 12: Mechanical dimension of Qseven SOM- Top View........................................................................................47
Figure 13: Mechanical dimension of Qseven SOM- Bottom View..................................................................................48
Figure 14: Mechanical dimension of Qseven SOM- Side View .......................................................................................48
Figure 15: Qseven Module Insertion procedure............................................................................................................. 49
Figure 16: Silk Screen Top View ...................................................................................................................................... 51
Figure 17: Silk Screen Bottom View ................................................................................................................................ 52
Figure 18: Cyclone V SoC Qseven SOM Development Platform .....................................................................................53
List of Tables
Table 1: Acronyms & Abbreviations.................................................................................................................................. 7
Table 2: Terminology ........................................................................................................................................................ 9
Table 3: Boot Media Settings Truth Table ...................................................................................................................... 16
Table 4: HPS JTAG Header Pin Assignment..................................................................................................................... 19
Table 5: FPGA JTAG Header Pin Assignment................................................................................................................... 20
Table 6: FPGA AS Header Pin Assignment ......................................................................................................................21
Table 7: 2Pin Power Connector....................................................................................................................................... 22
Table 8: Power IN Connector - BOM............................................................................................................................... 22
Table 9: 230-Pin PCB Edge Connector Pin Assignment...................................................................................................26
Table 10: Expansion Connector Pin Assignment............................................................................................................. 39
Table 11: Power Input Requirement............................................................................................................................... 43
Table 12: Power Sequence Timing.................................................................................................................................. 44
Table 13: Power Consumption........................................................................................................................................ 44
Table 14: Environmental Specification ...........................................................................................................................45
Table 15: Orderable Product Part Numbers ...................................................................................................................50

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1. INTRODUCTION
1.1 Purpose
This document is the Hardware User Guide for the Cyclone V SoC Qseven System On Module based on the Altera’s
Cyclone V SoC. This board is fully supported by iWave Systems Technologies Pvt. Ltd. This Guide provides detailed
information on the overall design, technical specification and usage of the Cyclone V SoC Qseven System On Module
from a Hardware Systems perspective.
1.2 Qseven SOM Overview
The Qseven concept is an off-the-shelf, multi-vendor, Single-Board-Computer that integrates all the core
components of a common PC and is mounted onto an application specific carrier board. Qseven modules have a
standardized form factor of 70mm x70mm and have specified pin outs based on the high speed MXM system
connector that has a standardized pin out regardless of the vendor. A single ruggedized MXM connector provides the
carrier board interface to carry all the I/O signals to and from the Qseven module.
1.3 List of Acronyms
The following acronyms will be used throughout this document.
Table 1: Acronyms & Abbreviations
Acronyms
Abbreviations
AC
Alternate Current
ARM
Advanced RISC Machine
BOM
Bill of Material
CAN
Controller Area Network
CPU
Central Processing Unit
DDR3
Double Data Rate 3
ECC
Error Correction Code
EEPROM
Electrically Erasable Programmable Read Only Memory
EPCQ
Enhanced Programmable Configuration Quad
FPGA
Field Programmable Gate Array
MMC
Multi Media Card
GB
Giga Byte
Gbps
Gigabits per sec
GPIO
General Purpose Input Output
HPS
Hard Processor System
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
JTAG
Joint Test Action Group
Kbps
Kilobits per second

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Acronyms
Abbreviations
LCD
Liquid Crystal Display
LED
Light Emitting Diode
LPC
Low Pin Count
MB
Mega Byte
Mbps
Megabits per sec
MDI
Media Dependent Interface
MHz
Mega Hertz
MMC
Multi Media Card
MOQ
Minimum Order Quantity
NAND
Not AND
PCB
Printed Circuit Board
PCIe
Peripheral Component Interconnect Express
PWM
Pulse Width Modulation
QSPI
Quad Serial Peripheral Interface
RAM
Random Access Memory
RGMII
Reduced Gigabit Media Independent Interface
ROM
Read-Only Memory
RTC
Real Time Clock
SATA
Serial Advanced Technology Attachment
SE
Single Ended
SD
Secure Digital
SDIO
Secure Digital Input Output
SDRAM
Synchronous Dynamic Random Access Memory
SMBUS
System Management Bus
SoC
System on Chip
SOM
System On Module
SPI
Serial Peripheral Interface
SSI
Synchronous Serial Interface
UART
Universal Asynchronous Receiver/Transmitter
USB
Universal Serial Bus
WDOG
Watch Dog

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1.4 Terminlogy Description
In this document, wherever Signal Type is mentioned, below terminology is used.
Table 2: Terminology
Terminology
Description
I
Input
O
Output
IO
Bidirectional Input/output
CMOS
Complementary Metal Oxide Semiconductor Signal
LVDS
Low Voltage Differential Signal
DIFF
Differential Signal
OD
Open Drain Signal
OC
Open Collector Signal
PU
Pull Up
PD
Pull Down
NA
Not Applicable
NC
Not Connected
Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes
the pull-ups or pull-downs implemented On-SOM.
1.5 References
Cyclone V Device Handbook
Cyclone V Device Overview
Qseven Specification Revision 2.0

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1.6 Important Note
In this document, wherever Cyclone V SoC signal name is mentioned, it is followed as per below format.
For SoC HPS Signals, If HPS pin functionality name and HPS pad name is same, Signal name is mentioned as
“HPS_SoC Pad Name”
Example: HPS_SDMMC_D0
In this signal, functionality which we are using and SoC pad name is SDMMC_D0.
For SoC HPS Signals, If HPS pin functionality name and pad name is different, Signal name is mentioned as
“HPS_Functionality Name(SoC Pad Name)”
Example: HPS_USB1_D0 (RGMII0_TXD0)
In this signal, HPS_USB1_D0 is the functionality which we are using and RGMII0_TXD0 is the SoC pad name.
For SoC FPGA Signals, signal name is mentioned as
“FPGA_Pin Number_Functionality Name”
Example: FPGA_AH23_LVDS_A0P
In this signal, AH23 is the Cyclone V SoC Pin number and LVDS_A0P is the functionality which we are using
with this FPGA pin.
Note: The above naming is not applicable for other signals which are not connected to Cyclone V SoC.

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2. ARCHITECTURE AND DESIGN
This section provides detailed information about the Cyclone V SoC Qseven SOM Features and Hardware
architecture with high level block diagram. Also this section provides detailed information about Qseven edge
connector & Expansion connector pin assignment and usage.
2.1 Cyclone V SoC Qseven SOM Block Diagram
iW-RainboW-G17M-Cyclone V SoC Qseven SOM Block Diagram
QSEVEN
PCB Edge
Connector
(230Pin)
80 Pin
Expansion
connector
DDR3 RAM
(512MB)
DDR3 (32bit)
QSPI Flash
(16MB)
QSPI
RTC
Controller
Ethernet
PHY
USB PHY USB 2.0 Hub
(4Port)
Gbit Ethernet
RGMII
Hard Processor System
(Dual-core
ARM® Cortex™-A9
MP Core processor)
FPGA
PCIe x 4 Port
SATA x 1 Port
UTMI
I2C
Power IN
(Optional)
Power
Regulators
5V
Power to
Peripherals
HPS JTAG JTAG USB Host
FPGA JTAG JTAG
SMBUS/2 SE IOs
DDR3 for ECC DDR3 ECC (8bit)
EEPROM
(Optional)
I2C
8 Single Ended IOs/LPC Interface
9 TX LVDS Pairs/18 SE IOs
Cyclone V SX - SoC FPGA
11 RX LVDS Pairs/22 SE IOs
General Purpose Clock Inputs (2 LVDS/2 SE)
SD/MMC (8bit)
SPI (with 2 Chip selects)
Debug UART
2nd UART
CAN
I2Cx 2 Ports
Micro SD
Connector
5 Single Ended IOs
WDOG
PWM
General Purpose Clock Outputs (1 LVDS/2 SE)
FPGA AS
Header
(Optional)
AS Interface
SATA 2nd Port* (Optional)
SDRAM
Controller SPIM0
I2C0, I2C1
UART0
UART1
CAN1
GPIO
USB1
JTAG
EMAC1
SD/MMC
PCIe
Hard IP
High Speed
Transceiver
CH0
CH1
CH2
CH3
CH5
CH4
AC97/I2S x 1 Port
FPGA IOs
(2.5V Differential /
2.5V Single Ended) FPGA IOs
(3.3V Single
Ended)
DDR3 RAM
(256MB)
EPCQ Flash
(Optional)
DDR3 (16bit)
QSPI Flash
(Optional)
DDR3 Controller
(Soft IP)
JTAG
FPGA Dedicated
Clock IOs
(2.5V Differential /
2.5V Single Ended)
LVDS LCD (24bpp) x 2 Port
LCD (Soft IP)
2.5V Differential
SMBUS (Soft IP)
3.3V Single Ended
* If SATA 2nd Port is needed, PCIe x 2 port only can be supported
QSPI
I2C0
I2C0
Active Serial
SATA
Soft IP
AC97/I2S(Soft IP)
3.3V Single Ended
Figure 1:Cyclone V SoC Qseven SOM Block Diagram

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2.2 Cyclone V SoC Qseven SOM Features
The Cyclone V SoC Qseven SOM supports the following features.
SoC
Altera’s Cyclone V SX SoC FPGA with Integrated Dual Core ARM Cortex-A9 @800MHz/Core Hard
Processor System(HPS) and FPGA up to 110K LEs
Boot Switches
Boot Media Setting Switch
Boot Clock Setting Switch (Optional)
Reset Switch
Memory
512MB HPS DDR3 RAM with ECC (Expandable)
HPS QSPI Flash(16MB)
HPS EEPROM (Optional)
256MB FPGA DDR3 RAM (Expandable)
FPGA Configuration Flash(Optional)
Other Features
RTC Controller
HPS JTAG Header
FPGA JTAG Header
FPGA AS Header (Optional)
Power IN Connector (Optional)
Qseven PCB Edge Interfaces
From HPS:
Gigabit Ethernet x 1 Port (through On-SOM Gigabit Ethernet PHY)
USB Host 2.0 x 4 Ports (through On-SOM 4 port USB Hub)
SD/MMC (8bit) x 1 Port
Debug UART
Data UART x 1 Port
CAN x 1 Port
I2C x 2 Ports
SPI x 1 Port (with 2 Chip selects )
WDOG

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From FPGA High Speed Transceiver:
PCIe Gen2.0 x 4 Ports through Cyclone V SoC Hard Block
SATA x 1 Port (Soft IP)
From FPGA (Soft IP):
LVDS LCD x 2 Ports
AC97/SSI Audio x 1 Port
PWM x 1 Port
8 Single Ended GPIOs/LPC Interface
Expansion Connector Interfaces (from FPGA)
General Purpose Clock Inputs (2 LVDS/2 SE)
General Purpose Clock Outputs (1 LVDS/2 SE)
9 TX LVDS Pairs/18 SE IOs
11 RX LVDS Pairs/22 SE IOs
5 Single Ended IOs
SMBUS/2 SE IOs
FPGA JTAG
General Specification
Power Supply : 5V, 2A
Form Factor : 70mm X 70mm (Qseven R2.0 Specification)
Note: If the FPGA interfaces available in the Qseven edge are not used for Qseven compliance requirement, same
interface pins can be used for custom Industrial/Networking interface requirements.
Note: iWave supports different Soft IPs for Cyclone V FPGA. Please contact iWave for more details.

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2.3 Cyclone V SoC
Cyclone V SoC Qseven SOM is based on Altera’s Cyclone V SX SoC Dual Core ARM Cortex-A9 HPS with FPGA based
CPU which can operate up to 800 MHz speed/core. The Dual ARM Cortex A9 core with the FPGA allows greater
flexibility for the system designers and helps to lower the system cost and power consumption. This improved logic
integration with increased bandwidth capacity which is ideal for cost-sensitive high end applications. The Block
diagram of Cyclone V SoC from the Altera’s Cyclone V SoC datasheet is shown below for your reference.
Figure 2: Cyclone V SoC Simplified Block Diagram
Note: Please refer the latest Cyclone V SoC Datasheet & Handbook from Altera website for Electrical characteristics of
Cyclone V SoC which may be revised from time to time.

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2.4 Boot Switches
Cyclone V SoC boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to
begin execution starting from the on-chip boot ROM. The Cyclone V SoC Boot ROM code reads the boot information
register to read the boot select (bsel) and clock select (csel) values to determine the boot source and to set up the
clock manager. The bsel and csel values come from the BOOTSEL and CLKSEL pins which are sampled out of reset.
Cyclone V SoC Qseven SOM supports below mentioned switches for boot purposes which are explained in following
section.
Boot Media Switch
Boot Clock Switch (Optional)
Reset Switch
Figure 3: Boot Switches

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2.4.1 Boot Media Switch
Cyclone V SoC Qseven SOM supports two positions Boot Media Switch (SW2) which is physically located in the top of
the PCB. This switch is used to select the boot media of Cyclone V SoC (bsel). Cyclone V SoC Qseven SOM supports
different boot media options for booting Cyclone V SoC as explained in the below table.
Table 3: Boot Media Settings Truth Table
Boot Media Setting On Cyclone V SoC
Qseven SOM
SW2 (2 Position Switch) for BOOTSEL
POS1
POS2
Image
SD Memory (4bit)
(Default)
OFF
ON
FPGA (HPS-to-FPGA bridge)
OFF
OFF
SPI or Quad SPI Flash Memory
ON
ON
ON - High
OFF - Low
2.4.2 Boot Clock Switch (Optional)
Cyclone V SoC Qseven SOM optionally supports two positions Boot Clock Switch (SW3) which is physically located in
the top of the PCB. This switch can be used to select the boot Clock Frequency of boot media. This is the optional
feature and will not be populated in default configuration.
Important Note: Cyclone V HPS’s OSC1 pin (HPS_CLK1) is provided with 25 MHz clock source on the SOM. Also
CSEL[1:0] pins are always set to 11b On-SOM hardware.
2.4.3 Reset Switch
Cyclone V SoC Qseven SOM supports On-SOM reset switch (SW1). This momentary push-button switch can be used
to reset the Cyclone V SoC. This reset is connected to Cyclone V HPS’s HPS_NPOR pin and Cyclone V FPGA IO pin (SoC
Pin number D12).

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2.5 Memory
2.5.1 HPS DDR3 SDRAM with ECC
Cyclone V SoC Qseven SOM uses two 256MB DDR3 SDRAM ICs to support a total on board HPS RAM memory of
512MB (Expandable). Also HPS supports 8bit ECC. These devices operate at 1.5V voltage level. The DRAM calibration
resistor used on Qseven SOM is 240 Ohm 1% resistor. This pair of DDR3 is connected to HPS Block of the Cyclone V
SoC. A pair of DDR3 IC is physically located on top of the Qseven SOM.
2.5.2 HPS QSPI Flash
Cyclone V SoC Qseven SOM supports 16MB QSPI (Expandable) memory as Mass storage also a boot device. QSPI is
connected to the HPS Block of the Cyclone V SoC and operating under 3.3V Voltage level. The QSPI flash memory is
physically located on top of the Qseven SOM.
2.5.3 HPS EEPROM (Optional)
Cyclone V SoC Qseven SOM supports 256Mbit EEPROM memory as optional configuration storage. EEPROM is
connected to the HPS Block of the Cyclone V SoC through I2C0 Interface and operating under 3.3V Voltage level. The
EEPROM memory is physically located on bottom of the Qseven SOM. This is the optional feature and will not be
populated in default configuration.
2.5.4 FPGA DDR3 SDRAM
Cyclone V SoC Qseven SOM uses single 256MB DDR3 SDRAM ICs to support FPGA Configuration. This device
operates at 1.5V voltage level. The DRAM calibration resistor used on Qseven SOM is 240 Ohm 1% resistor. This
DDR3 is connected to FPGA Block of the Cyclone V SoC. DDR3 IC is physically located on top of the Qseven SOM.
2.5.5 FPGA Configuration Flash (Optional)
Cyclone V SoC Qseven SOM optionally supports 64MB EPCQ Flash or QSPI Flash as an FPGA Configuration device.
This Flash is connected to the FPGA Block of the Cyclone V SoC and operating under 3.3V Voltage level. This is the
optional feature and will not be populated in default configuration.

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2.6 Other Features
2.6.1 RTC Controller
Cyclone V SoC Qseven SOM supports On-SOM external RTC Controller “BQ32000DR”. This device is connected to the
HPS Block of the Cyclone V SoC through I2C0 Interface and operating under 3.3V Voltage level. IRQ output of this
device is connected to HPS_GPI9. In SOM power off condition, this device will take power from Qseven Edge
VCC_RTC coin cell power input (Pin 193).
2.6.2 HPS JTAG Header
A customized 20-pin ARM JTAG connector is available in Cyclone V SoC Qseven SOM for debug purpose. 3.3V
reference voltage is provided to pin1 of the connector to allow JTAG tool to automatically configure the logic signals
for the right voltage. JTAG connector is physically located on top of the SOM.
Figure 4: HPS JTAG Connector
Number of Pins - 20
Connector Part - GRPB102MWCN-RC from Sullins Connector Solutions
Mating Connector - LPPB102CFFN-RC from Sullins Connector Solutions

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Table 4: HPS JTAG Header Pin Assignment
Pin
No
Signal Name
Signal Type/
Termination
Description
1
VCC_3V3
O, 3.3V Power
VREF reference Voltage.
2
VCC_3V3
O, 3.3V Power
Supply Voltage.
3
HPS_TRST
I, 3.3V CMOS/
10K PU
JTAG test reset signal.
4
GND
Power
Ground.
5
HPS_TDI
I, 3.3V CMOS/
10K PU
JTAG test data input.
6
GND
Power
Ground.
7
HPS_TMS
I, 3.3V CMOS/
10K PU
JTAG test mode select.
8
GND
Power
Ground.
9
HPS_TCK
I, 3.3V CMOS/
1K PD
JTAG test Clock.
10
GND
Power
Ground.
11
-
-
NC.
12
GND
Power
Ground.
13
HPS_TDO
O, 3.3V CMOS
JTAG test data output.
14
GND
Power
Ground.
15
RSTBTN
I, 3.3V CMOS
Reset Signal.
16
GND
Power
Ground.
17
-
-
NC.
18
GND
Power
Ground.
19
-
-
NC.
20
GND
Power
Ground.

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2.6.3 FPGA JTAG Header
A customized 10-pin FPGA JTAG connector is available in Cyclone V SoC Qseven SOM for debug and Configuration
purpose. JTAG connector is physically located on top of the SOM.
Figure 5: FPGA JTAG Connector
Number of Pins - 10
Connector Part - GRPB052MWCN-RC from Sullins Connector Solutions
Mating Connector - LPPB052CFFN-RC from Sullins Connector Solutions
Table 5: FPGA JTAG Header Pin Assignment
Pin
No
Signal Name
Signal Type/
Termination
Description
1
FPGA_JTAG_TCK
I, 3.3V CMOS/
1K PD
JTAG test clock.
2
GND
Power
Ground.
3
FPGA_JTAG_TDO
O, 3.3V CMOS
JTAG test data output.
4
VCC_3V3
O, 3.3V Power
Supply Voltage.
5
FPGA_JTAG_TMS
I, 3.3V CMOS/
10K PU
JTAG test mode select.
6
-
-
NC.
7
-
-
NC.
8
-
-
NC.
9
FPGA_JTAG_TDI
I, 3.3V CMOS/
10K PU
JTAG test data input.
10
GND
Power
Ground.