iWave iW-RainboW-G18M Installation manual

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i.MX6UL/i.MX6ULL SODIMM SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
iW-RainboW-G18M
i.MX6UL/i.MX6ULL SODIMM SOM
Hardware User Guide

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Document Revision History
Document Number
iW-PREVZ-UM-01-R2.0-REL1.2-Hardware
Revision
Date
Change Description
1.0
20th Oct 2015
Initial Release Version
1.1
15th Dec 2015
•SODIMM Edge conenctor pin details are updated in Table 5 for pins 135, 137, 141,
147, 179, 182, 184, 191 & 195.
•Non substantive changes throughout the document.
1.2
21st June 2017
•i.MX6ULL support is added throughout the document.
•Section 2.6.12 is updated with Important Note.
•Pins 47, 68, 73, 86, 133, 134 & 136 details are updated in Table 5.
•CPU Pad Name and ALT0 pin details are updated in Table 7 for pins 62, 63, 66, 70,
93, 104, 110 & 120.
•Orderable Product Part Numbers are updated in Table 12.
•Non substantive changes throughout the document.
PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the intended recipient(s). Do
not read this document if you are not the intended recipient. Any review, use, distribution or disclosure by others is
strictly prohibited. If you are not the intended recipient (or authorized to receive for the recipient), you are hereby
notified that any disclosure, copying distribution or use of any of the information contained within this document is
STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.”

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Disclaimer
iWave Systems reserves the right to change details in this publication including but not limited to any Product
specification without notice.
No warranty of accuracy is given concerning the contents of the information contained in this publication. To the
extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by iWave
Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or
inaccuracies in this document.
CPU and other major components used in this product may have several silicon errata associated with it. Under no
circumstances, iWave Systems shall be liable for the silicon errata and associated issues.
Trademarks
All registered trademarks, product names mentioned in this publication are the property of their respective owners
and used for identification purposes only.
Certification
iWave Systems Technologies Pvt. Ltd. is an ISO 9001:2015 Certified Company.
Warranty & RMA
Warranty support for Hardware: 1 Year from iWave or iWave's EMS partner.
For warranty terms, go through the below web link,
http://www.iwavesystems.com/support/warranty.html
For Return Merchandise Authorization (RMA), go through the below web link,
http://www.iwavesystems.com/support/rma.html
Technical Support
iWave Systems technical support team is committed to provide the best possible support for our customers so that
our Hardware and Software can be easily migrated and used.
For assistance, contact our Technical Support team at,
Email : [e-mail]
Website : www.iwavesystems.com
Address : iWave Systems Technologies Pvt. Ltd.
# 7/B, 29th Main, BTM Layout 2nd Stage,
Bangalore, Karnataka,
India –560076

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Table of Contents
1. INTRODUCTION ............................................................................................................................................7
1.1 Purpose .............................................................................................................................................................7
1.2 SODIMM SOM Overview................................................................................................................................... 7
1.3 List of Acronyms................................................................................................................................................7
1.4 Terminlogy Description.....................................................................................................................................9
1.5 References ........................................................................................................................................................9
1.6 Important Note ...............................................................................................................................................10
2. ARCHITECTURE AND DESIGN....................................................................................................................... 11
2.1 i.MX6UL/i.MX6ULL SODIMM SOM Block Diagram .........................................................................................11
2.2 i.MX6UL/i.MX6ULL SODIMM SOM Features...................................................................................................12
2.3 i.MX6UL/i.MX6ULL CPU ..................................................................................................................................14
2.4 PMIC................................................................................................................................................................16
2.5 Memory...........................................................................................................................................................16
2.5.1 DDR3L SDRAM.............................................................................................................................................16
2.5.2 NAND Flash .................................................................................................................................................16
2.6 SODIMM PCB Edge Connector........................................................................................................................17
2.6.1 UART Interface ............................................................................................................................................18
2.6.2 CAN Interface ..............................................................................................................................................18
2.6.3 SD Interface.................................................................................................................................................18
2.6.4 Parallel RGB Display Interface.....................................................................................................................18
2.6.5 Parallel Camera Interface............................................................................................................................19
2.6.6 I2S Audio Interface ......................................................................................................................................19
2.6.7 JTAG Interface .............................................................................................................................................19
2.6.8 USB 2.0 OTG Interface.................................................................................................................................20
2.6.9 Dual 10/100Mbps Ethernet.........................................................................................................................20
2.6.10 I2C Interface................................................................................................................................................21
2.6.11 PWM Interface ............................................................................................................................................21
2.6.12 Tamper Interface.........................................................................................................................................21
2.6.13 GPIO Interface.............................................................................................................................................21
2.6.14 General Purpose Clock.................................................................................................................................22
2.6.15 Boot Mode Signals ......................................................................................................................................22
2.6.16 Power Input.................................................................................................................................................23
2.6.17 Reset Signal.................................................................................................................................................23
2.6.18 Power Control Signal...................................................................................................................................23
2.7 Optional Features............................................................................................................................................36
2.7.1 eMMC Flash ................................................................................................................................................36
2.7.2 Micro SD Slot...............................................................................................................................................36
2.7.3 QSPI Flash....................................................................................................................................................36
2.7.4 PMIC OTP Header........................................................................................................................................37
2.8 i.MX6UL/i.MX6ULL Pin Multiplexing on SODIMM Edge .................................................................................38

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3. TECHNICAL SPECIFICATION.......................................................................................................................... 45
3.1 Electrical Characteristics .................................................................................................................................45
3.1.1 Power Input Requirement ...........................................................................................................................45
3.1.2 Power Input Sequencing..............................................................................................................................46
3.1.3 Power Consumption ....................................................................................................................................47
3.2 Environmental Characteristics ........................................................................................................................48
3.2.1 Environmental Specification........................................................................................................................48
3.2.2 RoHS Compliance ........................................................................................................................................48
3.2.3 Electrostatic Discharge................................................................................................................................48
3.3 Mechanical Characteristics .............................................................................................................................49
3.3.1 SODIMM SOM Mechanical Dimensions ......................................................................................................49
4. ORDERING INFORMATION .......................................................................................................................... 51
5. APPENDIX I................................................................................................................................................. 53
5.1 Guidelines to insert the SODIMM SOM into Carrier board ............................................................................53
5.2 Guidelines to remove the SODIMM SOM from Carrier board........................................................................53
6. APPENDIX II................................................................................................................................................ 54
6.1 i.MX6UL/i.MX6ULL SODIMM SOM Development Platform............................................................................54

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List of Figures
Figure 1: i.MX6UL/i.MX6ULL SODIMM SOM Block Diagram ..........................................................................................11
Figure 2: i.MX6UL Simplified Block Diagram...................................................................................................................14
Figure 3: i.MX6UL/i.MX6ULL CPU devices comparison ..................................................................................................15
Figure 4: SODIMM PCB Edge Connector.........................................................................................................................17
Figure 5: PMIC OTP Header.............................................................................................................................................37
Figure 6: i.MX6UL/i.MX6ULL SODIMM SOM Power Sequence.......................................................................................46
Figure 7: Mechanical dimension of SODIMM SOM - Top View ......................................................................................49
Figure 8: Mechanical dimension of SODIMM SOM - Bottom View ................................................................................49
Figure 9: Mechanical dimension of SODIMM SOM - Side View......................................................................................50
Figure 10: SODIMM SOM Insertion procedure...............................................................................................................53
Figure 11: SODIMM SOM Removal procedure ...............................................................................................................53
Figure 12: i.MX6UL/i.MX6ULL SODIMM SOM Development Platform...........................................................................54
List of Tables
Table 1: Acronyms & Abbreviations.................................................................................................................................. 7
Table 2: Terminology ........................................................................................................................................................9
Table 3: Compatible Magnetics ......................................................................................................................................20
Table 4: Boot Mode Pin Settings Truth Table .................................................................................................................22
Table 5: 200-Pin PCB Edge Connector Pin Assignment...................................................................................................24
Table 6: PMIC OTP Header Pin Assignment ....................................................................................................................37
Table 7: IOMUX Configuration of i.MX6UL/i.MX6ULL SODIMM SOM Edge Connector interfaces ................................38
Table 8: Power Input Requirement.................................................................................................................................45
Table 9: Power Sequence Timing....................................................................................................................................46
Table 10: Power Consumption........................................................................................................................................47
Table 11: Environmental Specification ...........................................................................................................................48
Table 12: Orderable Product Part Numbers ...................................................................................................................51

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1. INTRODUCTION
1.1 Purpose
This document is the Hardware User Guide for the i.MX 6UltraLite (here after mentioned as i.MX6UL)/i.MX6ULL
SODIMM System On Module based on the NXP’s i.MX6UL/i.MX6ULL Applications Processor with PMIC. This board is
fully supported by iWave Systems Technologies Pvt. Ltd. This Guide provides detailed information on the overall design
and usage of the i.MX6UL/i.MX6ULL SODIMM System On Module from a Hardware Systems perspective.
1.2 SODIMM SOM Overview
The i.MX6UL/i.MX6ULL SODIMM SOM is extension of i.MX6UL/i.MX6ULL CPU. Also with the SOM approach one can
reduce the cost and time required for the development of customised solution on i.MX6UL/i.MX6ULL platform.
SODIMM module has a form factor of 67.6mm.x 29mm and provides the functional requirements for an embedded
application. A single ruggedized SODIMM connector provides the carrier board interface to carry all the I/O signals to
and from the SODIMM module.
1.3 List of Acronyms
The following acronyms will be used throughout this document.
Table 1: Acronyms & Abbreviations
Acronyms
Abbreviations
A
Ampere
ARM
Advanced RISC Machine
BOM
Bill of Material
BPP
Bits Per Pixel
BSP
Board Support Package
CAN
Controller Area Network
CMOS
Complementary Metal-Oxide Semiconductor
CPU
Central Processing Unit
CSI
Camera Serial Interface
DDR3
Double Data Rate 3
eCSPI
Enhanced Configurable Serial Peripheral Interface
eMMC
Enhanced Multi Media Card
FLEXCAN
Flexible Controller Area Network
GB
Giga Byte
Gbps
Gigabits per sec
GPIO
General Purpose Input Output
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
JTAG
Joint Test Action Group

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Acronyms
Abbreviations
Kbps
Kilobits per second
LCD
Liquid Crystal Display
MAC
Media Access Controller
MB
Mega Byte
Mbps
Megabits per sec
MHz
Mega Hertz
NC
No Connect
NPTH
Non Plated Through hole
PCB
Printed Circuit Board
PMIC
Power Management Integrated Circuit
PTH
Plated Through hole
PWM
Pulse Width Modulation
PXP
Pixel Pipeline
QSPI
Quad Serial Peripheral Interface
RMII
Reduced Media Independent Interface
ROM
Read-Only Memory
RTC
Real Time Clock
SAI
Synchronous Audio Interface
SD
Secure Digital
SDRAM
Synchronous Dynamic Random Access Memory
SODIMM
Small Outline Dual in-line Memory Module
SOM
System On Module
uA
Micro Ampere
UART
Universal Asynchronous Receiver/Transmitter
UL
Ultra Lite
uSDHC
Ultra Secured Digital Host Controller
USB
Universal Serial Bus
USB OTG
USB On The Go
V
Voltage

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1.4 Terminlogy Description
In this document, wherever Signal Type is mentioned, below terminology is used.
Table 2: Terminology
Terminology
Description
I
Input Signal
O
Output Signal
IO
Bidirectional Input/output Signal
CMOS
Complementary Metal Oxide Semiconductor Signal
DIFF
Differential Signal
TMDS
Transition-Minimized Differential Signalling
OD
Open Drain Signal
OC
Open Collector Signal
Analog
Analog Signal
Power
Power Pin
PU
Pull Up
PD
Pull Down
NA
Not Applicable
NC
Not Connected
Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes
the pull-ups or pull-downs implemented On-SOM.
1.5 References
•i.MX6UL/i.MX6ULL Applications Processors Datasheet
•i.MX6UL/i.MX6ULL Applications Processors Reference Manual

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1.6 Important Note
i.MX6UL/i.MX6ULL SODIMM Edge connector pin name mentioned in Table 5 is followed as per below format for easy
understanding.
•If CPU pin functionality name and CPU pad name is same, Signal name is mentioned as
“CPU Pad Name”
Example: SD1_DATA1
In this signal, functionality which we are using and CPU Pad name is SD1_DATA1.
•If CPU pin functionality name and pad name is different, Signal name is mentioned as
“Functionality name (CPU Pad name)”
Example: CAN1_RXD (UART3_RTS_B)
In this signal, CAN1_RXD is the functionality which we are using and UART3_RTS_B is the CPU Pad name.
•If CPU pin functionality is GPIO, Signal name is mentioned as
“FunctionalityDescription (CPU Pad name)”
Example: PWM4_OUT (GPIO1_IO05)
In this signal, PWM4_OUT is the functionality which we are using and GPIO1_IO05 is the CPU pad name.
Note: The above naming is not applicable for other signals which are not connected to CPU.

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2. ARCHITECTURE AND DESIGN
This section provides detailed information about the i.MX6UL/i.MX6ULL SODIMM SOM Features and Hardware
architecture with high level block diagram. Also this section provides detailed information about SODIMM edge
connector pin assignment and usage.
2.1 i.MX6UL/i.MX6ULL SODIMM SOM Block Diagram
DDR3 RAM
(256MB)
NAND Flash1
(256MB)
SODIMM
PCB Edge
Connector
(200Pin)
10/100Mbps
Ethernet1
RMII
I2C x 1
PWM x 2
ENET1
I2C1
PWM4 &
PWM5
Tamper/
GPIOs
NAND (8bit)
DDR3 (16bit) 10/100Mbps
Ethernet PHY
MMDC
RAWNAND/
uSDHC2/
QSPI_A
LCDIF
iW-RainboW-G18M-i.MX6UL/i.MX6ULL SODIMM SOM Block Diagram
Tamper/GPIOs4
Power to
Peripherals
3.3V
CSI0
On-Board
PMIC
RGB LCD (24bpp)
Camera (8bit)/eCSPI x 1
ENET2
uSD
Connector1
(Optional)
eMMC1
(Optional)
USB OTG1
USB OTG2
USB OTG2
HS PHY
USB OTG1
HS PHY
RMII 10/100Mbps
Ethernet PHY
I2S3
SAI2/
JTAG
uSDHC1 SD (4bit)
UART1 Debug UART
UART2 &
UART3
Data UART (with CTS & RTS)
FLEXCAN1,
FLEXCAN2
CAN x 2
QSPI1
(Optional)
1For On-SOM storage, any one of the below
options can be selected.
•8bit NAND Flash (Default)
•8bit eMMC and QSPI flash
•4bit uSD and QSPI Flash
10/100Mbps
Ethernet2
RMII/Data UART x 3/Keypad (4x4)2
MMC (8bit)
SD (4bit)
QSPI (4bit)
JTAG3
UART5
Data UART x 2
BootMode0 &
BootMode1
Boot Mode
CPU
i.MX6UL/
i.MX6ULL
CCM_CLK General purpose Clock
2If 2nd Ethernet support is not required on the
SODIMM Edge Connector, RMII interface or
Data UART x 3ports or 4x4 Keypad interface
can be used in the SODIMM Edge.
3Since Audio and JTAG interface signals are
multiplexed in same pins on CPU, either one
interface only can be used at a time.
4Tamper functionality is supported only in
i.MX6UL3 version CPU.
Figure 1: i.MX6UL/i.MX6ULL SODIMM SOM Block Diagram

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2.2 i.MX6UL/i.MX6ULL SODIMM SOM Features
The i.MX6UL/i.MX6ULL SODIMM SOM supports the following features.
CPU
•NXP’s i.MX6UL/i.MX6ULL ARM Cortex®-A7 core based CPU
PMIC
•NXP’s PF3001 PMIC
Memory
•256MB DDR3L (Expandable)
•256MB NAND Flash (Expandable)
•4GB eMMC Flash (Optional)1
•Micro SD slot (Optional)2
•QSPI Flash (Optional)3
Network & Communication
•10/100Mbps Ethernet PHY x 2 Ports
SODIMM PCB Edge Interfaces
•Debug UART
•Data UART x 3 Ports
•CAN x 2 Ports
•SD (4bit) x 1 Port
•Parallel RGB Display (24bpp) x 1 Port
•Parallel Camera Interface (8bit) x 1 Port (or eCSPI x 1 Port)
•I2S Audio Interface x 1 Port4
•JTAG x 1 Port4
•USB OTG x 2 Ports
•10/100Mbps Ethernet x 2 Ports5
•I2C x 1 Port
•PWM x 2 Ports
•Tamper Signals6
•General Purpose Clock
•Boot Mode Signals
•Power Control Signals

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General Specification
•Power Supply : 3.3V, 1A
•Form Factor : 67.6mm x 29mm
1Since NAND Flash, eMMC and QSPI are multiplexed in same pins on i.MX6UL/i.MX6ULL CPU, if eMMC flash feature is
required in the SOM, NAND flash and Micro SD on SOM cannot be used.
2Since NAND Flash, Micro SD and QSPI are multiplexed in same pins on i.MX6UL/i.MX6ULL CPU, if Micro SD feature is
required in the SOM, NAND flash and eMMC on SOM cannot be used.
3Since NAND Flash and QSPI are multiplexed in same pins on i.MX6UL/i.MX6ULL CPU, if NAND Flash feature is required
in the SOM, QSPI on SOM cannot be used.
4Since Audio and JTAG interface signals are multiplexed in same pins on i.MX6UL/i.MX6ULL CPU, either one interface
only can be used at a time.
5 ENET2 interface is connected to On SOM Ethernet PHY and also optionally connected from i.MX6UL/i.MX6ULL CPU to
SODIMM edge connector, either one interface only can be used at a time.
6 Only i.MX6UL3 version CPU supports tamper functionality. For all other i.MX6UL/i.MX6ULL CPU versions, tamper pins
are used as only GPIOs.

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2.3 i.MX6UL/i.MX6ULL CPU
i.MX6UL/i.MX6ULL SODIMM SOM is based on NXP’s i.MX6UL/i.MX6ULL high performance, ultra-efficient processor
family featuring an advanced implementation of a single ARM® Cortex®-A7 core. The Block Diagram of i.MX6UL CPU
from the NXP’s i.MX6UL datasheet is shown below for reference.
Figure 2: i.MX6UL Simplified Block Diagram
Note: Please refer the latest i.MX6UL/i.MX6ULL Datasheet & Reference Manual from NXP website for Electrical
characteristics of i.MX6UL/i.MX6ULL Application CPU which may be revised from time to time.

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i.MX6UL CPU has many sub version CPUs i.MX6UL0, i.MX6UL1, i.MX6UL2 & i.MX6UL3. Also i.MX6ULL CPU has many
sub version CPUs i.MX6ULL0, i.MX6ULL1 & i.MX6ULL2 The difference between these CPUs from NXP’s factsheet is
shown below for reference.
Figure 3: i.MX6UL/i.MX6ULL CPU devices comparison

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2.4 PMIC
i.MX6UL/i.MX6ULL SODIMM SOM supports NXP’s PF3001 PMIC for On-SOM power management. The PF3001 is a
Power Management Integrated Circuit (PMIC) designed specifically for always ON application with the NXP
i.MX6UL/i.MX6ULL application processors. Also i.MX6UL/i.MX6ULL SODIMM SOM can optionally support NXP’s
PF3000 PMIC which supports Low power and Standby operation too.
The PF3001 PMIC provides all required power to i.MX6UL/i.MX6ULL CPU and all On SOM peripherals. This PMIC
supports up to three buck converters, six linear regulators, RTC supply and coin-cell charger. i.MX6UL/i.MX6ULL CPU’s
I2C1 interface is used for PMIC programming. I2C address for PMIC is 0x08.
2.5 Memory
2.5.1 DDR3L SDRAM
i.MX6UL/i.MX6ULL SODIMM SOM by default supports 256MB DDR3L RAM memory in 16bit mode. To support this, it
uses one 256MB DDR3L SDRAM IC. This device operates at 1.35V voltage level. DDR3L IC is physically located on
topside of the SODIMM SOM. The RAM size can be expandable up to maximum of 1GB.
2.5.2 NAND Flash
The i.MX6UL/i.MX6ULL SODIMM SOM supports 256MB NAND Flash as default boot device. This is connected to GPMI
controller of the i.MX6UL/i.MX6ULL CPU and operates at 3.3 Voltage level. The NAND flash memory is physically
located on topside of the SODIMM SOM. The NAND Flash size is expandable.

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2.6 SODIMM PCB Edge Connector
i.MX6UL/i.MX6ULL SODIMM SOM Supports JEDEC Physical Standard 200pin DDR SO-DIMM PCB edge connector for
interfaces expansion. The interfaces which are available at SODIMM Edge connector are explained in the following
sections.
Figure 4: SODIMM PCB Edge Connector
Number of Pins - 200
Connector Part - Not Applicable (On Board PCB Edge connector)
Mating Connector - 1473005-1 from TE Connectivity
Important Note: Some of the interfaces mentioned in the following section are subject to available based on the
i.MX6UL/i.MX6ULL CPU device version used in the SODIMM SOM. For more details, refer i.MX6UL/i.MX6ULL documents
from NXP or contact iWave.

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2.6.1 UART Interface
i.MX6UL/i.MX6ULL SODIMM SOM supports four UART interface on SODIMM Edge connector in which one for Debug
UART interface and other three for Data UART interface. i.MX6UL/i.MX6ULL CPU’s UART1 controller is used for Debug
UART interface and UART2, UART3 & UART5 controller is used for Data UART interface on SODIMM Edge connector.
Also i.MX6UL/i.MX6ULL SODIMM SOM supports hardware flow control for request to send and clear to send signals
on UART5 interface.
i.MX6UL/i.MX6ULL CPU UART controller supports Serial RS-232NRZ mode, 9-bit RS-485 mode and IrDA mode. It is
compatible with High-speed TIA/EIA-232-F (up to 5.0 Mbit/s) with auto baud rate detection (up to 115.2 Kbit/s). It
supports 7 or 8 data bits for RS-232 characters (9 bit RS-485 format), 1 or 2 stop bits and programmable parity (even,
odd, and no parity).
For more details, refer SODIMM Edge connector pins 117 & 118 for Debug UART, pins 98 & 99 for UART2 interface,
pins 7 & 9 for UART3 interface and pins 38, 75, 102 & 103 for UART5 interface on Table 5.
2.6.2 CAN Interface
i.MX6UL/i.MX6ULL SODIMM SOM supports two CAN interfaces on SODIMM Edge connector. CPU’s FLEXCAN1 and
FLEXCAN2 module is used for CAN interface which supports CAN protocol according to the CAN 2.0B protocol
specification. It supports programmable bit rate up to 1 Mb/sec with both standard and extended message frames.
Also it supports 64 Message Buffers. To connect external CAN module, it is necessary to add transceiver in between.
For more details, refer SODIMM Edge connector pins 176 & 178 for CAN1 interface and pins 175 & 177 for CAN2
interface on Table 5.
2.6.3 SD Interface
i.MX6UL/i.MX6ULL SODIMM SOM supports one SD interface port on SODIMM Edge connector. CPU’s uSDHC1
controller is used for SD interface which is fully compliant with SD Memory Card Specifications v3.0 including extended-
capacity SDHC cards. It supports 1-bit or 4-bit transfer mode for SD and SDIO cards up to UHS-I SDR104 mode.
For more details, refer SODIMM Edge connector pins 105, 107 to 109, 111, 112 & 114 on Table 5.
2.6.4 Parallel RGB Display Interface
i.MX6UL/i.MX6ULL SODIMM SOM supports one 24bpp Parallel RGB display interface on SODIMM Edge connector.
i.MX6UL/i.MX6ULL CPU’s eLCDIF controller is used for display interface which supports upto 24bit data bus
(8bits/colour) with up to WXGA (1366x768) resolution at 60Hz. Also CPU’s pixel/image processing engine (PXP) is used
to perform image processing on image/video buffers before sending to an LCD display,.
For more details, refer SODIMM Edge Connector pins 143 to 146 & 148 to 174 on Table 5.

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2.6.5 Parallel Camera Interface
i.MX6UL/i.MX6ULL SODIMM SOM supports one 8bit camera interface on SODIMM Edge Connector.
i.MX6UL/i.MX6ULL CPU’s CSI parallel port is used for camera interface which provides direct connectivity to most
relevant CMOS sensors and CCIR656 video interface. The sensor is the master of the pixel clock (PIXCLK) &
synchronization signals where synchronization signals can be received using dedicated control signals method (HSYNC
& VSYNC) or controls embedded in data stream method (CCIR.656 protocol).
For more details, refer SODIMM Edge connector pins 62, 63, 66, 70, 93, 104, 110, 119 to 123 on Table 5.
2.6.6 I2S Audio Interface
i.MX6UL/i.MX6ULL SODIMM SOM supports one SAI audio interface port on SODIMM Edge connector.
i.MX6UL/i.MX6ULL CPU’s synchronous audio interface (SAI) supports full-duplex serial interfaces with frame
synchronization such as I2S, AC97, TDM, and codec/DSP interfaces. The SAI transmitter and receiver support
asynchronous free-running bit clocks that can be generated internally from an audio master clock or supplied
externally. Also, the SAI transmitter and receiver can be configured to operate with synchronous bit clock and frame
sync.
For more details, refer SODIMM Edge connector pins 61, 64, 67, 89 & 90 on Table 5.
Important Note: Since Audio and JTAG interface signals are multiplexed in same pins on i.MX6UL/i.MX6ULL CPU, these
pins are connected to two places in SODIMM Edge connector and either one interface only can be used at a time.
2.6.7 JTAG Interface
i.MX6UL/i.MX6ULL SODIMM SOM supports one JTAG interface on SODIMM Edge Connector. i.MX6UL/i.MX6ULL CPU
implements JTAG Security modes internal to System JTAG Controller. The System JTAG Controller provides debug and
test control with the maximum security. The test access port is designed to support features compatible with the IEEE
Standard 1149.1 v2001 (JTAG). The SJC module of the processor provides the bridge between external development
and test instrumentation and the internal JTAG-accessible debug and test resources.
For more details, refer SODIMM Edge connector pins 191, 193, 195, 197 &199 on Table 5.
Important Note: Since Audio and JTAG interface signals are multiplexed in same pins on i.MX6UL/i.MX6ULL CPU, these
pins are connected to two places in SODIMM Edge connector and either one interface only can be used at a time.

REL1.2
Page 20 of 55
i.MX6UL/i.MX6ULL SODIMM SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.6.8 USB 2.0 OTG Interface
i.MX6UL/i.MX6ULL SODIMM SOM supports two High Speed USB 2.0 OTG interfaces (USB1 & USB2) on SODIMM Edge
connector. i.MX6UL/i.MX6ULL CPU’s USB Controller which has two independent USB On-The-Go (OTG) controller
cores are used for USB OTG interface. Each USB controller core can operate in High Speed operation (480 Mbps), Full
Speed operation (12 Mbps) and Low Speed operation (1.5 Mbps). Also it supports two integrated USB 2.0 PHY
macrocells provides a standard UTM interface to connect directly to a USB connector.
For more details, refer SODIMM Edge connector pins 74, 76, 77, 78, 81, 83 & 200 for USB OTG1 interface and pins 39,
140, 141, 188 & 190 for USB OTG2 interface on Table 5.
Note: Only USB1 interface can be used in i.MX6UL/i.MX6ULL Serial Downloader Boot Mode and USB2 cannot be used.
2.6.9 Dual 10/100Mbps Ethernet
i.MX6UL/i.MX6ULL SODIMM SOM supports two 10/100Mbps Ethernet interfaces on SODIMM Edge connector through
ENET1 and ENET2 interface. The MAC is integrated in the CPU and connected to the external Ethernet PHY on SOM.
Since MAC and PHY are supported on SOM itself, only Magnetics are required on the carrier board. i.MX6UL/i.MX6ULL
SODIMM SOM also supports Link and Speed indication LED control signals to SODIMM Edge.
i.MX6UL/i.MX6ULL SODIMM SOM supports two “KSZ8081RNBI” Ethernet PHY from Micrel. These PHY’s are interfaced
with CPU using ENET1 and ENET2 interface correspondingly and works at 3.3V IO voltage level. Since this PHY doesn’t
require center tap supply to the magnetics, CTREF voltage to SODIMM Edge is not supported on SOM. It is
recommended that center tap pins of magnetics should be separated from one another and connected through
separate 0.1uF common mode capacitors to ground. The below table provides the compatible magnetics
recommended by PHY Manufacturer.
Table 3: Compatible Magnetics
Part Description
Part Number
Manufacturer
Temperature
RJ45 Magjack with Green, Orange –LED’s.
0821-1X1T-36-F
Bel Fuse
-40°C to 85°C
RJ45 Magjack with Green, Yellow –LED’s.
SI-46001-F
Bel Fuse
-40°C to 85°C
RJ45 Magjack with Green, Yellow –LED’s.
HFJ11-E2450E-L12RL
Halo Electronics
-40°C to 85°C
RJ45 Magjack with Green, Yellow –LED’s.
JX0011D21BNL
Pulse Electronics
-40°C to 85°C
For more details, refer SODIMM Edge connector pins 2, 4, 6, 8, 11 & 12 for USB ENET1 interface and pins 30, 33 to 37
& 42 to 45 for ENET2 interface on Table 5.
Important Note: ENET2 interface is connected to On SOM Ethernet PHY and also optionally connected from CPU to
SODIMM edge connector. If ENET2 Ethernet PHY is not used on SOM, the same signals which are optionally connected
to SODIMM edge can be used for RMII interface or UART interface (3ports) or Keypad (4x4) interface. Please contact
iWave for more details on this support.