iWave iW-RainboW-G20M Installation manual

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RZ/G1M/G1N Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
iW-RainboW-G20M
RZ/G1M, RZ/G1N Qseven SOM
Hardware User Guide

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RZ/G1M/G1N Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Document Revision History
Document Number
iW-PREWZ-UM-01-R4.0-REL1.3-Hardware
Revision
Date
Description
1.0
09th Apr 2016
Offical Release Version
1.1
22nd Jun 2016
•PCIe reset GPIO number is corrected in section 2.6.3
•I2C interface pullup value is changed to 1K in Table 4 Qseven pins 60, 62, 66 & 68
•Qseven Pin 79 is changed from NC to USB1_OVC in Table 4
•Power IN connector BOM in Table 10 and correpsonding silk screen in Error!
Reference source not found. are updated
•IOMUX pin information are corrected in Table 11 for Qseven pins 64,66,68,70,72,
74,76,78,79,112 & 158
•Orderble Part Number is updated in Table 18
•Non substantive changes throughout the document
1.2
18th Nov 2016
•Section 2.4.2, Section 2.6.1 and Table 4 are updated.
•Section 2.12 is newly added.
•Non substantive changes throughout the document
1.3
29th Jan 2019
•Substantive changes throughout the document with respect to RZ/G1M, RZ/G1N
R5.0 SOM
PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the intended recipient(s). Do
not read this document if you are not the intended recipient. Any review, use, distribution or disclosure by others is
strictly prohibited. If you are not the intended recipient (or authorized to receive for the recipient), you are hereby
notified that any disclosure, copying distribution or use of any of the information contained within this document is
STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.”

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iWave Systems Technologies Pvt. Ltd.
Disclaimer
iWave Systems reserves the right to change details in this publication including but not limited to any Product
specification without notice.
No warranty of accuracy is given concerning the contents of the information contained in this publication. To the
extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by iWave
Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or
inaccuracies in this document.
CPU and other major components used in this product may have several silicon errata associated with it. Under no
circumstances, iWave Systems shall be liable for the silicon errata and associated issues.
Trademarks
All registered trademarks, product names mentioned in this publication are the property of their respective owners
and used for identification purposes only.
Certification
iWave Systems Technologies Pvt. Ltd. is an ISO 9001:2015 Certified Company.
Warranty & RMA
Warranty support for Hardware: 1 Year from iWave or iWave's EMS partner.
For warranty terms, go through the below web link,
http://www.iwavesystems.com/support/warranty.html
For Return Merchandise Authorization (RMA), go through the below web link,
http://www.iwavesystems.com/support/rma.html
Technical Support
iWave Systems technical support team is committed to provide the best possible support for our customers so that
our Hardware and Software can be easily migrated and used.
For assistance, contact our Technical Support team at,
Email : [e-mail]
Website : www.iwavesystems.com
Address : iWave Systems Technologies Pvt. Ltd.
# 7/B, 29th Main, BTM Layout 2nd Stage,
Bangalore, Karnataka,
India –560076

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iWave Systems Technologies Pvt. Ltd.
Table of Contents
1. INTRODUCTION ............................................................................................................................................7
1.1 Purpose .............................................................................................................................................................7
1.2 Qseven SOM Overview .....................................................................................................................................7
1.3 List of Acronyms................................................................................................................................................7
1.4 Terminlogy Description.....................................................................................................................................9
1.5 References ........................................................................................................................................................9
1.6 Important Note ...............................................................................................................................................10
2. ARCHITECTURE AND DESIGN....................................................................................................................... 11
2.1 RZ/G1M/G1N QsevenSOM Block Diagram .....................................................................................................11
2.2 RZ/G1M/G1N QsevenSOM Features ..............................................................................................................12
2.3 RZ/G1M/G1N CPU...........................................................................................................................................14
2.4 Memory...........................................................................................................................................................15
2.4.1 DDR3L SDRAM.............................................................................................................................................15
2.4.2 SPI NOR Flash ..............................................................................................................................................15
2.4.3 eMMC Flash ................................................................................................................................................16
2.4.4 Micro SD Slot...............................................................................................................................................16
2.5 RTC Controller.................................................................................................................................................16
2.6 Qseven PCB Edge Connector...........................................................................................................................17
2.6.1 Gigabit Ethernet..........................................................................................................................................18
2.6.2 USB3.0 Host Interface .................................................................................................................................18
2.6.3 PCIe Interface ..............................................................................................................................................19
2.6.4 SATA Interface (Optional)............................................................................................................................19
2.6.5 USB 2.0 OTG Interface.................................................................................................................................20
2.6.6 USB 2.0 Host Interface ................................................................................................................................20
2.6.7 SD Interface.................................................................................................................................................20
2.6.8 LVDS Display Interface ................................................................................................................................21
2.6.9 I2S Audio Interface ......................................................................................................................................21
2.6.10 DATA UART Interface ..................................................................................................................................22
2.6.11 CAN Interface ..............................................................................................................................................22
2.6.12 SPI Interface ................................................................................................................................................22
2.6.13 I2C Interface................................................................................................................................................23
2.6.14 PWM Interface ............................................................................................................................................23
2.6.15 GPIO Interface.............................................................................................................................................23
2.6.16 Manufacturing/Debug UART Interface.......................................................................................................24
2.6.17 Power Input.................................................................................................................................................24
2.6.18 Power Control Signal...................................................................................................................................24
2.6.19 Reset Signal.................................................................................................................................................24
2.7 Expansion Connector1 Interfaces ...................................................................................................................38
2.7.1 Parallel Camera Interface............................................................................................................................39
2.7.2 Parallel RGB Display Interface.....................................................................................................................40
2.7.3 Data UART Interface ...................................................................................................................................40

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2.8 Expansion Connector2 Interfaces ...................................................................................................................46
2.8.1 I2S Audio Interface ......................................................................................................................................47
2.8.2 CAN Interface ..............................................................................................................................................47
2.8.3 SPI Interface ................................................................................................................................................47
2.8.4 Data UART Interface ...................................................................................................................................48
2.8.5 PWM Interface ............................................................................................................................................48
2.8.6 Memory Bus Interface.................................................................................................................................48
2.9 Other Features................................................................................................................................................54
2.9.1 JTAG Header................................................................................................................................................54
1.1.1 SPI Programming Header............................................................................................................................56
2.10 Optional Features............................................................................................................................................57
2.10.1 Power IN Connector ....................................................................................................................................57
2.11 RZ/G1M/G1N PinMultiplexing on Qseven Edge and Expansion Connectors..................................................58
2.12 RZ/G1M CPU Reference Schematic ................................................................................................................65
3. TECHNICAL SPECIFICATION.......................................................................................................................... 70
3.1 Electrical Characteristics .................................................................................................................................70
3.1.1 Power Input Requirement ...........................................................................................................................70
3.1.2 Power Input Sequencing..............................................................................................................................71
3.1.3 Power Consumption ....................................................................................................................................72
3.2 EnvironmentalCharacteristics.........................................................................................................................73
3.2.1 Environmental Specification........................................................................................................................73
3.2.2 Heat Spreader .............................................................................................................................................73
3.2.3 RoHS Compliance ........................................................................................................................................74
3.2.4 Electrostatic Discharge................................................................................................................................74
3.3 MechanicalCharacteristics..............................................................................................................................75
3.3.1 Qseven SOM Mechanical Dimensions.........................................................................................................75
3.3.2 Guidelines to insert the Qseven SOM into Carrier board ............................................................................77
4. ORDERING INFORMATION .......................................................................................................................... 78
5. APPENDIX II................................................................................................................................................ 79
5.1 RZ/G1M/G1N Qseven SOM Development Platform.......................................................................................79

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List of Figures
Figure 1: RZ/G1M/G1N Qseven SOM Block Diagram .....................................................................................................11
Figure 2: RZ/G1M Simplified Block Diagram...................................................................................................................14
Figure 3: SPI NOR Flash...................................................................................................................................................15
Figure 4: Micro SD Connector.........................................................................................................................................16
Figure 5: Qseven PCB Edge Connector............................................................................................................................17
Figure 6: Expansion Connector1 .....................................................................................................................................38
Figure 7: Expansion Connector2 .....................................................................................................................................46
Figure 8: JTAG Header.....................................................................................................................................................54
Figure 9: SPI Flash Programming Header........................................................................................................................56
Figure 10: 2Pin Power Connector ...................................................................................................................................57
Figure 11: Qseven SOM Power Sequence.......................................................................................................................71
Figure 12: Heat Spreader Dimensions ............................................................................................................................74
Figure 13: Mechanical dimension of Qseven SOM- Top View........................................................................................75
Figure 14: Mechanical dimension of RZ/G1M/G1N Qseven SOM- Bottom View...........................................................76
Figure 15: Mechanical dimension of RZ/G1M/G1N Qseven SOM- Side View ................................................................76
Figure 16: Qseven Module Insertion procedure.............................................................................................................77
Figure 17: RZ/G1M/G1N Qseven SOM Development Platform with Add on Module....................................................79
List of Tables
Table 1: Acronyms & Abbreviations..................................................................................................................................7
Table 2: Terminology ........................................................................................................................................................9
Table 3: Compatible Magnetics ......................................................................................................................................18
Table 4: 230-Pin PCB Edge Connector Pin Assignment...................................................................................................25
Table 5: Parallel Camera Interface Pin Assignment on Expansion connector1 ..............................................................39
Table 6: Expansion Connector1 Pin Assignment.............................................................................................................41
Table 7: Expansion Connecto2 Pin Assignment ..............................................................................................................49
Table 8: JTAG Header Pin Assignment ............................................................................................................................55
Table 9: SPI Header.........................................................................................................................................................56
Table 10: Power IN Connector - BOM.............................................................................................................................57
Table 11: RZ/G1M/G1N CPU IOMUX for Qseven Edge Connector interfaces ................................................................58
Table 12: RZ/G1M/G1N CPU IOMUX for Expansion Connector1 interfaces...................................................................61
Table 13: RZ/G1M/G1N CPU IOMUX for Expansion Connector2 interfaces...................................................................63
Table 14: Power Input Requirement...............................................................................................................................70
Table 15: Power Sequence Timing..................................................................................................................................71
Table 16: Power Consumption........................................................................................................................................72
Table 17: Environmental Specification ...........................................................................................................................73
Table 18: Orderable Product Part Numbers ...................................................................................................................78

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iWave Systems Technologies Pvt. Ltd.
1. INTRODUCTION
1.1 Purpose
This document is the Hardware User Guide for the RZ/G1M, RZ/G1N Qseven System On Module based on the
Renesas’s RZ/G1M or RZ/G1N Application processor. This board is fully supported by iWave Systems Technologies Pvt.
Ltd. This Guide provides detailed information on the overall design and usage of the RZ/G1M, RZ/G1N Qseven System
On Module from a Hardware Systems perspective.
1.2 Qseven SOM Overview
The RZ/G1M, RZ/G1N Qseven SOM is an extension of RZ/G1M or RZ/G1N CPU. The Qseven concept is an off-the-shelf,
multi-vendor, Single-Board-Computer that integrates all the core components of a common PC and is mounted onto
an application specific carrier board. Qseven modules have a standardized form factor of 70mm x 70mm and have
specified pin outs based on the high speed MXM system connector that has a standardized pin out regardless of the
vendor. A single ruggedized MXM connector provides the carrier board interface to carry all the I/O signals to and
from the Qseven module.
1.3 List of Acronyms
The following acronyms will be used throughout this document.
Table 1: Acronyms & Abbreviations
Acronyms
Abbreviations
ARM
Advanced RISC Machine
BOM
Bill of Material
BPP
Bits Per Pixel
BSP
Board Support Package
CAN
Controller Area Network
CMOS
Complementary Metal-Oxide Semiconductor
CPU
Central Processing Unit
DDR3
Double Data Rate 3
eMMC
Enhanced Multi Media Card
GB
Giga Byte
Gbps
Gigabits per sec
GPIO
General Purpose Input Output
HSCIF
High Speed Serial Communication Interface with FIFO
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
JTAG
Joint Test Action Group
Kbps
Kilobits per second
LCD
Liquid Crystal Display

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Acronyms
Abbreviations
MAC
Media Access Controller
MB
Mega Byte
Mbps
Megabits per sec
MHz
Mega Hertz
MMCIF
Multi-media card interface
MSIOF
Clock-Synchronized Serial Interface with FIFO
PCB
Printed Circuit Board
PWM
Pulse Width Modulation
QSPI
Quad Serial Peripheral Interface
RTC
Real Time Clock
SCIF
Serial Communication Interface with FIFO
SD
Secure Digital
SDHI
SD Card Host Interface
SSI
Serial Sound Interface
SDRAM
Synchronous Dynamic Random Access Memory
SOM
System On Module
UART
Universal Asynchronous Receiver/Transmitter
USB
Universal Serial Bus
USB OTG
USB On The Go

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1.4 Terminlogy Description
In this document, wherever Signal Type is mentioned, below terminology is used.
Table 2: Terminology
Terminology
Description
I
Input Signal
O
Output Signal
IO
Bidirectional Input/output Signal
CMOS
Complementary Metal Oxide Semiconductor Signal
DIFF
Differential Signal
LVDS
Low Voltage Differential Signal
OD
Open Drain Signal
OC
Open Collector Signal
Power
Power Pin
PU
Pull Up
PD
Pull Down
NA
Not Applicable
NC
Not Connected
Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes
the pull-ups or pull-downs implemented On-SOM.
1.5 References
•RZ/G1M/G1N CPU Hardware User Manuals
•Qseven® Specification Version 2.0
•Qseven-Spec_2.0_SGET_errata_sheet_E2.00-001
•Qseven® Design Guide

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1.6 Important Note
In this document, wherever “RZ/G1M/G1N” is mentioned, it is always relates to both RZ/G1M and RZ/G1N CPU unless
otherwise specified.
RZ/G1M/G1N Qseven Edge connector signal name mentioned in Table 4 is followed as per below format for easy
understanding.
•If CPU pin has multiplexing option and selected particular function, then the signal name is mentioned as
“Selected Function Name (GPIO Number)”
Example: MSIOF2_SCK(GP1_13)
In this signal, MSIOF2_SCK is the functionality which we are using and GP1_13 is the GPIO number.
•If CPU pin has multiplexing option and selected as GPIO function, then the signal name is mentioned as
“GPIO_Functionality Description(GPIO Number)”
Example: GPIO_USBOTG_ID(GP1_11)
In this signal, USBOTG_ID is the GPIO functionality which we are using and GP1_11 is the GPIO number.
•If CPU pin doesn’t have multiplexing option, then the signal name is mentioned as,
“Function name”
Example: I2C5_SDA
In this signal, functionality which we are using I2C5_SDA
Note: The above naming is not applicable for other signals which are not connected to CPU.

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2. ARCHITECTURE AND DESIGN
This section provides detailed information about the RZ/G1M/G1N Qseven SOM features and Hardware architecture
with high level block diagram. Also this section provides detailed information about Qseven edge connector &
Expansion connector’s pin assignment and usage.
2.1 RZ/G1M/G1N QsevenSOM Block Diagram
iW-RainboW-G20M - RZ/G1M, RZ/G1N Qseven SOM Block Diagram
¹ PCIe is supported by default. SATA1 is not supported by default.
² USB3.0 is supported by default. SATA0 is not supported by default.
³ SCIF4 cannot be supported If VI1 16bit camera is used.
CPU
RZ/G1M,
RZ/G1N
DDR3L -1GB
(Upgradable)
SPI Flash - 2MB
(Upgradable)
eMMC - 4GB
(Upgradable)
QSEVEN
PCB Edge
Connector
(230Pin)
USB3.0 x 1²
LVDS x 1
Gigabit
Ethernet
GMII x 1
SDHC (4bit) x 1
I2C x 2
SPI x 1 (2 Chip selects)
CAN x 1
8 GPIOs, Status & Control Signals
PCIe/
SATA1
USB3.0/
SATA0
LVDS-DU0
EtherAVB
SDHI2
I2C2,
I2C5
MSIOF2
CAN0
GPIOs
MMC (8bit)
SPI
DDR3 (32bit)
Micro SD
Connector
SD (4bit)
Expansion
Connector1
(80Pin header)
Gigabit
Ethernet PHY
DBSC3–CH0
QSPI
MMC/
SDHI3
SDHI0
I2S x 1
SSI0/
SSI1
SCIF0
LCD (24bpp) x 1 & Camera (8bit) x 1
(or) Camera (16bit) x 1 DU1,
VI1
SSI3/
SSI4
LBSC
SSI/I2S x 1
JTAG
Memory Bus (16bit Sync/Async)
UART x 1
2Pin Power In
(Optional)
JTAG
Power to
Peripherals
5V
Debug
VI0,VI2
Camera (24bit) x 1 (or) Camera (8bit) x 2
JTAG
(20 Pin Header)
On-Board
Regulators
Dual SPDT
Switch IC
(Optional)
Expansion
Connector2
(80Pin header) MSIOF1/
HSCIF1
SPI x 1 (or) UART (with CTS & RTS) x 1
CAN1
CAN x 1
DDR3 (32bit) DBSC3–CH1
PWM x 2
PWM3,
PWM5
UART (with CTS & RTS) x 1
SCIFB1
USB1
SCIF1
UART x 1
PWM x 1
PWM1
SCIF4³
UART x 1
USB2.0 HUB
(2 Ports)
USB Host x 2
USB OTG
USB2.0 OTG x 1
USB0
RTC Controller I2C2
SPI
Programming
Header
PCIe x 1¹
SATA x 1¹
VRTC
VRTC
Note: Green Font blocks are not supported in RZ/G1N CPU
Figure 1: RZ/G1M/G1N Qseven SOM Block Diagram

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2.2 RZ/G1M/G1N QsevenSOM Features
The RZ/G1M/G1N Qseven SOM supports the following features.
CPU
•Renesas’RZ/G1M or RZ/G1N Dual Core ARM™ Cortex-A15 CPU @ 1.5GHz
Memory
•DDR3L SDRAM - 1GB (Expandable)
•SPI Flash - 2MB (Expandable)
•eMMC Flash - 8GB (Expandable)
•Micro SD slot
Other On-SOM Features
•Gigabit Ethernet PHY Transceiver
•USB 2.0 High Speed 2-Port Hub
•RTC controller
•JTAG Header
•SPI Programming Header
Qseven PCB Edge Interfaces
•Gigabit Ethernet x 1 Port (through On-SOM Gigabit Ethernet PHY transceiver)
•USB3.0 Host x 1 Port 1,3
•USB 2.0 OTG x 1 Port
•USB 2.0 Host x 2 Ports (through On-SOM USB 2.0 High Speed 2-port Hub)
•PCIe x 1 Port2,3
•SATA x 1 Port (Optional) 1,2,3
•SD (4bit) x 1 Port
•LVDS x 1 Port
•SSI/I2S (Audio Interface) x 1 Port
•Debug UART
•Data UART (with CTS & RTS) x 1 Port
•CAN x 1 Port
•SPI x 1 Port (with 2 Chip selects)
•I2C x 2 Ports
•PWM x 2 Ports
•8 GPIO’s

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Expansion Connector1 Interfaces
•Parallel Camera x 3 Ports (VIN0 –8bit/16bit/24bit, VIN1 –8bit/16bit, VIN2 –8bit) 4,5
•Parallel LCD (24bpp RGB) x 1 Port 4
•Data UART x 1 Port 6
Expansion Connector2 Interfaces
•SSI/I2S x 1 Port
•CAN x 1 Port
•SPI x 1 Port 7
•Data UART x 2 Ports 7
•PWM x 1 Port
•Memory Bus (16bit Sync/Async)
General Specification
•Power Supply : 5V,1.2A
•Power IN connector for Standalone usage (Optional)
•Form Factor :70mm x 70mm (Qseven® Specification Version 2.0)
1 In RZ/G1M CPU, USB3.0 and SATA0 are multiplexed in same pins and so either one interface only can be used at a
time. By default, USB3.0 is supported.
2 In RZ/G1M CPU, PCIe and SATA1 are multiplexed in same pins and so either one interface only can be used at a time.
By default, PCIe is supported.
3In RZ/G1N CPU, USB3.0, PCIe & SATA are multiplexed in same pins and so either one interface only can be used at a
time. By default USB3.0 is supported.
4 In RZ/G1M/G1N CPU, DU1 & VIN1 (some pins) are multiplexed in same pins and so DU1 cannot be supported when
VIN1 is supported in 16bit mode. If VIN1 is supported in 8bit mode, then DU1 also can be supported.
5 In RZ/G1M/G1N CPU, VIN0 & VIN2 are multiplexed in same pins and so VIN2 cannot be supported when VIN0 is
supported in 16bit/24bit mode. If VIN0 is supported in 8bit mode, then VIN2 also can be supported in 8bit mode.
6 In RZ/G1M/G1N CPU, SCIF4 & VIN1 (some pins) are multiplexed in same pins and so SCIF4 cannot be supported when
VI1 is supported in 16bit mode. If VIN1 is supported in 8bit mode, then SCIF4 also can be supported.
7 In RZ/G1M/G1N CPU, MSIOF1 and HSCIF1 are multiplexed in same pins and so MSIOF1 cannot be supported when
HSCIF1is supported with Hardware flow control signals. If HSCIF1is supported without Hardware flow control signals,
then MSIOF1 also can be supported.

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2.3 RZ/G1M/G1N CPU
The RZ/G1M/G1N Qseven SOM is based on Renesas’s RZ/G1M or RZ/G1N CPU with built-in dual ARM™ Cortex-A15
Microprocessor core which can operate up to 1.5 GHz/core. The Block Diagramof RZ/G1M CPU from Renesas’s website
is shown below for reference.
Figure 2: RZ/G1M Simplified Block Diagram
Note: Please refer the latest RZ/G1M/G1N Datasheet & Reference Manual for Electrical characteristics of RZ/G1M/G1N
CPU which may be revised from time to time.

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2.4 Memory
2.4.1 DDR3L SDRAM
The RZ/G1M/G1N Qseven SOM supports 1GB DDR3L RAM memory by default. This is connected to CPU in 32bit x 2ch
mode where it uses four 256MB DDR3L-SDRAM ICs. This device operates at 1.35V voltage level. DDR3L-SDRAM ICs are
physically located on either side of the SOM. The RAM size can be expandable up to maximum of 4GB. For customised
DDR3L memory based SOM contact iWave support team
Note: In RZ/G1N SOM, DDR3L-SDRAM is connected in 32bit x 1ch mode where it uses two 512MB DDR3L-SDRAM ICs
by default.
2.4.2 SPI NOR Flash
The RZ/G1M/G1N Qseven SOM supports 2MB SPI NOR Flash as default boot device. This is connected to QSPI
controller of the RZ/G1M/G1N CPU and operates at 3.3 Voltage level. While RZ/G1M/G1N booting, boot program in
the on-chip ROM starts up the QSPI and SYS-DMAC channel 1, and transfers the loader program previously stored in
the SPI Flash to the on-chip RAM via the QSPI controller. After loader program is transferred, the program
automatically jumps to the top address of the loader program. The SPI flash memory (U1) is physically located on top
side of the Qseven SOM.
Figure 3: SPI NOR Flash

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2.4.3 eMMC Flash
The RZ/G1M/G1N Qseven SOM supports 8GB eMMC Flash memory as mass storage. eMMC is directly connected to
the MMCIF controller of the RZ/G1M/G1N CPU which supports MMC 4.41 and operating at 3.3V Voltage level. The
eMMC flash memory is physically located on bottom side of the Qseven SOM. The memory size of the eMMC Flash
can be expandable.
2.4.4 Micro SD Slot
The RZ/G1M/G1N Qseven SOM supports Micro SD slot which can be used to connect Micro SD card as Mass storage.
Micro SD card connector (J3) is directly connected to the SDHI0 controller of the RZ/G1M/G1N CPU. It also supports
card detect feature Through RZ/G1M/G1N GPIO “GP7_11”. The main power to Micro SD Card Connector is 3.3 Voltage.
The RZ/G1M/G1N Qseven SOM optionally supports configurable IO voltage levels for SDHI0 lines which can be
controlled through CPU GPIO GP1_13. If GP1_13 is set to low, then 1.8V IO level is selected for SDHI0 lines. If GP1_13
is set to high, then 3.3V IO level is selected for SDHI0 lines. Micro SD Connector (J3) is physically located on topside of
the Qseven SOM as shown below.
Figure 4: Micro SD Connector
2.5 RTC Controller
The RZ/G1M/G1N Qseven SOM supports external RTC Controller “PCF85263AT/AJ” On-SOM for Real time clock
support. This external RTC Controller is connected to the RZ/G1M/G1N CPU through I2C2 Interface and operates at
3.3V voltage level. In SOM power off condition, this device will take power from Qseven Edge (VCC_RTC) coin cell
power input (Pin 193) and continues to keep the current time. The interrupt output from RTC controller is connected
to RZ/G1M/G1N GPIO”GP1_23”.

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2.6 Qseven PCB Edge Connector
The RZ/G1M/G1N Qseven SOM PCB edge connector has standard pin out as per Qseven Specification 2.0. The
interfaces which are available at 230pin Qseven Edge connector (J5) are explained in the following sections.
Figure 5: Qseven PCB Edge Connector
Number of Pins - 230
Connector Part - Not Applicable (On Board PCB Edge connector)
Mating Connector - IMSA-18010S-230A-GN1 from IRISO
88882-2D0K from Aces
AS0B326-S78N-7F from FOXCONN
CN113-230-0001VE from Yamaichi Electronics

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2.6.1 Gigabit Ethernet
The RZ/G1M/G1N Qseven SOM supports one 100/1000 Mbps Ethernet interface on Qseven Edge connector. The MAC
is integrated in the RZ/G1M/G1N CPU and connected to the external Gigabit Ethernet PHY on SOM. Since MAC and
PHY are supported on SOM itself, only Magnetics are required on the carrier board. RZ/G1M/G1N Qseven SOM also
supports Link and Activity indication LED control signals to Qseven Edge.
The RZ/G1M/G1N Qseven SOM supports “KSZ9031MNX”Ethernet PHY from Microchip. This PHY is interfaced with
RZ/G1M/G1N CPU EthernetAVB and works at 3.3V IO voltage level. Since this PHY doesn’t recommend to connect any
power source to magnetic center tap pins, CTREF voltage to Qseven Edge is not supported on SOM. It is recommended
that center tap pins of magnetics should be separated from one another and connected through separate 0.1uF
common mode capacitors to ground. This PHY has on-chip termination on differential pairs and so no need to add any
termination externally. The below table provides some of the compatible magnetics recommended by the PHY
Manufacturer.
Table 3: Compatible Magnetics
Part Description
Part Number
Manufacturer
Temperature
Gigabit Ethernet Discrete Transformer
TG1G-E001NZRL
HALO
-40°C to 85°C
Gigabit Ethernet Discrete Transformer
HX5008NL
Pulse
-40°C to 85°C
Gigabit Ethernet Discrete Transformer
000-7093-37R-LF1
Wurth
0°C to 70°C
RJ45 Magjack with two Green LED
JK0654219NL
Pulse
0°C to 70°C
RJ45 Magjack with two Green LED
0826-1G1T-23-F
Bel Fuse
0°C to 70°C
For more details, refer Qseven Edge connector pins 3 to 15 on Table 4.
2.6.2 USB3.0 Host Interface
The RZ/G1M/G1N Qseven SOM supports one High Speed USB3.0 host interface on Qseven Edge connector.
RZ/G1M/G1N CPU’s USB3.0 Host Controller is used for USB3.0 interface which is compliant with the Universal Serial
Bus (USB) 3.0 Specifications. It uses AXI Interconnection, which is a System Interface that is based on the AMBA® AXI
Protocol v1.0 Specification. The USB3.0 Host Controller supports Super Speed (5 Gbps), High Speed (480 Mbps), Full
Speed (12 Mbps) and Low Speed (1.5 Mbps). Also, the USB3.0 Host Controller is compliant with Battery Charging
Specification Revision 1.2 and Supports polarity inversion of USB3.0 SS differential data pin pair.
For more details, refer Qseven Edge connector pins 75, 76, 77 & 78 on Table 4.
Note: In RZ/G1M CPU, USB3.0 & SATA0 High speed transceivers are multiplexed in same pins and so either one interface
only can be used at a time. By default, USB3.0 is supported. Please contact iWave if SATA support is required.
Note: In RZ/G1N CPU, PCIe, USB3.0 & SATA High speed transceivers are multiplexed in same pins and so either one
interface only can be used at a time. By default USB3.0 is supported. Please contact iWave if PCIe or SATA support is
required in RZ/G1N CPU based Qseven SOM.

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2.6.3 PCIe Interface
The RZ/G1M Qseven SOM supports one PCI Express Gen2.0 lane on Qseven Edge connector. RZ/G1M CPU’s PCIEC
module with integrated PHY is used for PCIe Interface which can support PCIe Gen2.0 at multiple speeds (2.5GT/s and
5GT/s). RZ/G1M CPU’s PCIe PHY output is connected to Qseven Edge connector PCIe channel 0. 100MHz external clock
oscillator output is connected to CPU & Qseven Edge for PCIe reference clock. Also PCIe wake and PCIe reset are
supported on Qseven Edge connector from RZ/G1M CPU IOs GP5_11 & GP7_19 correspondingly.
For more details, refer Qseven Edge connector pins 155,156,157,158,179,180,181 & 182 on Table 4.
Note: PCIe differential transmitter lines are ac coupled on SOM itself. Also PCIe differential clock lines from external
clock oscillator are having on-chip termination resistors and so no external termination is required.
Note: In RZ/G1M CPU, PCIe & SATA1 High speed transceivers are multiplexed in same pins and so either one interface
only can be used at a time. By default PCIe is supported. Please contact iWave if SATA1 support is required.
Note: In RZ/G1N CPU, PCIe, USB3.0 and SATA High speed transceivers are multiplexed in same pins and so either one
interface only can be used at a time. By default USB3.0 is supported. Please contact iWave if PCIe or SATA support is
required in RZ/G1N CPU based Qseven SOM.
2.6.4 SATA Interface (Optional)
The RZ/G1M/G1N Qseven SOM can optionally support one SATA Gen2 lane on Qseven Edge connector. RZ/G1M/G1N
CPU’s SATA controller with integrated PHY is used for SATA Interface which can support Gen2 transfer rate of 3Gbps
and also backward compatible to Gen1 transfer rate of 1.5Gbps. RZ/G1M/G1N CPU’s SATA PHY output is connected
to Qseven Edge connector SATA channel 0. Also SATA activity LED output is supported on Qseven edge connector from
RZ/G1M/G1N CPU GPIO (GP5_11).
For more details, refer Qseven Edge connector pins 29,31,33,35 & 37 on Table 4.
Note: In RZ/G1M CPU, USB3.0 & SATA0 High speed transceivers are multiplexed in same pins and so either one interface
only can be used at a time. By default USB3.0 is supported. Please contact iWave if SATA support is required.
Note: In RZ/G1M CPU, PCIe & SATA1 High speed transceivers are multiplexed in same pins and so either one interface
only can be used at a time. By default PCIe is supported. Please contact iWave if SATA support is required.
Note: In RZ/G1N CPU, PCIe, USB3.0 and SATA High speed transceivers are multiplexed in same pins and so either one
interface only can be used at a time. By default USB3.0 is supported. Please contact iWave if PCIe or SATA1 support is
required in RZ/G1N CPU based Qseven SOM.

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2.6.5 USB 2.0 OTG Interface
The RZ/G1M/G1N Qseven SOM supports One USB2.0 OTG interface on Qseven Edge connector. RZ/G1M/G1N CPU’s
USB0 OTG controller with integrated PHY is used for OTG interface which supports USB2.0 High-Speed (480
Mbps)/Full-Speed (12 Mbps)/Low-Speed (1.5 Mbps) transfer. RZ/G1M/G1N CPU’s USB0 OTG controller can operate in
Host or Function (Peripheral) mode.
The RZ/G1M/G1N CPU’s USB0 PHY output is directly connected to Qseven Edge connector USB Port1. Also USB VBUS
& USB ID input from Qseven Edge connector is connected to RZ/G1M/G1N CPU’s VBUS & GPIO (GP1_11) pins
correspondingly. USB_DRIVE_VBUS to Qseven Edge connector is connected from RZ/G1M/G1N CPU’s USB0_PWEN pin
for controlling USB0 VBUS power.
For more details, refer Qseven Edge connector pins 56, 91, 92, 93 & 95 on Table 4.
2.6.6 USB 2.0 Host Interface
The RZ/G1M/G1N Qseven SOM supports two USB2.0 Host interface on Qseven Edge connector. To support two USB2.0
Host interfaces, SOM includes two-port USB hub “USB2422” from Microchip. This Hub is interfaced with RZ/G1M/G1N
CPU using USB1 Host controller (with integrated PHY) which supports USB2.0 High-Speed (480 Mbps)/Full-Speed (12
Mbps)/Low-Speed (1.5 Mbps) transfer.
Two port USB hub Outputs are connected to Qseven Edge connector USB Port0 and Port2. Also over current input of
USB Port0 & 1 and USB Port2 from Qseven Edge connector are connected to USB hub OCS1 and OCS2 pins
correspondingly for over current detection.
For more details, refer Qseven Edge connector pins 85, 86, 88, 90, 94 & 96 on Table 4.
2.6.7 SD Interface
The RZ/G1M/G1N Qseven SOM supports one SD interface port on Qseven Edge connector. RZ/G1M/G1N CPU’s SDHI2
controller is used for SD interface. It supports 1-bit or 4-bit transfer mode for SD memory/SDIO and works upto SDR50
class transfer rate at max. 48 Mbytes/s @ 97.5 MHz. RZ/G1M/G1N CPU supports SDIO card detect function & write
protect function and connected from Qseven Edge connector. It also supports SDIO power enable & Status LED output
on Qseven Edge connector and connected from RZ/G1M/G1N GPIOs GP1_16 & GP1_14 correspondingly.
The RZ/G1M/G1N Qseven SOM supports configurable IO voltage levels for SDHI2 lines which can be controlled through
CPU GPIO GP2_30. If GP2_30 is set to low, then 1.8V IO level is selected for SDHI2 lines. If GP2_30 is set to high, then
3.3V IO level is selected for SDHI2 lines.
For more details, refer Qseven Edge connector pins 42 to 51 on Table 4.