iWave iW-RainboW-G21M Installation manual

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RZ/G1H Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
iW-RainboW-G21M
RZ/G1H Qseven SOM
Hardware User Guide

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Document Revision History
Document Number
iW-PREXZ-UM-01-R4.0-REL1.1-Hardware
Revision
Date
Description
1.0
19th Oct 2016
Official Release Version
1.1
23rd May 2018
Updated Release for Production Version SOM
(Substantive changes throughout the document)
PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the intended recipient(s). Do
not read this document if you are not the intended recipient. Any review, use, distribution or disclosure by others is
strictly prohibited. If you are not the intended recipient (or authorized to receive for the recipient), you are hereby
notified that any disclosure, copying distribution or use of any of the information contained within this document is
STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.”

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Disclaimer
iWave Systems reserves the right to change details in this publication including but not limited to any Product
specification without notice.
No warranty of accuracy is given concerning the contents of the information contained in this publication. To the
extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by iWave
Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or
inaccuracies in this document.
CPU and other major components used in this product may have several silicon errata associated with it. Under no
circumstances, iWave Systems shall be liable for the silicon errata and associated issues.
Trademarks
All registered trademarks, product names mentioned in this publication are the property of their respective owners
and used for identification purposes only.
Certification
iWave Systems Technologies Pvt. Ltd. is an ISO 9001:2015 Certified Company.
Warranty & RMA
Warranty support for Hardware: 1 Year from iWave or iWave's EMS partner.
For warranty terms, go through the below web link,
http://www.iwavesystems.com/support/warranty.html
For Return Merchandise Authorization (RMA), go through the below web link,
http://www.iwavesystems.com/support/rma.html
Technical Support
iWave Systems technical support team is committed to provide the best possible support for our customers so that
our Hardware and Software can be easily migrated and used.
For assistance, contact our Technical Support team at,
Email : [e-mail]
Website : www.iwavesystems.com
Address : iWave Systems Technologies Pvt. Ltd.
# 7/B, 29th Main, BTM Layout 2nd Stage,
Bangalore, Karnataka,
India –560076

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Table of Contents
1. INTRODUCTION ............................................................................................................................................7
1.1 Purpose .............................................................................................................................................................7
1.2 Qseven SOM Overview .....................................................................................................................................7
1.3 List of Acronyms................................................................................................................................................7
1.4 Terminlogy Description.....................................................................................................................................9
1.5 References ........................................................................................................................................................9
1.6 Important Note ...............................................................................................................................................10
2. ARCHITECTURE AND DESIGN....................................................................................................................... 11
2.1 RZ/G1H QevenSOM Block Diagram ................................................................................................................11
2.2 RZ/G1H QsevenSOM Features ........................................................................................................................12
2.3 RZ/G1H CPU ....................................................................................................................................................15
2.4 Memory...........................................................................................................................................................16
2.4.1 DDR3 SDRAM ..............................................................................................................................................16
2.4.2 SPI NOR Flash ..............................................................................................................................................16
2.4.3 eMMC Flash ................................................................................................................................................17
2.5 RTC Controller.................................................................................................................................................17
2.6 Qseven PCB Edge Connector...........................................................................................................................18
2.6.1 Gigabit Ethernet..........................................................................................................................................19
2.6.2 USB 3.0 Host Interface ................................................................................................................................20
2.6.3 PCIe Interface ..............................................................................................................................................20
2.6.4 SATA Interface (Optional)............................................................................................................................21
2.6.5 USB 2.0 OTG Interface.................................................................................................................................21
2.6.6 USB 2.0 Host Interface ................................................................................................................................21
2.6.7 SD Interface.................................................................................................................................................22
2.6.8 LVDS Display Interface ................................................................................................................................22
2.6.9 HDMI Interface (Optional)...........................................................................................................................23
2.6.10 I2S Audio Interface ......................................................................................................................................23
2.6.11 DATA UART Interface ..................................................................................................................................24
2.6.12 CAN Interface ..............................................................................................................................................24
2.6.13 SPI Interface ................................................................................................................................................24
2.6.14 I2C Interface................................................................................................................................................25
2.6.15 PWM Interface ............................................................................................................................................25
2.6.16 GPIO Interface.............................................................................................................................................25
2.6.17 Manufacturing/Debug UART Interface.......................................................................................................26
2.6.18 Power Input.................................................................................................................................................26
2.6.19 Power Control Signal...................................................................................................................................26
2.6.20 Reset Signal.................................................................................................................................................26
2.7 Expansion Connector1 Interfaces ...................................................................................................................42
2.7.1 Parallel Camera Interfaces..........................................................................................................................43
2.8 Expansion Connector2 Interfaces ...................................................................................................................50
2.8.1 10/100Mbps Ethernet .................................................................................................................................51

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2.8.2 I2S Audio Interface ......................................................................................................................................51
2.8.3 Data UART Interface ...................................................................................................................................52
2.8.4 CAN Interface ..............................................................................................................................................52
2.8.5 SPI Interface ................................................................................................................................................53
2.8.6 PWM Interface ............................................................................................................................................53
2.9 Other Features ................................................................................................................................................60
2.9.1 JTAG Header................................................................................................................................................60
2.9.2 SPI Programming Header............................................................................................................................62
2.9.3 Power IN Connector (Optional) ...................................................................................................................63
2.10 RZ/G1H Pin Multiplexing on Qseven Edge and Expansion Connectors ..........................................................64
2.11 RZ/G1H CPU Reference Schematic .................................................................................................................74
3. TECHNICAL SPECIFICATION.......................................................................................................................... 79
3.1 Electrical Characteristics .................................................................................................................................79
3.1.1 Power Input Requirement ...........................................................................................................................79
3.1.2 Power Input Sequencing..............................................................................................................................80
3.1.3 Power Consumption ....................................................................................................................................81
3.2 Environmental Characteristics........................................................................................................................82
3.2.1 Environmental Specification........................................................................................................................82
3.2.2 Heat Sink/Spreader .....................................................................................................................................82
3.2.3 RoHS Compliance ........................................................................................................................................84
3.2.4 Electrostatic Discharge................................................................................................................................84
3.3 Mechanical Characteristics .............................................................................................................................85
3.3.1 Qseven SOM Mechanical Dimensions.........................................................................................................85
3.3.2 Guidelines to insert the Qseven SOM into Carrier board ............................................................................87
4. ORDERING INFORMATION .......................................................................................................................... 88
5. APPENDIX I................................................................................................................................................. 89
5.1 RZ/G1H Qseven SOM Configuration Switches................................................................................................89
6. APPENDIX II................................................................................................................................................ 90
6.1 RZ/G1H SPI Programmer Board ......................................................................................................................90
7. APPENDIX III............................................................................................................................................... 91
7.1 RZ/G1H Qseven SOM Development Platform ................................................................................................91

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List of Figures
Figure 1: RZ/G1H Qseven SOM Block Diagram...............................................................................................................11
Figure 2: RZ/G1H CPU Simplified Block Diagram ............................................................................................................15
Figure 3: Qseven PCB Edge Connector............................................................................................................................18
Figure 4: Expansion Connector1 .....................................................................................................................................42
Figure 5: Expansion Connector2 .....................................................................................................................................50
Figure 6: JTAG Header.....................................................................................................................................................60
Figure 7: SPI Programming Header.................................................................................................................................62
Figure 8: 2Pin Power Connector .....................................................................................................................................63
Figure 9: Qseven SOM Power Sequence.........................................................................................................................80
Figure 10: Heat Sink Dimensions ....................................................................................................................................83
Figure 11: Heat Spreader Dimensions ............................................................................................................................84
Figure 12: Mechanical dimension of Qseven SOM- Top View........................................................................................85
Figure 13: Mechanical dimension of RZ/G1H Qseven SOM- Bottom View ....................................................................86
Figure 14: Mechanical dimension of RZ/G1H Qseven SOM- Side View..........................................................................86
Figure 15: Qseven Module Insertion procedure.............................................................................................................87
Figure 16: Configuration Switches ..................................................................................................................................89
Figure 17: RZ/G1H SPI Programming Board....................................................................................................................90
Figure 18: RZ/G1H Qseven SOM Development Platform with Add on Module .............................................................91
List of Tables
Table 1: Acronyms & Abbreviations.................................................................................................................................. 7
Table 2: Terminology ........................................................................................................................................................9
Table 3: Compatible Magnetics ......................................................................................................................................19
Table 4: Qseven PCB Edge Connector Pin Assignment...................................................................................................27
Table 5: Parallel Camera Interface Pin Assignment on Expansion connector1 ..............................................................43
Table 6: Expansion Connector1 Pin Assignment.............................................................................................................44
Table 7: Compatible Magnetics ......................................................................................................................................51
Table 8: Expansion Connector2 Pin Assignment.............................................................................................................54
Table 9: JTAG Header Pin Assignment ............................................................................................................................61
Table 10: SPI Programming Header Pin Assignment ......................................................................................................62
Table 11: Power IN Connector - BOM.............................................................................................................................63
Table 12: RZ/G1H CPU IOMUX for Qseven Edge Connector interfaces..........................................................................64
Table 13: RZ/G1H CPU IOMUX for Expansion Connector1 interfaces ............................................................................69
Table 14: RZ/G1H CPU IOMUX for Expansion Connector2 interfaces ............................................................................72
Table 15: Power Input Requirement...............................................................................................................................79
Table 16: Power Sequence Timing..................................................................................................................................80
Table 17: Power Consumption........................................................................................................................................81
Table 18: Environmental Specification ...........................................................................................................................82
Table 19: Orderable Product Part Numbers ...................................................................................................................88
Table 20: SOM Configuration Switches...........................................................................................................................89

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1. INTRODUCTION
1.1 Purpose
This document is the Hardware User Guide for the RZ/G1H Qseven System On Module based on the Renesas’s RZ/G1H
Application processor. This board is fully supported by iWave Systems Technologies Pvt. Ltd. This Guide provides
detailed information on the overall design and usage of the RZ/G1H Qseven System On Module from a Hardware
Systems perspective.
1.2 Qseven SOM Overview
The RZ/G1H Qseven SOM is an extension of RZ/G1H CPU. The Qseven concept is an off-the-shelf, multi-vendor, Single-
Board-Computer that integrates all the core components of a common PC and is mounted onto an application specific
carrier board. Qseven modules have a standardized form factor of 70mm x 70mm and have specified pin outs based
on the high speed MXM system connector that has a standardized pin out regardless of the vendor. A single ruggedized
MXM connector provides the carrier board interface to carry all the I/O signals to and from the Qseven module.
1.3 List of Acronyms
The following acronyms will be used throughout this document.
Table 1: Acronyms & Abbreviations
Acronyms
Abbreviations
ARM
Advanced RISC Machine
BOM
Bill of Material
BPP
Bits Per Pixel
BSP
Board Support Package
CAN
Controller Area Network
CMOS
Complementary Metal-Oxide Semiconductor
CPU
Central Processing Unit
DDR3
Double Data Rate 3
DMA
Direct Memory Access
DVI
Digital Visual Interface
EDID
Extended Display Identification Data
eMMC
Enhanced Multi Media Card
GB
Giga Byte
Gbps
Gigabits per sec
GPIO
General Purpose Input Output
HDMI
High-Definition Multimedia Interface
HSCIF
High Speed Serial Communication Interface with FIFO
I2C
Inter-Integrated Circuit
IC
Integrated Circuit

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Acronyms
Abbreviations
JTAG
Joint Test Action Group
Kbps
Kilobits per second
LCD
Liquid Crystal Display
LVDS
Low-Voltage Differential Signal
MAC
Media Access Controller
MB
Mega Byte
Mbps
Megabits per sec
MHz
Mega Hertz
MSIOF
Clock-Synchronized Serial Interface with FIFO
NPTH
Non Plated Through hole
PCB
Printed Circuit Board
PCIe
Peripheral Component Interconnect Express
PTH
Plated Through hole
PWM
Pulse Width Modulation
QSPI
Quad Serial Peripheral Interface
RoHS
Restriction on Hazardous Substances
RTC
Real Time Clock
SATA
Serial Advanced Technology Attachment
SCIF
Serial Communication Interface with FIFO
SD
Secure Digital
SDHI
SD Card Host Interface
SSI
Serial Sound Interface
SDRAM
Synchronous Dynamic Random Access Memory
SOM
System On Module
TDM
Time Division Multiplexing
TPU
Time Pulse Unit
UART
Universal Asynchronous Receiver/Transmitter
USB
Universal Serial Bus
USB OTG
USB On The Go

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1.4 Terminlogy Description
In this document, wherever Signal Type is mentioned, below terminology is used.
Table 2: Terminology
Terminology
Description
I
Input Signal
O
Output Signal
IO
Bidirectional Input/output Signal
CMOS
Complementary Metal Oxide Semiconductor Signal
DIFF
Differential Signal
LVDS
Low Voltage Differential Signal
OD
Open Drain Signal
OC
Open Collector Signal
Power
Power Pin
PU
Pull Up
PD
Pull Down
NA
Not Applicable
NC
Not Connected
Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes
the pull-ups or pull-downs implemented On-SOM.
1.5 References
•RZ/G1H CPU Hardware User Manuals
•Qseven® Specification Version 2.0
•Qseven® Design Guide

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1.6 Important Note
RZ/G1H Qseven Edge connector signal name mentioned in Pinout Tables is followed as per below format for easy
understanding.
•If CPU pin has multiplexing option and selected particular function, then the signal name is mentioned as
“Selected Function Name (GPIO Number)”
Example: CAN0_RX(GP4_26)
In this signal, CAN0_RX is the functionality which we are using and GP4_26 is the GPIO number.
•If CPU pin has multiplexing option and selected as GPIO function, then the signal name is mentioned as
“GPIO_Functionality Description(GPIO Number)”
Example: GPIO_PCIe_RST/MD4(GP4_31)
In this signal, PCIe_RST is the GPIO functionality which we are using and GP4_31 is the GPIO number.
•If CPU pin doesn’t have multiplexing option, then the signal name is mentioned as,
“Function name”
Example: I2C3_SDA
In this signal, functionality which we are using I2C3_SDA
Note: The above naming is not applicable for other signals which are not connected to CPU.

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2. ARCHITECTURE AND DESIGN
This section provides detailed information about the RZ/G1H Qseven SOM features and Hardware architecture with
high level block diagram. Also this section provides detailed information about Qseven edge connector & Expansion
connector’s pin assignment and usage.
2.1 RZ/G1H QevenSOM Block Diagram
CPU
RZ/G1H
DDR3 -1GB
(Upgradable)
SPI Flash -
16MB
(Upgradable)
QSEVEN
PCB Edge
Connector
(230Pin)
Gigabit
Ethernet 4
SDHI2
I2C x 3
SPI x 1 (2 Chip selects)
CAN x 1
8 GPIOs, Status & Control Signals
PCIe/
SATA1
USB3.0/
SATA0
EtherAVB/
VI0
I2C0, I2C2
I2C3
MSIOF0
CAN1
GPIOs
QSPI
DDR3 (32bit)
Expansion
Connector1
(80Pin header)
Gigabit
Ethernet
PHY
DBSC3–CH0
I2S x 1
SSI3/
SSI4
SCIF2
SSI/I2S x 1
JTAG
iW-RainboW-G21M - RZ/G1H Qseven SOM Block Diagram
UART x 1
2Pin Power In
(Optional)
JTAG
Power to
Peripherals
5V
Debug
VI1
JTAG (Optional)
(20 Pin Header)
On-Board
Regulators
Dual SPDT
Switch IC
(Optional)
Expansion
Connector2
(80Pin header)
CAN0
CAN x 1
DDR3 -1GB
(Upgradable)
DDR3 (32bit) DBSC3–CH1
PWM x 2
TPU0TO0,
TPU0TO1
UART (with CTS & RTS) x 1
SCIFB1
¹ SATA0 & SATA1 is not supported by default.
² VI2 camera interface supports only Embedded Sync.
³ Through DIP switch, either MMC1-8bit (Since MMC_DATA7 line is shared with VI1_CLK) or VI1 can be selected at a time. If VI1 is used in 16bit, then VI2 cannot be used.
4 Through DIP switch, either EtherAVB (or) 4th Camera (VI0-8/16bit) can be selected at a time. If VI0 is used in 16bit, then VI3 cannot be used
USB1
MSIOF3
PWM x 3 PWM0,3,4
USB2.0 HUB
(2 Ports)
USB Host x 2
USB Host
USB Host x 1
USB2
EtherMAC
RMII x 1
SPI x 1 (2 Chip selects)
10/100Mbps
Ethernet PHY
SCIFA2
SCIF1,SCIF0
HSCIF0
SSI0
UART x 3
UART (with CTS & RTS) x 1
eMMC - 8GB
(Upgradable)
MMC1 (7bit) MMC1/
SDHI3
VI2/QSPI
Camera (8bit) x 1²
SDHI2
Bus
Switch VI0 (8/16bit)4
MMC1(1bit)3
Camera (8bit) x 1 VI3
Bus Switch
MMC1(1bit)3
VI1(8/16bit)x1 3
VI0 (8/16bit) x 14
SCIFB2
UART (with CTS & RTS) x 1
USB3.0 x 1²
PCIe x 1¹
SATA x 1¹
LVDS x 1, PWM x 1
DU_LVDS0,
TPU0TO2
DU_LVDS1 HDMI X 1
HDMI
Transmitter
(Optional)
RTC Controller VRTC
I2C0
SPI
Programming
Header
USB OTG x 1
USB0
Figure 1: RZ/G1H Qseven SOM Block Diagram

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2.2 RZ/G1H QsevenSOM Features
The RZ/G1H Qseven SOM supports the following features.
CPU
•Renesas’s RZ/G1H CPU: Quad ARM Cortex®-A15 MPCore® @ 1.4GHz and Quad ARM Cortex®-A7
MPCore® @ 780MHz
Memory
•DDR3 SDRAM - 2GB (Expandable)
•SPI Flash - 16MB (Expandable) 1
•eMMC Flash - 8GB (Expandable) 2
Other On-SOM Features
•Gigabit Ethernet PHY Transceiver
•10/100 Ethernet PHY Transceiver
•USB 2.0 High Speed 2-Port Hub
•RTC controller
•SPI Programming Header
•JTAG Header (Optional)
•HDMI Transmitter(Optional)
Qseven PCB Edge Interfaces
•Gigabit Ethernet x 1 Port (through On-SOM Gigabit Ethernet PHY transceiver) 3
•USB 3.0 Host x 1 Port 4
•PCIe x 1 Port5
•SATA x 1 Port (Optional) 4,5
•USB 2.0 OTG x 1 Port
•USB 2.0 Host x 1 Ports
•USB 2.0 Host x 2 Ports (through On-SOM USB 2.0 High Speed 2-Port Hub)
•SD (4bit) x 1 Port
•LVDS x 2 Ports 6
•HDMI x 1 Port 6
•SSI/I2S (Audio Interface) x 1 Port
•Debug UART
•Data UART (with CTS & RTS) x 1 Port

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•CAN x 1 Port
•SPI x 1 Port (with 2 Chip selects)
•I2C x 3 Ports
•PWM x 3 Ports
•8 GPIOs
Expansion Connector1 Interfaces
•Parallel Camera Interface x 4 Ports
➢VIN0 –8bit/16bit 3,7
➢VIN1 –8bit/16bit 2,8
➢VIN2 –8bit1,8
➢VIN3 –8bit7
Expansion Connector2 Interfaces
•10/100 Ethernet x 1 Port (through On-SOM Ethernet PHY transceiver)
•SSI/I2S x 1 Port
•Data UART x 3 Ports
•CAN x 1 Port
•SPI x 1 Port
•PWM x 3 Port
General Specification
•Power Supply : 5V,2A
•Power IN connector for Standalone usage (Optional)
•Form Factor :70mm x 70mm
1 In RZ/G1H CPU, SPI and VIN2 signals are multiplexed in same pins and so either one interface only can be used at a
time.
2 In RZ/G1H CPU, eMMC Data7 and VIN1 clock is multiplexed in same pin and so eMMC will operate only in 4bit mode
when VIN1 is supported. If VIN1 is not supported, then eMMC can operate in 8bit mode. A DIP switch (SW3) is provided
on SOM to select either eMMC 8bit mode or VIN1.
3 In RZ/G1H CPU, EtherAVB and VIN0 are multiplexed in same pins and so either one interface only can be used at a
time. A DIP switch (SW2) is provided on SOM to select either EtherAVB or VIN0.

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4 In RZ/G1H CPU, USB3.0 and SATA0 are multiplexed in same pins and so either one interface only can be used at a
time. By default, USB3.0 is supported.
5 In RZ/G1H CPU, PCIe and SATA1 are multiplexed in same pins and so either one interface only can be used at a time.
By default, PCIe is supported.
6In RZ/G1H SOM, RZ/G1H CPU’s DU_LVDS1 output can be connected to either HDMI transmitter or Secondary LVDS
port of Qseven Edge. By default, it is connected to Secondary LVDS port of Qseven Edge.
7In RZ/G1H CPU, VIN0 2nd 8bit and VIN3 are multiplexed in same pins and so VIN3 cannot be supported when VIN0 is
supported in 16bit mode. If VIN0 is supported in 8bit mode, then VIN3 also can be supported in 8bit mode.
8 In RZ/G1H CPU, VIN1 2nd 8bit and VIN2 are multiplexed in same pins and so VIN2 cannot be supported when VIN1 is
supported in 16bit mode. If VIN1 is supported in 8bit mode, then VIN2 also can be supported in 8bit mode.

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2.3 RZ/G1H CPU
The RZ/G1H Qseven SOM is based on Renesas’s RZ/G1H CPU with built-in Quad ARM™ Cortex-A15 Microprocessor
core and Quad ARM™ Cortex-A7 Microprocessor core both can operate up to 1.4 GHz/core and 780MHz/core
respectively. The Block Diagram of RZ/G1H CPU from the datasheet is shown below for reference.
Figure 2: RZ/G1H CPU Simplified Block Diagram
Note: Please refer the latest RZ/G1H Datasheet & Reference Manual for Electrical characteristics of RZ/G1H CPU which
may be revised from time to time.

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2.4 Memory
2.4.1 DDR3 SDRAM
The RZ/G1H Qseven SOM supports 2GB DDR3 RAM memory by default. This is connected to CPU in 32bit x 2ch mode
where it uses four 512MB DDR3-SDRAM ICs. This device operates at 1.5V voltage level. DDR3-SDRAM ICs are physically
located on either side of the SOM. The RAM size can be expandable up to maximum of 4GB.
2.4.2 SPI NOR Flash
The RZ/G1H Qseven SOM supports 16MB SPI NOR Flash as default boot device. This is connected to QSPI controller of
the RZ/G1H CPU and operates at 3.3 Voltage level. While RZ/G1H booting, boot program in the on-chip ROM starts up
the QSPI and SYS-DMAC channel 1 and transfers the loader program previously stored in the SPI Flash to the on-chip
RAM via the QSPI controller. After loader program is transferred, the program automatically jumps to the top address
of the loader program. The SPI flash memory (U21) is physically located on top side of the Qseven SOM.
In RZ/G1H CPU, QSPI and VIN2 are multiplexed in same pins and so either one interface only can be used at a time. A
bus switch is provided in these pins to select between QSPI and VIN2. This bus switch can be controlled by software
though GPIO pin “GP0_18”. If “GP0_18” pin is set to low, then QSPI is selected. If “GP0_18” pin is set to high, then
VIN2 is selected.
To program the boot code in to the SPI flash (for the first time or if boot code is corrupted), use iWave’s RZ/G1H SPI
Programmer Board through SPI Flash Programming Header (J4) (or) JTAG debugger through JTAG Header (J3).
Optionally the external SPI programmer can be used for programming the SPI flash through SPI Flash Programming
Header (J4).
Also RZ/G1H SOM supports single bit DIP switch (SW1) to select & deselect the QSPI chip select connection to SPI NOR
Flash. This switch is useful while programming the SPI NOR Flash using SPI Programming Board.
Note: For more details on single bit DIP switch (SW1) setting, refer APPENDIX I.
Note: For more details on SPI Programming Board, refer APPENDIX II.

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2.4.3 eMMC Flash
The RZ/G1H Qseven SOM supports 8GB eMMC Flash memory as mass storage. eMMC is directly connected to the
MMCIF controller of the RZ/G1H CPU which supports MMC 4.41 and operating at 3.3V Voltage level. The eMMC flash
memory is physically located on bottom side of the Qseven SOM. The memory size of the eMMC Flash can be
expandable.
In RZ/G1H CPU, MMCIF Data7 and VIN1 clock is multiplexed in same pin “GP3_15”and so eMMC will operate only in
4bit mode when VIN1 is supported. A bus switch is provided for “GP3_15” pin which is controlled by a DIP switch (SW3)
to select between eMMC 8bit and VIN1. If the DIP switch is set to “OFF” position, then eMMC will work in 8bit mode
and VIN1 cannot be supported. If the DIP switch is set to “ON” position, then VIN1 can be supported and eMMC will
work only in 4bit mode. This DIP switch position can be read by software though GPIO pin “GP4_12”.
Note: For more details on DIP switch (SW3), refer APPENDIX I.
2.5 RTC Controller
The RZ/G1H Qseven SOM supports external RTC Controller “PCF85263A”On-SOM for Real time clock support. This
external RTC Controller is connected to the RZ/G1H CPU through I2C0 Interface with slave address 0x51 and operates
at 3.3V voltage level. In SOM power off condition, this device will take power from Qseven Edge (VCC_RTC) coin cell
power input (Pin 193) and continues to keep the current time.

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RZ/G1H Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.6 Qseven PCB Edge Connector
The RZ/G1H Qseven SOM PCB edge connector has standard pin out as per Qseven Specification 2.0. The interfaces
which are available at 230pin Qseven Edge connector are explained in the following sections.
Figure 3: Qseven PCB Edge Connector
Number of Pins - 230
Connector Part - Not Applicable (On Board PCB Edge connector)
Mating Connector - IMSA-18010S-230A-GN1 from IRISO
88882-2D0K from Aces
AS0B326-S78N-7F from FOXCONN
CN113-230-0001VE from Yamaichi Electronics

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RZ/G1H Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.6.1 Gigabit Ethernet
The RZ/G1H Qseven SOM supports one 100/1000 Mbps Ethernet interface on Qseven Edge connector. The MAC is
integrated in the RZ/G1H CPU and connected to the external Gigabit Ethernet PHY on SOM. Since MAC and PHY are
supported on SOM itself, only Magnetics are required on the carrier board. RZ/G1H Qseven SOM also supports Link
and Activity indication LED control signals to Qseven Edge.
The RZ/G1H Qseven SOM supports “KSZ9031MNX” Ethernet PHY from Microchip. This PHY is interfaced with RZ/G1H
CPU’s EtherAVB controller and works at 3.3V IO voltage level. Since this PHY doesn’t recommend connecting any power
source to magnetic centre tap pins, CTREF voltage to Qseven Edge is not supported on SOM. It is recommended that
centre tap pins of magnetics should be separated from one another and connected through separate 0.1uF common
mode capacitors to ground. This PHY has on-chip termination on differential pairs and so no need to add any
termination externally. The below table provides some of the compatible magnetics recommended by the PHY
Manufacturer.
Table 3: Compatible Magnetics
Part Description
Part Number
Manufacturer
Temperature
Gigabit Ethernet Discrete Transformer
TG1G-E001NZRL
HALO
-40°C to 85°C
Gigabit Ethernet Discrete Transformer
HX5008NL
Pulse
-40°C to 85°C
Gigabit Ethernet Discrete Transformer
000-7093-37R-LF1
Wurth
0°C to 70°C
RJ45 Magjack with two Green LED
JK0654219NL
Pulse
0°C to 70°C
RJ45 Magjack with two Green LED
0826-1G1T-23-F
Bel Fuse
0°C to 70°C
For more details, refer Qseven Edge connector pins 3 to 15 on Table 4.
In RZ/G1H CPU, EtherAVB and VIN0 are multiplexed in same pins and so either one interface only can be used at a
time. A bus switch is provided in these pins which is controlled by a DIP switch (SW2) to select between EtherAVB and
VIN0. If the DIP switch is set to “OFF” position, then EtherAVB is supported. If the DIP switch is set to “ON” position,
then VIN0 is supported. This DIP switch position can be read by software though GPIO pin “GP5_21”.
Note: For more details on DIP switch (SW2), refer APPENDIX I.

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RZ/G1H Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.6.2 USB 3.0 Host Interface
The RZ/G1H Qseven SOM supports one High Speed USB 3.0 host interface on Qseven Edge connector. RZ/G1H CPU’s
USB3.0 Host Controller is used for USB3.0 interface which is compliant with the Universal Serial Bus (USB) 3.0
Specifications. It uses AXI Interconnection, which is a System Interface that is based on the AMBA® AXI Protocol v1.0
Specification. The USB3.0 Host Controller supports Super Speed (5 Gbps), High Speed (480 Mbps), Full Speed (12 Mbps)
and Low Speed (1.5 Mbps). Also the USB3.0 Host Controller is compliant with Battery Charging Specification Revision
1.2 and Supports polarity inversion of USB3.0 SS differential data pin pair.
For more details, refer Qseven Edge connector pins 75, 76, 77 & 78 on Table 4.
Note: In RZ/G1H CPU, USB3.0 & SATA0 High speed transceivers are multiplexed in same pins and so either one interface
only can be used at a time. By default, USB3.0 is supported. Please contact iWave if SATA support is required.
2.6.3 PCIe Interface
The RZ/G1H Qseven SOM supports one PCI Express Gen2.0 lane on Qseven Edge connector. RZ/G1H CPU’s PCIEC
module with integrated PHY is used for PCIe Interface which can support PCIe Gen2.0 at multiple speeds (2.5GT/s and
5GT/s). RZ/G1H CPU’s PCIe PHY output is connected to Qseven Edge connector PCIe channel 0. 100MHz external clock
oscillator output is connected to CPU & Qseven Edge for PCIe reference clock. Also PCIe wake and PCIe reset are
supported on Qseven Edge connector from RZ/G1H CPU IOs GP2_14 & GP4_31 correspondingly.
For more details, refer Qseven Edge connector pins 155, 156, 157, 158, 179, 180, 181 & 182 on Table 4.
Note: PCIe differential transmitter lines are ac coupled on SOM itself. Also PCIe differential clock lines from external
clock oscillator are having on-chip termination resistors and so no external termination is required.
Note: In RZ/G1H CPU, PCIe & SATA1 High speed transceivers are multiplexed in same pins and so either one interface
only can be used at a time. By default, PCIe is supported. Please contact iWave if SATA1 support is required.