iWave iW-RainboW-G30D Installation manual

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Page 1 of 89
iWave Systems Technologies Pvt. Ltd.
Zynq-Ultrascale+ MPSoC SOM Development Platform Hardware User Guide
iW-RainboW-G30D
Zynq Ultrascale+ MPSoC SOM
Development Platform
Hardware User Guide

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iWave Systems Technologies Pvt. Ltd.
Zynq-Ultrascale+ MPSoC SOM Development Platform Hardware User Guide
Document Revision History
Document Number
iW-PRFUD-UM-01-R2.0-REL1.1-Hardware-ZynqMPSoC-DevKit
Revision
Date
Change Description
1.0
27th Sep 2019
Official Release Version
1.1
9th May 2022
Updated Release Version
PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the intended recipient(s). Do
not read this document if you are not the intended recipient. Any review, use, distribution or disclosure by others is
strictly prohibited. If you are not the intended recipient (or authorized to receive for the recipient), you are hereby
notified that any disclosure, copying distribution or use of any of the information contained within this document is
STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.”

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iWave Systems Technologies Pvt. Ltd.
Zynq-Ultrascale+ MPSoC SOM Development Platform Hardware User Guide
Disclaimer
iWave Systems reserves the right to change details in this publication including but not limited to any Product
specification without notice.
No warranty of accuracy is given concerning the contents of the information contained in this publication. To the
extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by iWave
Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or
inaccuracies in this document.
CPU and other major components used in this product may have several silicon errata associated with it. Under no
circumstances, iWave Systems shall be liable for the silicon errata and associated issues.
Trademarks
All registered trademarks, product names mentioned in this publication are the property of their respective owners
and used for identification purposes only.
Certification
iWave Systems Technologies Pvt. Ltd. is an ISO 9001:2015 Certified Company.
Warranty & RMA
Warranty support for Hardware: 1 Year from iWave or iWave's EMS partner.
For warranty terms, go through the below web link,
http://www.iwavesystems.com/support/warranty.html
For Return Merchandise Authorization (RMA), go through the below web link,
http://www.iwavesystems.com/support/rma.html
Technical Support
iWave Systems technical support team is committed to provide the best possible support for our customers so that
our Hardware and Software can be easily migrated and used.
For assistance, contact our Technical Support team at,
Email : [e-mail]
Website : www.iwavesystems.com
Address : iWave Systems Technologies Pvt. Ltd.
# 7/B, 29th Main, BTM Layout 2nd Stage,
Bangalore, Karnataka,
India –560076

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iWave Systems Technologies Pvt. Ltd.
Zynq-Ultrascale+ MPSoC SOM Development Platform Hardware User Guide
Table of Contents
1. INTRODUCTION ..................................................................................................................................................8
1.1 Purpose.......................................................................................................................................................8
1.2 Overview.....................................................................................................................................................8
1.3 List of Acronyms ..........................................................................................................................................8
1.4 Terminology Description............................................................................................................................10
1.5 References.................................................................................................................................................10
2. ARCHITECTURE AND DESIGN ............................................................................................................................11
2.1 Zynq Ultrascale+ MPSoC SOM Carrier Board Block Diagram.......................................................................11
2.2 Zynq Ultrascale+ MPSoC SOM Carrier Board Features................................................................................12
2.3 Board to Board Connectors........................................................................................................................14
2.3.1 Board to Board Connector1....................................................................................................................14
2.3.2 Board to Board Connector2....................................................................................................................15
2.4 PS Interface Features.................................................................................................................................16
2.4.1 PS-GTR Transceivers...............................................................................................................................16
2.4.1.1 PCIe x4 Connector..........................................................................................................................18
2.4.1.2 Display Port Connector...................................................................................................................21
2.4.1.3 USB Type-C Connector ...................................................................................................................23
2.4.1.4 M.2 SATA Connector ......................................................................................................................26
2.4.2 Gigabit Ethernet Port1 ...........................................................................................................................29
2.4.3 Gigabit Ethernet Port2 ...........................................................................................................................30
2.4.4 USB2.0 OTG Port....................................................................................................................................31
2.4.5 Standard SD Port....................................................................................................................................32
2.4.6 CAN0 Header .........................................................................................................................................33
2.4.7 Debug UART ..........................................................................................................................................34
2.5 PL Interface Features.................................................................................................................................35
2.5.1 GTH High Speed Transceivers.................................................................................................................35
2.5.1.1 SFP+ Connector..............................................................................................................................36
2.5.1.2 SDI Video IN ...................................................................................................................................38
2.5.1.3 SDI Video OUT................................................................................................................................39
2.5.2 FMC HPC Connector1 .............................................................................................................................40
2.5.3 FMC HPC Connector2 .............................................................................................................................55
2.5.4 Pmod Host Port Connectors ...................................................................................................................69
2.6 Additional Features ...................................................................................................................................71
2.6.1 Clock Synthesizer/Generator ..................................................................................................................71
2.6.2 IO Expander ...........................................................................................................................................73
2.6.3 JTAG Connector......................................................................................................................................74
2.6.4 GPIO Header..........................................................................................................................................76
2.6.5 I2C Tree .................................................................................................................................................78
2.6.6 Power ON/OFF Switch............................................................................................................................79
2.6.7 Reset Switch ..........................................................................................................................................80
2.6.8 RTC Coin Cell Holder...............................................................................................................................81

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iWave Systems Technologies Pvt. Ltd.
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3. TECHNICAL SPECIFICATION...............................................................................................................................82
3.1 Power Input Requirement..........................................................................................................................82
3.2 Power Output Specification .......................................................................................................................83
3.3 Environmental Characteristics ...................................................................................................................84
3.3.1 Environmental Specification...................................................................................................................84
3.3.2 RoHS Compliance...................................................................................................................................84
3.3.3 Electrostatic Discharge...........................................................................................................................84
3.4 Mechanical Characteristics ........................................................................................................................85
3.4.1 Carrier Board Mechanical Dimensions....................................................................................................85
3.4.2 Guidelines to insert and remove the Zynq Ultrascale+ SoC SOM with Carrier Board ................................86
3.4.3 Fan Sink Fixing procedure on SOM with Carrier Board ............................................................................87
4. ORDERING INFORMATION................................................................................................................................88

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iWave Systems Technologies Pvt. Ltd.
Zynq-Ultrascale+ MPSoC SOM Development Platform Hardware User Guide
List of Figures
Figure 1: Zynq Ultrascale+ MPSoC SOM Carrier Board Block Diagram........................................................................11
Figure 2: Board to Board Connector1 ........................................................................................................................14
Figure 3: Board to Board Connector2 ........................................................................................................................15
Figure 4: PS-GTR External Switch Connectivity...........................................................................................................16
Figure 5: PS-GTR Lane Selection Switch.....................................................................................................................17
Figure 6: PCIe x4 Connector ......................................................................................................................................18
Figure 7: Display Port Connector...............................................................................................................................21
Figure 8: USB Type-C Connector................................................................................................................................24
Figure 9: M.2 SATA Connector (Key B).......................................................................................................................26
Figure 10: Gigabit Ethernet Connector1 ....................................................................................................................29
Figure 11: Gigabit Ethernet Connector2 ....................................................................................................................30
Figure 12: USB OTG Connector..................................................................................................................................31
Figure 13: Standard SD Connector.............................................................................................................................32
Figure 14: CAN0 Header............................................................................................................................................33
Figure 15: Debug UART Connector ............................................................................................................................34
Figure 16: GTH Transceiver Connections ...................................................................................................................35
Figure 17: SFP+ Connector with Cage ........................................................................................................................36
Figure 18: SDI Video IN HD BNC Connector ...............................................................................................................38
Figure 19: SDI Video OUT HD BNC Connector ............................................................................................................39
Figure 20: FMC Connector1.......................................................................................................................................40
Figure 21: FMC HPC Connector1 Pin Out ...................................................................................................................41
Figure 22: FMC Connector2.......................................................................................................................................55
Figure 23: FMC HPC Connector2 Pin Out ...................................................................................................................56
Figure 24: Pmod Host Port Connectors......................................................................................................................69
Figure 25: Clock Tree.................................................................................................................................................72
Figure 26: JTAG Connector........................................................................................................................................74
Figure 27: GPIO Header.............................................................................................................................................76
Figure 28: I2C Tree....................................................................................................................................................78
Figure 29: Power On/Off Switch................................................................................................................................79
Figure 30: Reset Switch.............................................................................................................................................80
Figure 31: RTC Coin Cell Holder.................................................................................................................................81
Figure 32: Power Jack................................................................................................................................................82
Figure 33: Carrier Board Mechanical dimension –Top and Bottom Views .................................................................85
Figure 34: Carrier board Mechanical dimension –Side Views....................................................................................85
Figure 35: Zynq Ultrascale+ SoC SOM Insert and Removal Procedure........................................................................86
Figure 36: Zynq Ultrascale+ SOM with Fan Sink fixing procedure...............................................................................87

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iWave Systems Technologies Pvt. Ltd.
Zynq-Ultrascale+ MPSoC SOM Development Platform Hardware User Guide
List of Tables
Table 1: Acronyms & Abbreviations.............................................................................................................................8
Table 2: Terminology ................................................................................................................................................10
Table 3: PS-GTR Lane Selection Switch Setting ..........................................................................................................17
Table 4: PCIe x4 Connector Pin Assignment...............................................................................................................19
Table 5: Display Port Connector Pin Assignment........................................................................................................22
Table 6: USB Type-C Pin Assignment .........................................................................................................................25
Table 7: M.2 SATA Connector Pin Assignment...........................................................................................................27
Table 8: CAN0 Header Pin Assignment ......................................................................................................................33
Table 9: SFP+ Connector Pin Assignment...................................................................................................................37
Table 10: FMC HPC Connector1 Pin Assignment........................................................................................................42
Table 11: FMC HPC Connector2 Pin Assignment........................................................................................................57
Table 12: Pmod Connector1 Pin Assignment .............................................................................................................70
Table 13: Pmod Connector2 Pin Assignment .............................................................................................................70
Table 14: Clock Synthesizer Output Clocks ................................................................................................................71
Table 15: IO Expander pinout details.........................................................................................................................73
Table 16: JTAG Header Pin Assignment .....................................................................................................................75
Table 17: GPIO Header Pin Assignment .....................................................................................................................76
Table 18: Power Input Requirement..........................................................................................................................82
Table 19: Power Output Specification .......................................................................................................................83
Table 20: Environmental Specification.......................................................................................................................84
Table 21: Orderable Product Part Numbers...............................................................................................................88

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iWave Systems Technologies Pvt. Ltd.
Zynq-Ultrascale+ MPSoC SOM Development Platform Hardware User Guide
1. INTRODUCTION
1.1 Purpose
The Zynq Ultrascale+ MPSoC SOM Development platform incorporates Zynq Ultrascale+ MPSoC based SOM and High-
Performance Carrier board for complete validation of Zynq Ultrascale+ MPSoC functionality. This document is the
Hardware User Guide for the Zynq Ultrascale+ MPSoC Carrier Board and provides detailed information on the overall
design & usage of the Carrier Board from a Hardware Systems perspective. The details about the Zynq Ultrascale+
MPSoC SOM hardware is explained in another document “iW-RainboW-G30M-Zynq-Ultrascale+MPSoC-SOM-
HardwareUserGuide”.
1.2 Overview
iWave's Zynq Ultrascale+ MPSoC Development platform incorporates Zynq Ultrascale+ MPSoC SOM which is based on
Xilinx’s Zynq Ultrascale+ MPSoC and the High-Performance Carrier Board. The development board can be used for
quick prototyping of various applications targeted by the Zynq Ultrascale+ MPSoC. With the 130mmx140mm size,
carrier board is packed with all the necessary on-board connectors to validate the features of Zynq Ultrascale+ MPSoC
SOM.
1.3 List of Acronyms
The following acronyms will be used throughout this document.
Table 1: Acronyms & Abbreviations
Acronyms
Abbreviations
ARM
Advanced RISC Machine
B2B
Board to Board
CAN
Controller Area Network
CH
Channel
CMOS
Complementary Metal Oxide Semiconductor Signal
DP
Display Port
FPGA
Field Programmable Gate Array
FMC
FPGA Mezzanine Card
Gbps
Gigabits per sec
GEM
Gigabit Ethernet Controller
GPIO
General Purpose Input Output
HPC
High Pin Count
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
JTAG
Joint Test Action Group
LVCMOS
Low Voltage Complementary Metal Oxide Semiconductor Signal
LVDS
Low Voltage Differential Signal

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Acronyms
Abbreviations
Mbps
Megabits per sec
MHz
Mega Hertz
NC
No Connect
NPTH
Non Plated Through Hole
PCB
Printed Circuit Board
PCIe
Peripheral Component Interconnect Express
PD
Pull Down
PMOD
Peripheral Module
PTH
Plated Through Hole
PU
Pull Up
RGMII
Reduced Gigabit Media Independent Interface
RX
Receiver
SATA
Serial Advanced Technology Attachment
SDI
Serial Digital Interface
SDIO
Secure Digital Input Output
SDHI
SD Card Host Interface
SFP
Small Form-factor Pluggable
SOM
System On Module
TXVR
Transceiver
TX
Transmitter
UART
Universal Asynchronous Receiver/Transmitter
USB
Universal Serial Bus
USB OTG
USB On The Go

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1.4 Terminology Description
In this document, wherever Signal Type is mentioned, below terminology is used.
Table 2: Terminology
Terminology
Description
I
Input Signal
O
Output Signal
IO
Bidirectional Input/output Signal
CMOS
Complementary Metal Oxide Semiconductor Signal
DIFF
Differential Signal
OD
Open Drain Signal
OC
Open Collector Signal
Analog
Analog Signal
Power
Power Pin
PU
Pull Up
PD
Pull Down
NA
Not Applicable
NC
Not Connected
Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes
the pull-ups or pull-downs implemented on board.
1.5 References
•Zynq Ultrascale+ MPSoC Datasheet & Reference Manual
•Zynq Ultrascale+ MPSoC SOM Hardware User Guide

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2. ARCHITECTURE AND DESIGN
This section provides detailed information about the Zynq Ultrascale+ MPSoC Development platform carrier board
features with high level block diagram and detailed information about each block.
2.1 Zynq Ultrascale+ MPSoC SOM Carrier Board Block Diagram
Figure 1: Zynq Ultrascale+ MPSoC SOM Carrier Board Block Diagram
High Performance
SoC FPGA SOM
SOM High Speed Board to Board Conenctor1
SOM High Speed Board to Board Conenctor2
High Performance SoC FPGA SOM - Carrier Board Block Diagram
Power Jack
(12V)
Debug UART UART to USB
converter
Power
Regulators
USB MicroAB
Connector1
Debug Port
Power to
Peripherals
20Pin PS IO
Header
UART, SPI, CAN, I2C & GPIOs
Power
Regulator
5V
12V
FPGA IOs, FPGA CLKIN/CLKOUT
GTH High Speed Transceivers x 4channels
USB MicroAB
Connector2
USB2.0 OTG
SD
Connector
SD (4bit)
CAN
Header
CAN
Transceiver
CAN x 1
CAN
14Pin JTAG
Header
JTAG
RJ45
Magjack1
Gigabit Ethernet
RJ45
Magjack2
Ethernet
PHY
Gigabit Ethernet
RGMII
GTH High Speed Transceivers x 8channels
FPGA IOs (up to 20LVDS)
FPGA CLKIN (4pairs)
FPGA CLKOUT (2pairs)
FMC
Connector2
FPGA IOs (up to 15LVDS)
FPGA CLKIN (2pairs)
FPGA CLKOUT (1pair)
To Transceiver Banks
SFP+
Connector
Clock
Generator
SDI Video In
BNC Jack
SDI Video Out
BNC Jack
USB TypeC
Connector
M.2 SATA
Connector
DP
Connector
2:1
Mux/DeMux
2:1
Mux/DeMux
2:1
Mux/DeMux
2:1
Mux/DeMux
PCIe x4
Connector
FPGA IOs, FPGA CLKIN/CLKOUT
RGMIIx1
GTR High Speed
TXVR x 1
GTR High Speed
TXVR x 1
Pmod
Connector1
Pmod
Connector2
3G/12G Cable
Driver ¹
3G/12G Cable
Equalizer ¹
GTH High Speed
TXVR x 1
FPGA IOs x 8 (I2C/SPI/UART/GPIOs)
FPGA IOs x 8 (I2C/SPI/UART/GPIOs)
SATA
USB3.0
DP
DP
PCIe x 4
SDI¹
SDO¹
RTC Coin cell
Holder
3V
FPGA IOs (up to 20SE)
FPGA IOs (up to 4SE)
GTR High Speed Transceivers x 2channels
GTH High Speed Transceivers x 4channels
GTR High Speed
TXVR x 1
FMC
Connector1
GTH High Speed Transceivers x 2channels
GTH High Speed TXVR x 1
CANx2
GTR High Speed
TXVR x 1
Note:
¹ By default, 3G SDI IN/OUT is supported. Optionally, 12G SDI IN/OUT can be supported on request.

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2.2 Zynq Ultrascale+ MPSoC SOM Carrier Board Features
The Zynq Ultrascale+ MPSoC Carrier board supports the following features to validate the Zynq Ultrascale+ MPSoC
SOM supported interfaces.
PS Interface Features
•PS GTR Features:
•PCIex1 Connector x 1
•Display Port Connector x 1
•USB 3.0 OTG through Type-C Connector x 1
•M.2 SATA Connector x 1
•Gigabit Ethernet through RJ45MagJack (GEM0) x 1
•Gigabit Ethernet through RJ45MagJack (GEM3) x 1
•USB2.0 OTG through MicroAB Connector x 1
•Standard SD Connector x 1
•CAN Header x 1
•Debug UART through USB MicroAB Connector x 1
PL Interface Features
•SFP+ Connector x 1
•SDI Video IN through HD BNC Connector x 1
•SDI Video OUT through HD BNC Connector x 1
•FMC High Pin Count (HPC) Connector1
➢8 GTH High Speed Transceivers
➢2 GTH Reference Clock
➢Upto 20 LVDS IOs/40 Single ended (SE) IOs
➢Upto 20 Single ended (SE) IOs
➢4 Clock Input Capable LVDS/SE pins
➢2 Clock Output Capable LVDS/SE pins
•FMC High Pin Count (HPC) Connector2
➢6 GTH High Speed Transceivers
➢2 GTH Reference Clock Capable
➢Upto 15 LVDS IOs/30 Single ended (SE) IOs
➢Upto 4 Single ended (SE) IOs
➢2 Clock Input Capable LVDS/SE pins
➢1 Clock Output Capable LVDS/SE pins
•PMOD Connector x 2

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Additional Features
•Clock Synthesizer/Generator
•16-Bit IO Expander
•JTAG Connector x 1
•20 Pin GPIO Header x 1
•Power ON/OFF DIP Switch x 1
•Reset Pushbutton Switch x 1
•RTC Coin Cell Holder x 1
General Specification
•Power Supply : DC 12V, 5A Power Input Jack
•Form Factor : 130mmX140mm

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2.3 Board to Board Connectors
The Zynq Ultrascale+ MPSoC Carrier board supports two 240 Pin Board to Board mating connectors for Zynq
Ultrascale+ MPSoC SOM attachment. This 240 pin Board to Board connector is capable of handling high-speed
serialized signals and can be used for size constrained embedded applications.
2.3.1 Board to Board Connector1
Board to Board Connector1 (J10) is physically located at the top of the board as shown below.
Note: For the Board to Board Connector1 pinout, refer the Zynq Ultrascale+ MPSoC SOM Hardware User Guide.
Figure 2: Board to Board Connector1

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2.3.2 Board to Board Connector2
Board to Board Connector2 (J11) is physically located at the top of the board as shown below.
Note: For the Board to Board Connector2 pinout, refer the Zynq Ultrascale+ MPSoC SOM Hardware User Guide.
Figure 3: Board to Board Connector2

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2.4 PS Interface Features
The features which are supported from Zynq Ultrascale+ MPSoC’s PS is explained in the following section.
2.4.1 PS-GTR Transceivers
The Zynq Ultrascale+ MPSoC Carrier board supports different high speed interfaces through four PS-GTR lanes (two
from B2B-1 and two from B2B-2). Each PS-GTR lane is conencted to High speed MUX/DEMUX IC to support different
high speed interfaces as mentioned below.
ox1, x2, or x4 lane of PCIe at Gen1 (2.5Gb/s) or Gen2 (5.0Gb/s) rates
o1 or 2 lanes of DisplayPort (TX only) at 1.62Gb/s, 2.7Gb/s, or 5.4Gb/s
o1 SATA port at 1.5Gb/s, 3.0Gb/s, or 6.0Gb/s
o1 USB3.0 port at 5.0Gb/s
The MUX/DEMUX connection and interface selection option is shown below for easy understanding. The selection
control of each MUX IC is connected to PS-GTR Lane selection 4bit DIP switch (SW5).
Figure 4: PS-GTR External Switch Connectivity.

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The PS-GTR Lane selection switch (SW5) setting and corresponding interface selection option is explained below.
Table 3: PS-GTR Lane Selection Switch Setting
PS-GTR Lanes
PS-GTR Lane Selection Switch (SW5)
Switch Bit
Number
Switch Bit Position
ON
OFF
Lane0
Bit1
PS-GTR Lane0 is connected to Lane0
of PCIe x4 connector (default)
PS-GTR Lane0 is connected to Lane1
of DP connector
Lane1
Bit2
PS-GTR Lane1 is connected to Lane1
of PCIe x4 connector
PS-GTR Lane1 is connected to Lane0
of DP connector (default)
Lane2
Bit3
PS-GTR Lane2 is connected to Lane2
of PCIe x4 connector
PS-GTR Lane2 is connected to Lane1
of USB3.0 TypeC connector (default)
Lane3
Bit4
PS-GTR Lane3 is connected to Lane3
of PCIe x4 connector
PS-GTR Lane3 is connected to M.2
SATA connector (default)
Figure 5: PS-GTR Lane Selection Switch

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2.4.1.1 PCIe x4 Connector
The Zynq Ultrascale+ MPSoC Carrier board supports one PCIe x4 connector through PS-GTR Lanes of Zynq Ultrascale+
MPSoC PS. All the four PS-GTR lanes from Board to Board Connectors are connected to PCIe x4 connector to support
x1, x2 & x4 PCIe devices. The PS-GTR Lane selection to PCIe x4 connector is done through PS-GTR Lane Selection Switch
(SW5). The Carrier board provides 100MHz reference clock to PCIe x4 connector from on board Clock Synthesizer. This
PCIe x4 connector (J19) is physically located at the top of the board as shown below.
Note: For more details on PS-GTR Lane selection options, refer Table 3.
Figure 6: PCIe x4 Connector

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Table 4: PCIe x4 Connector Pin Assignment
Pin No
Pin Name
Signal Name
Signal Type/
Termination
Description
A1
PRSNT1#
NA
NA
Default Grounded.
A2
+12V
VCC_12V
O, 12V Power
12V Supply Voltage.
A3
+12V
VCC_12V
O, 12V Power
12V Supply Voltage.
A4
GND
GND
Power
Ground.
A5
TCK
NA
NA
NC.
A6
TDI
NA
NA
NC.
A7
TDO
NA
NA
NC.
A8
TMS
NA
NA
NC.
A9
+3V3
VCC_3V3
O, 3.3V Power
3.3V Supply Voltage.
A10
+3V3
VCC_3V3
O, 3.3V Power
3.3V Supply Voltage.
A11
PERST#
PL_H14_LVDS46_L4P
O, 3.3V CMOS
PCIe Reset through PL Bank IO.
A12
GND
GND
Power
Ground.
A13
REFCLK+
PCIe_REFCLKP
O, DIFF
100MHz PCIe Reference Clock positive.
A14
REFCLK-
PCIe_REFCLKn
O, DIFF
100MHz PCIe Reference Clock negative.
A15
GND
GND
Power
Ground.
A16
PERp0
PS_MGTRRXP0_505
I, DIFF
PCIe Lane0 Receive pair positive.
A17
PERn0
PS_MGTRRXN0_505
I, DIFF
PCIe Lane0 Receive pair negative.
A18
GND
GND
Power
Ground.
A19
RSVD
NA
NA
NC.
A20
GND
GND
Power
Ground.
A21
PERp1
PS_MGTRRXP1_505
NA
PCIe Lane1 Receive pair positive.
A22
PERn1
PS_MGTRRXN1_505
NA
PCIe Lane1 Receive pair negative
A23
GND
GND
Power
Ground.
A24
GND
GND
Power
Ground.
A25
PERp2
PS_MGTRRXP2_505
NA
PCIe Lane2 Receive pair positive.
A26
PERn2
PS_MGTRRXN2_505
NA
PCIe Lane2 Receive pair negative.
A27
GND
GND
Power
Ground.
A28
GND
GND
Power
Ground.
A29
PERp3
PS_MGTRRXP3_505
NA
PCIe Lane3 Receive pair positive.
A30
PERn3
PS_MGTRRXN3_505
NA
PCIe Lane3 Receive pair negative.
A31
GND
GND
Power
Ground.
A32
RSVD
NA
NA
NC.
B1
+12V
VCC_12V
O, 12V Power
12V Supply Voltage.
B2
+12V
VCC_12V
O, 12V Power
12V Supply Voltage.
B3
RSVD
NA
NA
NC.
B4
GND
GND
Power
Ground.
B5
SMCLK
I2C0_SCL(PS_MIO10_500)
O, 3.3V CMOS
SMB Clock.
B6
SMDAT
I2C0_SDA(PS_MIO11_500)
IO, 3.3V CMOS
SMB DATA.
B7
GND
GND
Power
Ground.
B8
+3V3
VCC_3V3
O, 3.3V Power
3.3V Supply Voltage.
B9
TRST#
NA
NA
NC.

REL1.1
Page 20 of 89
iWave Systems Technologies Pvt. Ltd.
Zynq-Ultrascale+ MPSoC SOM Development Platform Hardware User Guide
Pin No
Pin Name
Signal Name
Signal Type/
Termination
Description
B10
3V3AUX
VCC_3V3_AUX
O, 3.3V Power
3.3V Supply Voltage
B11
WAKE#
PL_G14_LVDS46_L4N
O, 3.3V CMOS
PCIe Wake through PL Bank IO.
B12
RSVD
NA
NA
NC.
B13
GND
GND
Power
Ground.
B14
PETp0
PS_MGTRTXP0_505
O, DIFF
PCIe Lane0 Transmit pair positive.
B15
PETn0
PS_MGTRTXN0_505
O, DIFF
PCIe Lane0 Transmit pair negative.
B16
GND
GND
Power
Ground.
B17
PRSNT2
NA
NA
NC.
B18
GND
GND
Power
Ground.
B19
PETp1
PS_MGTRTXP1_505
NA
PCIe Lane1 Transmit pair positive.
B20
PETn1
PS_MGTRTXN1_505
NA
PCIe Lane1 Transmit pair negative
B21
GND
GND
Power
Ground.
B22
GND
GND
Power
Ground.
B23
PETp2
PS_MGTRTXP2_505
NA
PCIe Lane2 Transmit pair positive.
B24
PETn2
PS_MGTRTXN2_505
NA
PCIe Lane2 Transmit pair negative
B25
GND
GND
Power
Ground.
B26
GND
GND
Power
Ground.
B27
PETp3
PS_MGTRTXP3_505
NA
PCIe Lane3 Transmit pair positive.
B28
PETn3
PS_MGTRTXN3_505
NA
PCIe Lane3 Transmit pair negative
B29
GND
GND
Power
Ground.
B30
RSVD
NA
NA
NC.
B31
PRSNT#2
NA
NA
NC.
B32
GND
GND
Power
Ground.