iWave Zynq Ultrascale+ iW-RainboW-G30M Installation manual

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Zynq Ultrascale+ MPSoC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
iW-RainboW-G30M
Zynq Ultrascale+ MPSoC SOM
Hardware User Guide

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Zynq Ultrascale+ MPSoC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Document Revision History
Document Number
iW-PRFUZ-UM-01-R2.0-REL1.0-Hardware
Release
Date
Description
1.0
25th Jul 2019
Official Release Version
PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the intended recipient(s). Do
not read this document if you are not the intended recipient. Any review, use, distribution or disclosure by others
is strictly prohibited. If you are not the intended recipient (or authorized to receive for the recipient), you are
hereby notified that any disclosure, copying distribution or use of any of the information contained within this
document is STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.”

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Disclaimer
iWave Systems reserves the right to change details in this publication including but not limited to any Product
specification without notice.
No warranty of accuracy is given concerning the contents of the information contained in this publication. To the
extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by
iWave Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or
inaccuracies in this document.
CPU and other major components used in this product may have several silicon errata associated with it. Under no
circumstances, iWave Systems shall be liable for the silicon errata and associated issues.
Trademarks
All registered trademarks, product names mentioned in this publication are the property of their respective owners
and used for identification purposes only.
Certification
iWave Systems Technologies Pvt. Ltd. is an ISO 9001:2015 Certified Company.
Warranty & RMA
Warranty support for Hardware: 1 Year from iWave or iWave's EMS partner.
For warranty terms, go through the below web link,
http://www.iwavesystems.com/support/warranty.html
For Return Merchandise Authorization (RMA), go through the below web link,
http://www.iwavesystems.com/support/rma.html
Technical Support
iWave Systems technical support team is committed to provide the best possible support for our customers so that
our Hardware and Software can be easily migrated and used.
For assistance, contact our Technical Support team at,
Email : [e-mail]
Website : www.iwavesystems.com
Address : iWave Systems Technologies Pvt. Ltd.
# 7/B, 29th Main, BTM Layout 2nd Stage,
Bangalore, Karnataka,
India –560076

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Table of Contents
1. INTRODUCTION ..................................................................................................................................................7
1.1 Purpose.......................................................................................................................................................7
1.2 SOM Overview.............................................................................................................................................7
1.3 List of Acronyms ..........................................................................................................................................7
1.4 Terminlogy Description................................................................................................................................9
1.5 References...................................................................................................................................................9
2. ARCHITECTURE AND DESIGN ............................................................................................................................10
2.1 Zynq Ultrascale+ MPSoC SOM Block Diagram.............................................................................................10
2.2 Zynq Ultrascale+ MPSoC SOM Features .....................................................................................................11
2.3 Zynq Ultrascale+ MPSoC ............................................................................................................................14
2.3.1 MPSoC Power........................................................................................................................................16
2.3.2 MPSoC Reset .........................................................................................................................................17
2.3.3 MPSoC Reference Clock.........................................................................................................................17
2.3.4 MPSoC Configuration & Status...............................................................................................................18
2.3.5 MPSoC Boot Mode Switch .....................................................................................................................19
2.3.6 MPSoC System Monitor/ADC .................................................................................................................20
2.4 PMIC with RTC...........................................................................................................................................20
2.5 Memory.....................................................................................................................................................21
2.5.1 DDR4 SDRAM with ECC for PS ................................................................................................................21
2.5.2 DDR4 SDRAM for PL...............................................................................................................................21
2.5.3 eMMC Flash...........................................................................................................................................21
2.6 On SOM Fearures ......................................................................................................................................22
2.6.1 JTAG Header..........................................................................................................................................22
2.6.2 Fan Header ............................................................................................................................................24
2.7 Board to Board Connector1 .......................................................................................................................25
2.7.1 PS Interfaces..........................................................................................................................................30
2.7.1.1 PS-GTR Transceivers.......................................................................................................................30
2.7.1.2 RGMII/ULPI Interface .....................................................................................................................31
2.7.1.3 CAN Interface.................................................................................................................................33
2.7.2 PL Interfaces..........................................................................................................................................34
2.7.2.1 GTH High Speed Transceivers .........................................................................................................34
2.7.2.2 PL IOs –HD BANK45.......................................................................................................................38
2.7.2.3 PL IOs –HD BANK46.......................................................................................................................41
2.7.3 Power Control Input ..............................................................................................................................44
2.8 Board to Board Connector2 .......................................................................................................................45
2.8.1 PS Interfaces..........................................................................................................................................49
2.8.1.1 PS-GTR High Speed Transceivers.....................................................................................................49
2.8.1.2 Gigabit Ethernet Interface ..............................................................................................................50
2.8.1.3 USB2.0 OTG Interface.....................................................................................................................51
2.8.1.4 SD/SDIO Interface ..........................................................................................................................51
2.8.1.5 SPI Interface...................................................................................................................................52

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2.8.1.6 Debug UART Interface....................................................................................................................53
2.8.1.7 Data UART Interface.......................................................................................................................53
2.8.1.8 I2C Interface...................................................................................................................................54
2.8.1.9 JTAG Interface................................................................................................................................54
2.8.2 PL Interfaces..........................................................................................................................................55
2.8.2.1 GTH High Speed Transceivers .........................................................................................................55
2.8.2.2 PL IOs –HP BANK64 .......................................................................................................................57
2.8.2.3 PL IOs –HP BANK66 ........................................................................................................................62
2.8.3 Power & Reset Input..............................................................................................................................67
2.9 Zynq Ultrascale+ MPSoC PS Pin Multiplexing on Board to Board Connectors..............................................68
3. TECHNICAL SPECIFICATION...............................................................................................................................70
3.1 Electrical Characteristics............................................................................................................................70
3.1.1 Power Input Requirement......................................................................................................................70
3.1.2 Power Input Sequencing ........................................................................................................................71
3.1.3 Power Consumption ..............................................................................................................................72
3.2 Environmental Characteristics ...................................................................................................................73
3.2.1 Temperature Specification.....................................................................................................................73
3.2.2 RoHS2 Compliance.................................................................................................................................73
3.2.3 Electrostatic Discharge...........................................................................................................................73
3.2.4 Heat Sink ...............................................................................................................................................74
3.3 MechanicalCharacteristics .........................................................................................................................75
3.3.1 Zynq Ultrascale+ MPSoC SOM Mechanical Dimensions ..........................................................................75
4. ORDERING INFORMATION................................................................................................................................77
5. APPENDIX .........................................................................................................................................................79
5.1 Zynq Ultrascale+ MPSoC SOM Development Platform ...............................................................................79

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List of Figures
Figure 1: Zynq Ultrascale+ MPSoC SOM Block Diagram .............................................................................................10
Figure 2: Zynq Ultrascale+ MPSoC CPU Simplified Block Diagram ..............................................................................14
Figure 3: Zynq Ultrascale+ MPSoC Devices Comparison.............................................................................................15
Figure 4: Error Status Indication LEDs........................................................................................................................18
Figure 5: JTAG Header...............................................................................................................................................22
Figure 6: Fan Header.................................................................................................................................................24
Figure 7: Board to Board Connector1 ........................................................................................................................25
Figure 8: Board to Board Connector2 ........................................................................................................................45
Figure 9: Power Input Sequencing.............................................................................................................................71
Figure 10: Heat Sink Dimensions ...............................................................................................................................74
Figure 11: Mechanical dimension of Zynq Ultrascale+ MPSoC SOM - Top View..........................................................75
Figure 12: Mechanical dimension of Zynq Ultrascale+ MPSoC SOM - Bottom View....................................................76
Figure 13: Mechanical dimension of Zynq Ultrascale+ MPSoC SOM - Side View.........................................................76
Figure 14: Zynq Ultrascale+ MPSoC SOM Development Platform ..............................................................................79
List of Tables
Table 1: Acronyms & Abbreviations.............................................................................................................................7
Table 2: Terminology ..................................................................................................................................................9
Table 3: Zynq Ultrascale+ MPSoC SOM Reference Clock............................................................................................17
Table 4: Boot Mode Switch Truth Table.....................................................................................................................19
Table 5: JTAG Header Pinout.....................................................................................................................................23
Table 6: Fan Header Pinout .......................................................................................................................................24
Table 7: Board to Board Connector1 Pinout ..............................................................................................................26
Table 8: Board to Board Connector2 Pinout ..............................................................................................................46
Table 9: PS IOMUX on Zynq Ultrascale+ MPSoC SOM ................................................................................................68
Table 10: Power Input Requirement..........................................................................................................................70
Table 11: Power Sequence Timing.............................................................................................................................71
Table 12: Power Consumption¹ .................................................................................................................................72
Table 13: Temperature Specification.........................................................................................................................73
Table 14: Orderable Product Part Numbers...............................................................................................................77

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1. INTRODUCTION
1.1 Purpose
This document is the Hardware User Guide for the Zynq Ultrascale+ MPSoC System on Module based on the Xilinx
Zynq Ultrascale+ MPSoC. This board is fully supported by iWave Systems Technologies Pvt. Ltd. This Guide provides
detailed information on the overall design and usage of the Zynq Ultrascale+ MPSoC System on Module from a
Hardware Systems perspective.
1.2 SOM Overview
The Zynq Ultrascale+ MPSoC SOM is an extension of Zynq Ultrascale+ MPSoC. Zynq Ultrascale+ MPSoC SOM has a
form factor of 95mm x 75mm and provides the functional requirements for an embedded application. Two high
speed ruggedized terminal strip connectors provide the carrier board interface to carry all the I/O signals to and from
the Ultrascale+ MPSoC SOM.
1.3 List of Acronyms
The following acronyms will be used throughout this document.
Table 1: Acronyms & Abbreviations
Acronyms
Abbreviations
ADC
Analog to Digital Converter
ARM
Advanced RISC Machine
BSP
Board Support Package
CAN
Controller Area Network
CPU
Central Processing Unit
DDR4 SDRAM
Double Data Rate fourth-generation Synchronous Dynamic Random Access Memory
FPGA
Field Programmable Gate Array
eMMC
Embedded Multimedia Card
GB
Giga Byte
Gbps
Gigabits per sec
GEM
Gigabit Ethernet Controller
GHz
Giga Hertz
GPIO
General Purpose Input Output
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
JTAG
Joint Test Action Group
Kbps
Kilobits per second
LVDS
Low Voltage Differential Signalling
MAC
Media Access Controller
MB
Mega Byte
Mbps
Megabits per sec

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Acronyms
Abbreviations
MHz
Mega Hertz
NPTH
Non Plated Through hole
PCB
Printed Circuit Board
PMIC
Power Management Integrated IC
PTH
Plated Through hole
PL
Programmable Logic
PS
Processing System
RGMII
Reduced Gigabit Media Independent Interface
RTC
Real Time Clock
SD
Secure Digital
SDIO
Secure Digital Input Output
SGMII
Serial Gigabit Media Independent Interface
SoC
System On Chip
SOM
System On Module
SPI
Serial Peripheral Interface
UART
Universal Asynchronous Receiver/Transmitter
ULPI
UTMI+ Low Pin Interface
USB
Universal Serial Bus
USB OTG
USB On The Go
UTMI
USB2.0 Transceiver Macrocell Interface

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1.4 Terminlogy Description
In this document, wherever Signal Type is mentioned, below terminology is used.
Table 2: Terminology
Terminology
Description
I
Input Signal
O
Output Signal
IO
Bidirectional Input/output Signal
CMOS
Complementary Metal Oxide Semiconductor Signal
LVDS
Low Voltage Differential Signal
GBE
Gigabit Ethernet Media Dependent Interface differential pair signals
USB
Universal Serial Bus differential pair signals
OD
Open Drain Signal
OC
Open Collector Signal
Power
Power Pin
PU
Pull Up
PD
Pull Down
NA
Not Applicable
NC
Not Connected
Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes
the pull-ups or pull-downs implemented On-SOM.
1.5 References
•Zynq Ultrascale+ MPSoC Technical Reference Manual
•Zynq Ultrascale+ MPSoC Device Overview

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2. ARCHITECTURE AND DESIGN
This section provides detailed information about the Zynq Ultrascale+ MPSoC SOM features and Hardware
architecture with high level block diagram. Also, this section provides detailed information about two Board to Board
connector pin assignment and usage.
2.1 Zynq Ultrascale+ MPSoC SOM Block Diagram
Board to
Board
High Speed
Conenctor1
(240Pin)
Board to
Board
High Speed
Conenctor2
(240Pin)
iW-RainboW-G30M–Zynq Ultrascale+ MPSoC SOM Block Diagram
Processing System (PS)
Quad/Dual ARM Cortex-A53,
Dual Cortex-R5,Mali-400MP2,VCU
Zynq Ultrascale+
ZU4/ZU5/ZU7 - CG/EG/EV 3
GEM0
USB2.0
PHY
USB OTG
Ethernet
PHY
Gigabit Ethernet
ULPI
RGMII
DDR
Memory
Controller
SD0
DDR4 (64bit)
DDR4 –4GB
(Upgradable)
DDR4 (ECC)
eMMC –8GB
(Upgradable)
DDR4 ECC (8bit)
eMMC (8bit)
High Speed Transceiver (4 Channels) 2
Programmable Logic (PL)
Bank 225
Bank 224
Bank 227
Bank 226
High Speed Transceiver (4 Channels) 2
FPGA IOs (24LVDS/48SE/16ADC) 4
Bank 45
Bank 46
Bank 64
FPGA IOs (22SE/8ADC) 4
FPGA IOs (24SE/12ADC) 4
High Speed Transceiver (4 Channels) 2
High Speed Transceiver (4 Channels) 2
GTH Transceiver FPGA IOs
GTH Transceiver
FPGA IOs
JTAG
Header
FAN Header
5V
Power IN
(Optional)
Power
Regulators
Power to
Peripherals
5V
DDR4 (16bit)
USB0
Bank 505
PS GTR (4 TXVR)
High Speed Transceiver x 2 1
PS JTAG JTAG
SD (4bit) x 1
SD1
SPI0 SPI x 1
CAN0, CAN1
CAN x 2 Debug UART
UART x 1
UART0
UART1
I2C0,I2C1 I2C x 2
ULPI x 1 or RGMII x 1 GEM3/USB1
1 PS GTR Transceiver supports data rates up to 6Gb/s and can be configured as PCIe/SATA/USB3.0/DisplayPort/Ethernet SGMII.
2 PL GTH Transceiver supports data rates up to 16.3Gb/s
3 CG devices supports Dual ARM Cortex-A53 & Dual ARM Cortex-R5. EG devices supports Quad ARM Cortex-A53, Dual ARM Cortex-R5 & Mali-400MP2 GPU. EV devices supports Quad ARM
Cortex-A53, Dual ARM Cortex-R5 , Mali-400MP2 GPU & H.264/H.265 VCU.
4 SYSMONE4 supports 10bit 200KSPS ADC and supports upto 17 Analog Inputs (One dedicated Analog input and 16 auxiliary analog input from any PL BANKs)
Bank 65
FPGA IOs (24LVDS/48SE/16ADC) 4
Bank 66
DDR4 –1GB
SYSMONE4 ADC Inputs 4
High Speed PS GTR
Transceiver x 2 1
Figure 1: Zynq Ultrascale+ MPSoC SOM Block Diagram

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2.2 Zynq Ultrascale+ MPSoC SOM Features
The Zynq Ultrascale+ MPSoC SOM supports the following features.
SoC
•Xilinx Zynq Ultrascale+ MPSoC
➢Compatible Zynq Ultrascale+ MPSoC Family (FBVB900) –ZU7EV, ZU5EV, ZU4EV
Programming Logic with up to 504K Logic cells and Processing System with integrated Quad-core
ARM Cortex-A53 MPCore Application processor (up to 1.5GHz), Dual-core ARM Cortex-R5 MPCore
Real Time Processor (up to 600MHz), Mali™-400 MP2 Graphics Processor and H.264/H.265 Video
Codec.
➢Compatible Zynq Ultrascale+ MPSoC Family (FBVB900) –ZU7EG, ZU5EG, ZU4EG
Programming Logic with up to 504K Logic cells and Processing System with integrated Quad-core
ARM Cortex-A53 MPCore Application processor (up to 1.5GHz), Dual-core ARM Cortex-R5 MPCore
Real Time Processor (up to 600MHz) and Mali™-400 MP2 Graphics Processor.
➢Compatible Zynq Ultrascale+ MPSoC Family (FBVB900) –ZU7CG, ZU5CG, ZU4CG
Programming Logic with up to 504K Logic cells and Processing System with integrated Quad-core
ARM Cortex-A53 MPCore Application processor (up to 1.3GHz) and Dual-core ARM Cortex-R5
MPCore Real Time Processor (up to 533MHz).
PMIC
•Dialog’s DA9062 PMIC with RTC
Memory
•4GB DDR4 SDRAM (64bit) with ECC for PS (Expandable)
•1GB DDR4 SDRAM (16bit) for PL (Expandable)
•8GB eMMC Flash (Expandable)
Other On-SOM Features
•Gigabit Ethernet PHY Transceiver
•USB2.0 Transceiver
•JTAG Header
•Fan Header

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Board to Board Connector1 Interfaces
From PS Block
•PS-GTR High Speed Transceivers (upto 6Gbps) x 2
•RGMII Interface or ULPI Interface x 1 Port
•CAN x 2 Ports
From PL Block
•PL-GTH High Speed Transceivers (upto 16.3Gbps) x 12
•PL IOs - HD Bank452
➢Upto 11 LVDS IOs/22 Single ended (SE) IOs
oUpto 3 HDGC Global Clock Input pins (LVDS/SE)
oUpto 8 ADC Input pins (Differential/Single Ended)
•PL IOs - HD Bank462
➢Upto 12 LVDS IOs/24 Single Ended (SE) IOs
oUpto 4 HDGC Global Clock Input pins (LVDS/SE)
oUpto 12 ADC Input pins (Differential/Single Ended)
Board to Board Connector2 Interfaces
From PS Block
•PS-GTR High Speed Transceivers (upto 6Gbps) x 2
•Gigabit Ethernet x 1 Port (through On-SOM Gigabit Ethernet PHY transceiver)
•USB2.0 OTG x 1 Port (through On-SOM USB2.0 transceiver)
•SD (4bit) x 1 Port
•SPI x 1 Port
•Debug UART x 1 Port
•Data UART x 1 Port
•I2C x 2 Ports
•PS JTAG

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From PL Block
•PL-GTH High Speed Transceivers (upto 16.3Gbps) x4
•PL IOs - HP Bank642
➢Upto 24 LVDS IOs/48 Single ended (SE) IOs
oUpto 4 GC Global Clock Input pins (LVDS/SE)
oUpto 16 ADC Input pins (Differential/Single Ended)
•PL IOs - HP Bank662
➢Upto 24 LVDS IOs/48 Single ended (SE) IOs
oUpto 4 GC Global Clock Input pins (LVDS/SE)
oUpto 16 ADC Input pins (Differential/Single Ended)
General Specification
•Power Supply : 5V (from Board to Board Connector2)
•Form Factor : 95mm x 75mm
1In Zynq Ultrascale+ MPSoC PS, GEM3 RGMII interface & USB1 ULPI interface signals are multiplexed in same pins
and so either GEM3 or USB1 only can be supported.
2 In Zynq Ultrascale+ MPSoC SOM, PL BANK45 & BANK46 supports variable IO voltage setting and configurable
through software.

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2.3 Zynq Ultrascale+ MPSoC
Xilinx’s SoC portfolio integrates the software programmability of a processor with the hardware programmability of
an FPGA, providing unrivalled levels of system performance, flexibility, and scalability. Unlike traditional SoC
processing solutions, the flexible programmable logic provides optimization and differentiation, allowing to add the
peripherals and accelerators for a broad base of applications.
The Zynq Ultrascale+ MPSoC SOM is based on Xilinx Zynq Ultrascale+ MPSoC with FBVB900 package. Zynq
Ultrascale+ MPSoC family integrates Processing system (PS) and Xilinx programmable logic (PL) in a single device.
MPSoC’s Processing system includes feature-rich Quad-core ARM Cortex-A53 MPCore up to 1.5 GHz of Application
processor, Dual-core ARM Cortex-R5 MPCore up to 600MHz, Mali™-400 MP2 of Graphics Processor and H.264/H.265
of Video Codec. The Block Diagram of Zynq Ultrascale+ MPSoC from Xilinx website is shown below for reference.
Figure 2: Zynq Ultrascale+ MPSoC CPU Simplified Block Diagram
Note: Please refer the latest Zynq Ultrascale+ MPSoC Datasheet & Technical Reference Manual for more details
which may be revised from time to time.

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The Zynq Ultrascale+ MPSoC SOM is compatible to ZU7EV, ZU5EV, ZU4EV, ZU7EG, ZU5EG, ZU4EG, ZU7CG, ZU5CG
and ZU4CG MPSoC devices and feature comparison between these devices are shown below.
Figure 3: Zynq Ultrascale+ MPSoC Devices Comparison
The Zynq Ultrascale+ MPSoC’s PS has 78 dedicated I/O pins referred as MIO (Multiplexed I/O) for the PS peripheral
interfaces. These 78 MIO pins are divided into three banks (PS BANK500, 501 & 502) and each bank includes 26
device pins. Since 78 MIO pins are not enough to support simultaneous use of all the peripherals supported by PS,
there is option in MPSoC to route most of the IO peripheral interfaces to PL Bank I/O pins referred as EMIO
(Extended MIO). Zynq Ultrascale+ MPSoC’s PS Peripheral Pin mapping options between MIO & EMIO is shown below.

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Peripheral
Interface
MIO
EMIO
Quad-SPI
NAND
Yes
No
USB2.0: 0,1
Yes: External PHY
No
SDIO 0,1
Yes
Yes
SPI: 0,1
I2C: 0,1
CAN: 0,1
GPIO
Yes
CAN: External PHY
GPIO: Up to 78 bits
Yes
CAN: External PHY
GPIO: Up to 96 bits
GigE: 0,1,2,3
RGMII v2.0:
External PHY
Supports GMII, RGMII v2.0 (HSTL), RGMII v1.3, MII, SGMII, and
1000BASE-X in Programmable Logic
UART: 0,1
Simple UART:
Only two pins (TX and RX)
Full UART (TX, RX, DTR, DCD, DSR, RI, RTS, and CTS) requires either:
• Two Processing System (PS) pins (RX and TX) through MIO and six
additional Programmable Logic (PL) pins, or
• Eight Programmable Logic (PL) pins
Debug Trace
Ports
Yes: Up to 16 trace bits
Yes: Up to 32 trace bits
Processor JTAG
Yes
Yes
The Zynq Ultrascale+ MPSoC’s PL Banks are classified as high-performance (HP) banks or high-density (HD) banks.
The HP Bank I/Os are optimized for highest performance operation organized in banks of 52pins. The HD Bank I/Os
are reduced-feature I/Os organized in banks of 24pins.
In Zynq Ultrascale+ MPSoC PL, each bank supports four global clock (GC or HDGC) input pin pairs. GC pins have direct
access to the global clock buffers, MMCMs and PLLs of the same Bank. HDGC pins are from HD I/O banks and have
direct access only to the global clock buffers.
Also Zynq Ultrascale+ MPSoC supports two types of high speed transceivers namely GTH and PS-GTR. These
transceivers are arranged in groups of four known as a transceiver Quad. GTH transceivers are from PL and PS-GTR
transceivers are from PS.
2.3.1 MPSoC Power
The Zynq Ultrascale+ MPSoC SOM uses discrete power regulators along with DA9062 PMIC from Dialog
Semiconductor for MPSoC power management. In SOM, PS low-power domain, PS full-power domain & PL power
domain supply voltage (VCC_PSINTLP, VCC_PSINTFP, VCCINT) is fixed to 0.85V or 0.9V based on the speed grade of
the MPSoC. Also all PS Bank (VCCO_PSIO) I/O voltage is fixed to 1.8V.
The I/O voltage of PL HP Banks (PL Bank 64 & 66) which are connected to Board to Board Connectors is fixed to 1.8V.
The I/O voltage of PL HD Banks (PL Bank 45 & 46) which are connected to Board to Board Connectors are generated
from PMIC LDO3 and by default set to 1.8V. I/O voltage is configurable through software after bootup.

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2.3.2 MPSoC Reset
The Zynq Ultrascale+ MPSoC SOM uses PMIC’s Reset output (nRESET) for PS Power On Reset and connected to
PS_POR_B pin of MPSoC. Also it supports warm reset input from Board to Board Connector2 pin35 and connected to
PS_SRST_B pin of MPSoC.
2.3.3 MPSoC Reference Clock
The Zynq Ultrascale+ MPSoC SOM supports on board clock oscillators for reference clock to different blocks of Zynq
Ultrascale+ MPSoC. These reference clock details are mentioned in the below table.
Table 3: Zynq Ultrascale+ MPSoC SOM Reference Clock.
Sl.
No
On-SOM Oscillator
Frequency
SoC Ball Name/
Pin Number
Signal Type/
Termination
Description
1
33.33MHz
PS_REF_CLK/P19
1.8V, LVCMOS
33.33Mhz single ended reference
clock for PS.
2
100MHz¹
IO_L5P_HDGC_45/G16
1.8V², LVCMOS
100Mhz single ended reference
clock for PL. This is connected to
PL Bank45 HDGC Global clock pin.
3
300MHz
IO_L11P_T1U_N8_GC_65/AG8 &
IO_L11N_T1U_N9_GC_65/AH8
1.8V, LVDS
LVDS reference clock for PL DDR4.
This is connected to PL Bank65
Global clock pins.
¹ Important Note: I/O voltage of PL Bank45 is software configurable. Since this oscillator supports 1.8V to 3.3V VCC
only, this reference clock can be used only if the I/O voltage of PL Bank45 is set between 1.8V to 3.3V.
²Mentioned voltage level is based on default I/O voltage set to PL Bank45.

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Zynq Ultrascale+ MPSoC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.3.4 MPSoC Configuration & Status
The Zynq Ultrascale+ MPSoC uses multi-stage boot process that supports both a non-secure and a secure boot. The
PS is the master of the boot and configuration process. Upon reset, device executes code out of on-chip ROM and
copies the first stage boot loader (FSBL) from the boot device to the on-chip RAM. The FSBL initiates the boot of the
PS and can load and configure the PL or configuration of the PL can be deferred to a later stage.
The Zynq Ultrascale+ MPSoC SOM supports two LEDs (D6 & D5) for the MPSoC error status indication namely
PS_ERROR_OUT and PS_ERROR_STATUS. LED D6 is for PS_ERROR_OUT and it is asserted for accidental loss of power,
a hardware error, or an exception in the PMU. LED D5 is for PS_ERROR_STATUS and it indicates a secure lockdown
state. Alternatively, it can be used by the PMU firmware to indicate system status.
Figure 4: Error Status Indication LEDs

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Zynq Ultrascale+ MPSoC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.3.5 MPSoC Boot Mode Switch
The Zynq Ultrascale+ MPSoC always boots from PS first and configures the PL through software. MPSoC can support
eMMC, SD1, USB0 & JTAG as boot device and configurable through mode pins. Upon device reset, MPSoC mode pins
are read to determine the primary boot device.
The Zynq Ultrascale+ MPSoC SOM supports Boot Mode switch (SW1) to select the required boot device. By default,
eMMC is supported as boot device. Refer the below table to select the required boot device.
Table 4: Boot Mode Switch Truth Table
Zynq Ultrascale+
MPSoC Boot Mode
SW1 (4 Position Switch)
PS Mode 3
PS Mode 2
PS Mode 1
PS Mode 0
Switch Position Image
PS JTAG
OFF
OFF
OFF
OFF
SD1
OFF
ON
OFF
ON
eMMC
(Default)
OFF
ON
ON
OFF
USB0
OFF
ON
ON
ON

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Zynq Ultrascale+ MPSoC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.3.6 MPSoC System Monitor/ADC
The Zynq Ultrascale+ MPSoC contain two System Monitor block (SYSMONE4), one in the PL (PL SYSMON) and
another in the PS (PS SYSMON). It is used to enhance the overall safety, security and reliability of the system by
monitoring the physical environment via on-chip power supply and temperature sensors.
The PL SYSMON uses 10-bit 200kSPS ADC to digitize the sensor/ADC inputs. It monitors the die temperature in the PL
and several internal PL and PS power supply nodes. The PL SYSMON can also monitor up to 17 external analog
channels which includes 16 auxiliary analog inputs and one VP_VN dedicated input. The external auxiliary inputs can
be routed through any PL Bank. The ADC voltage reference is selectable between an internal reference and the
external pins VREFP and VREFN. In Zynq Ultrascale+ MPSoC SOM, 1.25V external voltage reference is supported.
The PS SYSMON uses 10-bit 1MSPS ADC to digitize the sensor inputs. It is located in the PS LPD and monitors two
temperature points & several internal fixed voltage nodes. The PS has two temperature sensors, one is physically
located in the PS SYSMON near the RPU. The second, remote sensor is located in the FPD near the APU. The ADC
always uses an internally generated voltage reference.
2.4 PMIC with RTC
The Zynq Ultrascale+ MPSoC SOM supports Dialog semiconductor DA9062 PMIC. The I2C0 module of Zynq
Ultrascale+ MPSoC PS is used for PMIC interface through MIO pins with I2C address 0x58.
PMIC’s LDO3 is connected to I/O voltage of PL HD Banks (PL Bank 45 & 46) and by default set to 1.8V. The I/O voltage
is configurable through software after bootup. PMIC supports reset output and connected to Zynq Ultrascale+
MPSoC PS (PS_POR_B) for power on reset. Also PMIC supports IRQ output for events indication and connected to
MPSoC’s PS GPIO (PS_MIO2_500).
The PMIC supports Real Time Clock functionality. It uses the Coin cell battery power from Board to Board
Connector2 pin68 for RTC backup power. The PMIC can support backup battery charging to charge Lithium-
Manganese coin cell batteries and super capacitors if required.