iWave Zynq-7000 SoC Installation manual

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iWave Systems Technologies Pvt. Ltd.
Zynq-7000 SoC SODIMM Development Platform Hardware User Guide
Zynq-7000 SoC
SODIMM Development Platform
Hardware User Guide

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iWave Systems Technologies Pvt. Ltd.
Zynq-7000 SoC SODIMM Development Platform Hardware User Guide
Document Revision History
Document Number
iW-PRFOZ-UM-02-R1.0-REL1.0-Hardware-Zynq-7000-DevKit
Revision
Date
Change Description
1.0
03rd Oct 2018
Initial Release Version
PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the intended recipient(s). Do
not read this document if you are not the intended recipient. Any review, use, distribution or disclosure by others is
strictly prohibited. If you are not the intended recipient (or authorized to receive for the recipient), you are hereby
notified that any disclosure, copying distribution or use of any of the information contained within this document is
STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.”

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iWave Systems Technologies Pvt. Ltd.
Zynq-7000 SoC SODIMM Development Platform Hardware User Guide
Disclaimer
iWave Systems reserves the right to change details in this publication including but not limited to any Product
specification without notice.
No warranty of accuracy is given concerning the contents of the information contained in this publication. To the
extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by
iWave Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or
inaccuracies in this document.
CPU and other major components used in this product may have several silicon errata associated with it. Under no
circumstances, iWave Systems shall be liable for the silicon errata and associated issues.
Trademarks
All registered trademarks, product names mentioned in this publication are the property of their respective owners
and used for identification purposes only.
Certification
iWave Systems Technologies Pvt. Ltd. is an ISO 9001:2015 Certified Company.
Warranty & RMA
Warranty support for Hardware: 1 Year from iWave or iWave's EMS partner.
For warranty terms, go through the below web link,
http://www.iwavesystems.com/support/warranty.html
For Return Merchandise Authorization (RMA), go through the below web link,
http://www.iwavesystems.com/support/rma.html
Technical Support
iWave Systems technical support team is committed to provide the best possible support for our customers so that
our Hardware and Software can be easily migrated and used.
For assistance, contact our Technical Support team at,
Email : [e-mail]
Website : www.iwavesystems.com
Address : iWave Systems Technologies Pvt. Ltd.
# 7/B, 29th Main, BTM Layout 2nd Stage,
Bangalore, Karnataka,
India –560076

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iWave Systems Technologies Pvt. Ltd.
Zynq-7000 SoC SODIMM Development Platform Hardware User Guide
Table of Contents
1. INTRODUCTION ............................................................................................................................................6
1.1 Purpose .............................................................................................................................................................6
1.2 Overview ...........................................................................................................................................................6
1.3 List of Acronyms................................................................................................................................................6
1.4 References ........................................................................................................................................................7
2. ARCHITECTURE AND DESIGN.........................................................................................................................8
2.1 Zynq SODIMM Carrier Board Block Diagram ....................................................................................................8
2.2 Zynq-7000 SoC SODIMM Carrier Board Features .............................................................................................9
2.3 SODIMM Connector........................................................................................................................................10
2.4 Serial Interface Features.................................................................................................................................25
2.4.1 Debug UART ................................................................................................................................................25
2.5 Communication Features................................................................................................................................26
2.5.1 Gigabit Ethernet Port ..................................................................................................................................26
2.5.2 USB 2.0 OTG Port ........................................................................................................................................27
2.5.3 MicroSD Port ...............................................................................................................................................28
2.6 Expasnion Connectors.....................................................................................................................................29
2.6.1 FMC Connector............................................................................................................................................29
2.6.2 Pmod Host Port Connectors ........................................................................................................................48
2.7 Additional Features.........................................................................................................................................50
2.7.1 JTAG Connector ...........................................................................................................................................50
2.7.2 Power ON/OFF Switch.................................................................................................................................51
2.7.3 Reset Switch ................................................................................................................................................51
2.7.4 RTC Coin Cell Holder....................................................................................................................................52
3. TECHNICAL SPECIFICATION.......................................................................................................................... 53
3.1 Electrical Characteristics .................................................................................................................................53
3.1.1 Power Input Requirement ...........................................................................................................................53
3.2 Environmental Characteristics........................................................................................................................54
3.2.1 Environmental Specification........................................................................................................................54
3.2.2 RoHS Compliance ........................................................................................................................................54
3.2.3 Electrostatic Discharge................................................................................................................................54
3.3 Mechanical Characteristics .............................................................................................................................55
3.3.1 SODIMM Carrier Board Mechanical Dimensions ........................................................................................55
3.3.2 Guidelines to insert the Zynq-7000 SoC SODIMM SOM into Carrier Board ................................................56
3.3.3 Guidelines to remove the Zynq-7000 SoC SODIMM SOM from Carrier board ............................................56
4. ORDERING INFORMATION .......................................................................................................................... 57

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iWave Systems Technologies Pvt. Ltd.
Zynq-7000 SoC SODIMM Development Platform Hardware User Guide
List of Figures
Figure 1: Zynq-7000 SoC SODIMM Carrier Board Block Diagram.....................................................................................8
Figure 2: SODIMM Edge Connector................................................................................................................................10
Figure 3: Debug UART .....................................................................................................................................................25
Figure 4: Gigabit Ethernet Connector.............................................................................................................................26
Figure 5: USB OTG Connector .........................................................................................................................................27
Figure 6: MicroSD Connector..........................................................................................................................................28
Figure 7: FMC HPC Connector.........................................................................................................................................29
Figure 8: FMC HPC Connector Pin Out............................................................................................................................30
Figure 9: Pmod Host Port Connectors.............................................................................................................................48
Figure 10: JTAG Connector..............................................................................................................................................50
Figure 11: Power On/Off Switch .....................................................................................................................................51
Figure 12: Reset Switch...................................................................................................................................................51
Figure 13: RTC Coin Cell Holder ......................................................................................................................................52
Figure 14: Power Jack......................................................................................................................................................53
Figure 15: SODIMM carrier board Mechanical dimension –Top View ..........................................................................55
Figure 16: SODIMM carrier board Mechanical dimension –Side View..........................................................................55
Figure 17: Zynq-7000 SoC SODIMM SOM Insertion procedure......................................................................................56
Figure 18: Zynq-7000 SoC SODIMM SOM removal procedure.......................................................................................56
List of Tables
Table 1: Acronyms & Abbreviations..................................................................................................................................6
Table 2: Terminology ........................................................................................................................................................7
Table 3: SODIMM Edge Connector Pin Out ....................................................................................................................11
Table 4: Micro SD Connector Pin Out .............................................................................................................................28
Table 5: FMC HPC Connector Pin Out.............................................................................................................................31
Table 6: Pmod Connector1 Pin Out.................................................................................................................................49
Table 7: Pmod Connector2 Pin Out.................................................................................................................................49
Table 8: JTAG Header Pin Out.........................................................................................................................................50
Table 9: Power Input Requirement.................................................................................................................................53
Table 10: Environmental Specification ...........................................................................................................................54
Table 11: Orderable Product Part Numbers ...................................................................................................................57

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iWave Systems Technologies Pvt. Ltd.
Zynq-7000 SoC SODIMM Development Platform Hardware User Guide
1. INTRODUCTION
1.1 Purpose
The Zynq-7000 SoC SODIMM Development platform incorporates Zynq-7000 SoC based SODIMM SOM and SODIMM
Carrier board for complete validation of Zynq-7000 SoC functionality. This document is the Hardware User Guide for
the Zynq-7000 SoC SODIMM Carrier Board and provides detailed information on the overall design & usage of the
Carrier Board from a Hardware Systems perspective. The details about the Zynq-7000 SoC SODIMM SOM hardware
is explained in Zynq-7000 SoC SODIMM SOM hardware user guide document.
1.2 Overview
iWave's Zynq-7000 SoC SODIMM Development platform incorporates Zynq 7000 SoC SODIMM SOM which is based
on Xilinx’s Zynq-7000 SoC and the SODIMM Carrier Board. With the 100mmx72mm size, carrier board is packed with
all the necessary on-board connectors to validate the features of Zynq-7000 SoC SODIMM SOM.
1.3 List of Acronyms
The following acronyms will be used throughout this document.
Table 1: Acronyms & Abbreviations
Acronyms
Abbreviations
ARM
Advanced RISC Machine
CH
Channel
CMOS
Complementary Metal Oxide Semiconductor Signal
CPU
Central Processing Unit
FMC
FPGA Mezzanine Card
GPIO
General Purpose Input Output
HPC
High Pin Count
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
Mbps
Megabits per sec
MHz
Mega Hertz
NC
No Connect
NPTH
Non Plated Through hole
PCB
Printed Circuit Board
PTH
Plated Through hole
SDIO
Secure Digital Input Output
SDHI
SD Card Host Interface
SOM
System On Module
UART
Universal Asynchronous Receiver/Transmitter
USB
Universal Serial Bus
USB OTG
USB On The Go

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Terminology Description
In this document, wherever Signal Type is mentioned, below terminology is used.
Table 2: Terminology
Terminology
Description
I
Input Signal
O
Output Signal
IO
Bidirectional Input/output Signal
CMOS
Complementary Metal Oxide Semiconductor Signal
DIFF
Differential Signal
TMDS
Transition-Minimized Differential Signalling
OD
Open Drain Signal
OC
Open Collector Signal
Analog
Analog Signal
Power
Power Pin
PU
Pull Up
PD
Pull Down
NA
Not Applicable
NC
Not Connected
Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes
the pull-ups or pull-downs implemented on board.
1.4 References
•Zynq-7000 SoC Datasheet & Reference Manual
•Zynq-7000 SoC SODIMM SOM Hardware User Guide

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2. ARCHITECTURE AND DESIGN
This section provides detailed information about the Zynq-7000 SoC SODIMM Development platform carrier board
features with high level block diagram and detailed information about each block.
2.1 Zynq SODIMM Carrier Board Block Diagram
Zynq-7000 SOM
SODIMM Connector
FPGA
IOs
SDHC
JTAG
USB OTG
USB Micro AB
Connector
Micro SD
Connector
SDHC x 4bit
USB OTG
Processor System (PS)
Programmable Logic (PL)
FMC
HPC Connector
(400pins)
Upto 98 SE IOs/39 LVDS IOs
iW-RainboW-G28D –Zynq-7000 SoC SODIMM Carrier Board Block Diagram
JTAG
Connector
3.3V
Power IN Power Jack
(5V)
3.3V Power
Regulator
To On-Board Power
Regulators & Peripherals
Power
3.3V
12V (Optional)
RTC
Push button
Switch
RTC Coin Cell
Holder
RST
I2C0
UART0
10/100/1000Mbps Ethernet0
RJ45
MagJack
UART to USB
Bridge
Debug
USB Micro AB
Connector
I2C0
I2C0
12pin Pmod
Connector2
12pin Pmod
Connector1
Figure 1: Zynq-7000 SoC SODIMM Carrier Board Block Diagram

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2.2 Zynq-7000 SoC SODIMM Carrier Board Features
The Zynq-7000 SoC SODIMM carrier board supports the following features to validate the Zynq-7000 SoC SOM
SODIMM Edge Connector features.
Serial Interface Features
•Debug UART through USB MicroAB Connector
Communication Features
•Gigabit Ethernet through RJ45MagJack x 1
•USB2.0 OTG through MicroAB Connector x 1
•SDIO through Micro SD Connector x 1
Expansion Connectors
•FMC High Pin Count (HPC) Connector x 1
➢Upto 98 Single ended (SE) IOs/39 LVDS IOs
•12pin PMOD Host Port Connector x 2
➢16 Single ended (SE) IOs (8 IOs on each connector)
Additional Features
•JTAG Connector x 1
•Power ON/OFF DIP Switch x 1
•Reset Pushbutton Switch x 1
•RTC Coin Cell Holder x 1
General Specification
•Power Supply : 5V Power Input Jack
•Form Factor : 100mm X 72mm
Note: In Zynq-7000 SoC, PL Bank13 is not available in Z-7007S and Z-7010 devices and so Bank13 IOs (20 SE IOs) on
FMC connector & Pmod connector1 is NC in Z-7007S and Z-7010 SoC based SODIMM DevKit.

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2.3 SODIMM Connector
The Zynq-7000 SoC SODIMM Carrier board supports 200 Pin SODIMM Edge mating connector for SODIMM SOM
attachment. This standard 200-pin robust connector is capable of handling high-speed serialized signals and can be
used for size constrained embedded applications. This SODIMM Edge mating connector (J7) is physically located at
the top of the board as shown below.
Figure 2: SODIMM Edge Connector

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Table 3: SODIMM Edge Connector Pin Out
Pin
No.
SODIMM Edge Connector
Pin Name
Signal Type/
Termination
Description
1
GND
Power
Ground.
2
GPHY_ATXRXM
IO, DIFF
Ethernet transmit differential pair 0 negative.
This pin is connected to RJ45 Magjack.
3
NC
NA
NC.
4
GPHY_ATXRXP
IO, DIFF
Ethernet transmit differential pair 0 positive.
This pin is connected to RJ45 Magjack.
5
GND
Power
Ground.
6
GPHY_BTXRXM
IO, DIFF
Ethernet receive differential pair 1 negative.
This pin is connected to RJ45 Magjack.
7
PL_IO_L19N_T3_VREF_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
Note: Optionally this pin is connected to E13th pin
of FMC connector (J1) through resistor and default
not populated.
8
GPHY_BTXRXP
IO, DIFF
Ethernet receive differential pair 1 positive.
This pin is connected to RJ45 Magjack.
9
PL_IO_L19P_T3_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
Note: Optionally this pin is connected to K16th pin
of FMC connector (J1) through resistor and default
not populated.
10
PL_IO_L6N_T0_VREF_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to 2nd pin of Pmod
connector1 (J3).
Note: Optionally this pin is connected to E19th pin
of FMC connector (J1) through resistor and default
not populated.
11
GPHY_LINK_LED2
I, 3.3V CMOS
Gigabit Ethernet link status LED.
12
GPHY_ACTIVITY_LED1
I, 3.3V CMOS
Gigabit Ethernet speed status LED.
13
GND
Power
Ground.
14
GPHY_CTXRXM
IO, DIFF
Gigabit Ethernet differential pair 3 negative.
15
GPHY_DTXRXM
IO, DIFF
Gigabit Ethernet differential pair 4 negative.
16
GPHY_CTXRXP
IO, DIFF
Gigabit Ethernet differential pair 3 positive.
17
GPHY_DTXRXP
IO, DIFF
Gigabit Ethernet differential pair 4 positive.
18
PL_IO_L11N_T1_SRCC_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to K14th pin of FMC
connector (J1).
19
PL_IO_L11P_T1_SRCC_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to K13th pin of FMC
connector (J1)
20
VIN_3V3
O, 3.3V Power
Supply Voltage.

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Pin
No.
SODIMM Edge Connector
Pin Name
Signal Type/
Termination
Description
21
PL_IO_L22P_T3_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to K10th pin of FMC
connector (J1).
22
PL_IO_L15P_T2_DQS_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to E6th pin of FMC connector
(J1).
23
PL_IO_L22N_T3_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to K11th pin of FMC
connector (J1).
24
PL_IO_L15N_T2_DQS_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to E7th pin of FMC connector
(J1).
25
NC
NA
NC.
26
PL_IO_L12P_T1_MRCC_13
IO, 3.3V CMOS
Bank13 Clock user Multi region positive Single
ended pin.
This pin is connected to E2nd pin of FMC
connector (J1).
27
GND
Power
Ground.
28
PL_IO_L12N_T1_MRCC_13
IO, 3.3V LVCMOS
Bank13 Clock user Multi region negative Single
ended pin.
This pin is connected to E3rd pin of FMC connector
(J1).
29
PL_IO_L20P_T3_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to K7th pin of FMC connector
(J1).
30
PL_IO_L18P_T2_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to J9th pin of FMC connector
(J1).
31
PL_IO_L20N_T3_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to K8th pin of FMC connector
(J1).
32
VIN_3V3
O, 3.3V Power
Supply Voltage.
33
PL_IO_L18N_T2_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to J10th pin of FMC
connector (J1).
34
PL_IO_L1N_T0_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to H8th pin of FMC
connector (J1).
35
PL_IO_L2N_T0_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to G10th pin of FMC
connector (J1).

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Pin
No.
SODIMM Edge Connector
Pin Name
Signal Type/
Termination
Description
36
PL_IO_L1P_T0_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to H7th pin of FMC
connector (J1).
37
PL_IO_L2P_T0_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to G9th pin of FMC
connector (J1).
38
PL_IO_L10N_T1_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to G13th pin of FMC
connector (J1).
39
PL_IO_L10P_T1_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to G12th pin of FMC
connector (J1).
40
GND
Power
Ground.
41
GND
Power
Ground.
42
PL_IO_L18N_T2_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to H17th pin of FMC
connector (J1).
43
PL_IO_L23N_T3_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to C19th pin of FMC
connector (J1).
44
PL_IO_L18P_T2_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to H16th pin of FMC
connector (J1).
45
PL_IO_L23P_T3_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to C18th pin of FMC
connector (J1).
46
VIN_3V3
O, 3.3V Power
Supply Voltage.
47
PL_IO_L13N_T2_MRCC_34
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to 2nd pin of Pmod
connector2 (J5).
Note: Optionally this pin is connected to J16th pin
of FMC connector (J1) through resistor and default
not populated.
48
PL_IO_L17N_T2_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to F8th pin of FMC connector
(J1).
49
NC
NA
NC.
50
PL_IO_L17P_T2_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to F7th pin of FMC connector
(J1).
51
GND
Power
Ground.

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Pin
No.
SODIMM Edge Connector
Pin Name
Signal Type/
Termination
Description
52
PL_IO_L13N_T2_MRCC_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to F5th pin of FMC connector
(J1).
53
PL_IO_L14N_T2_SRCC_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to E10th pin of FMC
connector (J1).
54
PL_IO_L13P_T2_MRCC_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to F4th pin of FMC connector
(J1).
55
PL_IO_L14P_T2_SRCC_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to E9th pin of FMC connector
(J1).
56
PL_IO_L21N_T3_DQS_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to J7th pin of FMC connector
(J1).
57
PL_IO_L16N_T2_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to F11th pin of FMC
connector (J1).
58
PL_IO_L21P_T3_DQS_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to J6th pin of FMC connector
(J1).
59
PL_IO_L16P_T2_13
IO, 3.3V LVCMOS
Bank13 User I/O Single ended pin.
This pin is connected to F10th pin of FMC
connector (J1).
60
VIN_3V3
O, 3.3V Power
Supply Voltage.
61
PL_IO_L8N_T1_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to H14th pin of FMC
connector (J1).
62
PL_IO_L4N_T0_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to H11th pin of FMC
connector (J1).
63
PL_IO_L8P_T1_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to H13th pin of FMC
connector (J1).
64
PL_IO_L4P_T0_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to H10th pin of FMC
connector (J1).
65
GND
Power
Ground.
66
PL_IO_L7N_T1_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to C11th pin of FMC
connector (J1).

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Pin
No.
SODIMM Edge Connector
Pin Name
Signal Type/
Termination
Description
67
PL_IO_L11N_T1_SRCC_34
O, 3.3V CMOS
Bank34 Clock user Single region negative Single
ended pin.
This pin is connected to G3rd pin of FMC
connector (J1).
68
PL_IO_L7P_T1_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to C10th pin of FMC
connector (J1).
69
PL_IO_L11P_T1_SRCC_34
O, 3.3V LVCMOS
Bank34 Clock user Single region positive Single
ended pin.
This pin is connected to G2nd pin of FMC
connector (J1).
70
PL_IO_L17P_T2_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to C14th pin of FMC
connector (J1).
71
PL_IO_L6N_T0_VREF_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to 10th pin of Pmod
connector2 (J5).
Note: Optionally this pin is connected to K17th pin
of FMC connector (J1) through resistor and default
not populated.
72
VIN_3V3
O, 3.3V Power
Supply Voltage.
73
PL_IO_L6P_T0_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to 9th pin of Pmod
connector2 (J5).
Note: Optionally this pin is connected to F13th pin
of FMC connector (J1) through resistor and default
not populated.
74
PL_IO_L17N_T2_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to C15th pin of FMC
connector (J1).
75
PL_IO_0_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to 9th pin of Pmod
connector1 (J3).
Note: Optionally this pin is connected to C30th pin
of FMC connector (J1) through resistor and default
not populated.
76
PL_IO_25_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to 7th pin of Pmod
connector2 (J5).
Note: Optionally this pin is connected to C31st pin
of FMC connector (J1) through resistor and default
not populated.

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Page 16 of 58
iWave Systems Technologies Pvt. Ltd.
Zynq-7000 SoC SODIMM Development Platform Hardware User Guide
Pin
No.
SODIMM Edge Connector
Pin Name
Signal Type/
Termination
Description
77
USB_OTG_ID
O, 3.3V CMOS
USB OTG ID input for USB host or device
detection.
This pin is connected from Micro USB OTG
connector (J4).
78
USB_PWR_EN
I, 3.3V CMOS
USB active high power enable output to control
external USB Vbus.
This pin is connected to USB OTG Power switch
enable pin to control USB OTG VBUS power.
79
GND
Power
Ground.
80
PL_IO_L3P_T0_DQS_PUDC
_B_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
Note: Optionally this pin is connected to J15th pin
of FMC connector (J1) through resistor and default
not populated.
81
USB_OTG_DP
IO, DIFF
USB OTG data positive.
This pin is connected to Micro USB OTG connector
(J4).
82
NC
NA
NC.
83
USB_OTG_DM
IO, DIFF
USB OTG data negative.
This pin is connected to Micro USB OTG connector
(J4).
84
NC
NA
NC.
85
NC
NA
NC.
86
PL_IO_L9P_T1_DQS_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to H19th pin of FMC
connector (J1).
87
NC
NA
NC.
88
VIN_3V3
O, 3.3V Power
Supply Voltage.
89
PL_IO_L9N_T1_DQS_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to H20th pin of FMC
connector (J1).
90
PL_IO_L12P_T1_MRCC_34
O, 3.3V LVCMOS
Bank34 Clock user Multi region positive Single
ended pin.
This pin is connected to H4th pin of FMC
connector (J1).
91
PL_IO_L19P_T3_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to 1st pin of Pmod
connector2 (J5).
Note: Optionally this pin is connected to F16th pin
of FMC connector (J1) through resistor and default
not populated.

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Page 17 of 58
iWave Systems Technologies Pvt. Ltd.
Zynq-7000 SoC SODIMM Development Platform Hardware User Guide
Pin
No.
SODIMM Edge Connector
Pin Name
Signal Type/
Termination
Description
92
PL_IO_L12N_T1_MRCC_34
O, 3.3V LVCMOS
Bank34 Clock user Multi region negative Single
ended pin.
This pin is connected to H5th pin of FMC
connector (J1).
93
PL_IO_L19N_T3_VREF_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to 4th pin of Pmod
connector1 (J3).
Note: Optionally this pin is connected to J19th pin
of FMC connector (J1) through resistor and default
not populated.
94
PL_IO_L22P_T3_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to D17th pin of FMC
connector (J1).
95
GND
Power
Ground.
96
PL_IO_L22N_T3_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to D18th pin of FMC
connector (J1).
97
PL_IO_L5P_T0_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to D11th pin of FMC
connector (J1).
98
PL_IO_L21P_T3_DQS_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to G21st pin of FMC
connector (J1).
99
PL_IO_L5N_T0_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to D12th pin of FMC
connector (J1).
100
PL_IO_L21N_T3_DQS_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to G22nd pin of FMC
connector (J1).
101
PL_IO_L20P_T3_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to G15th pin of FMC
connector (J1).
102
PL_IO_L16P_T2_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to D14th pin of FMC
connector (J1).
103
PL_IO_L20N_T3_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is optionally connected to G16th pin of
FMC connector (J1).
104
PL_IO_L16N_T2_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is optionally connected to D15th pin of
FMC connector (J1).

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Page 18 of 58
iWave Systems Technologies Pvt. Ltd.
Zynq-7000 SoC SODIMM Development Platform Hardware User Guide
Pin
No.
SODIMM Edge Connector
Pin Name
Signal Type/
Termination
Description
105
SD0_CD(PS_MIO48_501)
O, 1.8V LVCMOS/
SD0 Card Detect pin.
This pin is connected from Micro SD connector for
card detection.
106
VIN_3V3
O, 3.3V Power
Supply Voltage.
107
SD0_DATA0(PS_MIO42_50
1)
IO, 3.3V LVCMOS
SD0 Data0.
This pin is connected to Micro SD connector.
108
SD0_CMD(PS_MIO41_501)
IO, 3.3V LVCMOS
SD0 command.
This pin is connected to Micro SD connector.
109
SD0_CLK(PS_MIO40_501)
I, 3.3V LVCMOS
SD0 clock.
This pin is connected to Micro SD connector.
110
PL_IO_L24N_T3_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to 8th pin of Pmod
connector2 (J5).
Note: Optionally this pin is connected to E16th pin
of FMC connector (J1) through resistor and default
not populated.
111
SD0_DATA1(PS_MIO43_50
1)
IO, 3.3V LVCMOS
SD0 Data1.
This pin is connected to Micro SD connector
112
SD0_DATA2(PS_MIO44_50
1)
IO, 3.3V LVCMOS
SD0 Data2.
This pin is connected to Micro SD connector
113
GND
Power
Ground.
114
SD0_DATA3(PS_MIO45_50
1)
IO, 3.3V LVCMOS
SD0 Data3.
This pin is connected to Micro SD connector
115
I2C0_SDA(PS_MIO47_501)
IO, 3.3V OD
I2C0 data.
This pin is connected to C31st pin of FMC
connector (J1).
116
I2C0_SCL(PS_MIO46_501)
I, 3.3V OD
I2C0 clock.
This pin is connected to C30th pin of FMC
connector (J1).
117
UART0_RX(PS_MIO50_501
)
O, 3.3V LVCMOS/
10K PU
Debug UART0 Receive data line.
This pin is connected from Serial to USB
converter.
118
UART0_TX(PS_MIO51_501
)
I, 3.3V LVCMOS
Debug UART0 Transmit data line.
This pin is connected to Serial to USB converter.
119
PL_IO_L14N_T2_SRCC_34
IO, 3.3V LVCMOS
Bank34 Clock user Single region negative Single
ended pin.
This pin is connected to D21st pin of FMC
connector (J1).
120
PL_IO_L15N_T2_DQS_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to G19th pin of FMC
connector (J1).

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Page 19 of 58
iWave Systems Technologies Pvt. Ltd.
Zynq-7000 SoC SODIMM Development Platform Hardware User Guide
Pin
No.
SODIMM Edge Connector
Pin Name
Signal Type/
Termination
Description
121
PL_IO_L14P_T2_SRCC_34
IO, 3.3V LVCMOS
Bank34 Clock user Single region positive Single
ended pin.
This pin is connected to D20th pin of FMC
connector (J1).
122
PL_IO_L15P_T2_DQS_34
O, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to G18th pin of FMC
connector (J1).
123
PL_IO_L3N_T0_DQS_34
IO, 3.3V LVCMOS
Bank34 User I/O Single ended pin.
This pin is connected to 10th pin of Pmod
connector1 (J3).
Note: Optionally this pin is connected to F17th pin
of FMC connector (J1) through resistor and default
not populated.
124
VIN_3V3
O, 3.3V Power
Supply Voltage.
125
PL_IO_L23P_T3_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to G36th pin of FMC
connector (J1).
126
PL_IO_L21P_T3_DQS_AD1
4P_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to H25th pin of FMC
connector (J1).
127
NC
NA
NC.
128
NC
NA
NC.
129
NC
NA
NC.
130
NC
NA
NC.
131
GND
Power
Ground.
132
PL_IO_L22N_T3_AD7N_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to H33rd pin of FMC
connector (J1).
133
PL_IO_L23N_T3_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to G37th pin of FMC
connector (J1).
134
PL_IO_L20P_T3_AD6P_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to H34th pin of FMC
connector (J1).
135
NC
NA
NC.
136
PL_IO_L12P_T1_MRCC_35
O, 3.3V LVCMOS
Bank35 Clock user Single region positive Single
ended pin.
This pin is connected to J2nd pin of FMC connector
(J1).
137
NC
NA
NC.
138
PL_IO_L22P_T3_AD7P_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to H22nd pin of FMC
connector (J1).

REL1.0
Page 20 of 58
iWave Systems Technologies Pvt. Ltd.
Zynq-7000 SoC SODIMM Development Platform Hardware User Guide
Pin
No.
SODIMM Edge Connector
Pin Name
Signal Type/
Termination
Description
139
PL_IO_L24P_T3_AD15P_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to G33rd pin of FMC
connector (J1).
140
PL_IO_L21N_T3_DQS_AD1
4N_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to H26th pin of FMC
connector (J1).
141
NC
NA
NC.
142
VIN_3V3
O, 3.3V Power
Supply Voltage.
143
PL_IO_L8N_T1_AD10N_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to D27th pin of FMC
connector (J1).
144
PL_IO_L11N_T1_SRCC_35
O, 3.3V LVCMOS
Bank35 Clock user Single region negative Single
ended pin.
This pin is connected to K5th pin of FMC connector
(J1).
145
PL_IO_L8P_T1_AD10P_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to D26th pin of FMC
connector (J1).
146
PL_IO_L7P_T1_AD2P_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to J12th pin of FMC
connector (J1).
147
PL_IO_L7N_T1_AD2N_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to J13th pin of FMC
connector (J1).
148
PL_IO_L9P_T1_DQS_AD3P
_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to G24th pin of FMC
connector (J1).
149
PL_IO_L9N_T1_DQS_AD3N
_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to G25th pin of FMC
connector (J1).
150
PL_IO_L11P_T1_SRCC_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to K4th pin of FMC connector
(J1).
151
GND
Power
Ground.
152
PL_IO_L14P_T2_AD4P_SRC
C_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to D8th pin of FMC
connector (J1).
153
PL_IO_L10N_T1_AD11N_3
5
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to G7th pin of FMC
connector (J1).
154
PL_IO_L10P_T1_AD11P_35
IO, 3.3V LVCMOS
Bank35 User I/O Single ended pin.
This pin is connected to G6th pin of FMC
connector (J1).