iWave Zynq Ultrascale+ MPSoC Installation manual

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Zynq Ultrascale+ MPSoC SBC Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
iW-RainboW-G36S
Zynq Ultrascale+ MPSoC SBC
Hardware User Guide
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Zynq Ultrascale+ MPSoC SBC Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Document Revision History
Document Number
iW-PRGGG-UM-01-R2.0-REL0.1-Hardware
Release
Date
Description
0.1
18th May 2021
Initial Draft Version
PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the intended recipient(s). Do
not read this document if you are not the intended recipient. Any review, use, distribution or disclosure by others is
strictly prohibited. If you are not the intended recipient (or authorized to receive for the recipient), you are hereby
notified that any disclosure, copying distribution or use of any of the information contained within this document is
STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.”
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Disclaimer
iWave Systems reserves the right to change details in this publication including but not limited to any Product
specification without notice.
No warranty of accuracy is given concerning the contents of the information contained in this publication. To the
extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by iWave
Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or
inaccuracies in this document.
CPU and other major components used in this product may have several silicon errata associated with it. Under no
circumstances, iWave Systems shall be liable for the silicon errata and associated issues.
Trademarks
All registered trademarks, product names mentioned in this publication are the property of their respective owners
and used for identification purposes only.
Certification
iWave Systems Technologies Pvt. Ltd. is an ISO 9001:2015 Certified Company.
Warranty & RMA
Warranty support for Hardware: 1 Year from iWave or iWave's EMS partner.
For warranty terms, go through the below web link,
http://www.iwavesystems.com/support/warranty.html
For Return Merchandise Authorization (RMA), go through the below web link,
http://www.iwavesystems.com/support/rma.html
Technical Support
iWave Systems technical support team is committed to provide the best possible support for our customers so that
our Hardware and Software can be easily migrated and used.
For assistance, contact our Technical Support team at,
Email : [e-mail]
Website : www.iwavesystems.com
Address : iWave Systems Technologies Pvt. Ltd.
# 7/B, 29th Main, BTM Layout 2nd Stage,
Bangalore, Karnataka,
India –560076
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Table of Contents
1. INTRODUCTION ..................................................................................................................................................8
1.1 Purpose.......................................................................................................................................................8
1.2 SBC Overview ..............................................................................................................................................8
1.3 List of Acronyms ..........................................................................................................................................8
1.4 Terminlogy Description..............................................................................................................................10
1.5 References.................................................................................................................................................10
2. ARCHITECTURE AND DESIGN ............................................................................................................................11
2.1 Zynq Ultrascale+ MPSoC SBC Block Diagram ..............................................................................................11
2.2 Zynq Ultrascale+ MPSoC SBC Features.......................................................................................................12
2.3 Zynq Ultrascale+ MPSoC ............................................................................................................................16
2.3.1 MPSoC Power........................................................................................................................................18
2.3.2 MPSoC Reset .........................................................................................................................................19
2.3.3 MPSoC Reference Clock.........................................................................................................................19
2.3.4 MPSoC Configuration & Status...............................................................................................................20
2.3.5 MPSoC Boot Mode.................................................................................................................................20
2.3.6 MPSoC System Monitor/ADC .................................................................................................................21
2.4 PMIC with RTC...........................................................................................................................................21
2.5 Memory.....................................................................................................................................................22
2.5.1 DDR4 SDRAM for PS...............................................................................................................................22
2.5.2 DDR4 SDRAM for PL...............................................................................................................................22
2.5.3 eMMC Flash...........................................................................................................................................22
2.5.4 EEPROM ................................................................................................................................................22
2.5.5 Micro SD Connector (Optional) ..............................................................................................................23
2.6 Fearures from PS Block..............................................................................................................................24
2.6.1 Dual 10/100/1000Mbps Ethernet through RJ45 Magjack .......................................................................24
2.6.2 WLAN & BT Module with Antenna connector.........................................................................................25
2.6.3 Debug UART Header ..............................................................................................................................26
2.7 Features from PS-GTR................................................................................................................................27
2.7.1 Display Port Connector ..........................................................................................................................27
2.7.2 Dual USB3.0 Type A Jack ........................................................................................................................28
2.7.3 M.2 Key B Connector with SATA & USB3.0 .............................................................................................29
2.8 Features from PL-GTH................................................................................................................................33
2.8.1 HDMI Input Connector...........................................................................................................................33
2.8.2 HDMI Output Connector........................................................................................................................34
2.8.3 SFP+ Connector......................................................................................................................................35
2.8.4 3G/12G SDI IN (Optional).......................................................................................................................37
2.8.5 3G/12G SDI Output (Optional) ...............................................................................................................37
2.9 Additional Features ...................................................................................................................................38
2.9.1 Clock Synthesizers..................................................................................................................................38
2.9.2 JTAG Header..........................................................................................................................................38
2.9.3 Fan Header ............................................................................................................................................40
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2.9.4 RTC Header............................................................................................................................................41
2.9.5 Power On/OFF Switch............................................................................................................................42
2.9.6 Reset Switch ..........................................................................................................................................42
2.10 Board to Board Connector1 .......................................................................................................................43
2.10.1 PS Interfaces..........................................................................................................................................45
2.10.1.1 SPI Interface...............................................................................................................................45
2.10.1.2 CAN Interface.............................................................................................................................45
2.10.1.3 I2C Interface...............................................................................................................................46
2.10.2 PL Interfaces..........................................................................................................................................46
2.10.2.1 PL IOs –HP BANK64....................................................................................................................46
2.10.2.2 PL IOs –HD BANK45 ...................................................................................................................51
2.10.3 Power....................................................................................................................................................52
2.11 Board to Board Connector2 .......................................................................................................................53
2.11.1 PL Interfaces..........................................................................................................................................55
2.11.1.1 PL IOs –HP BANK64....................................................................................................................55
2.11.1.2 PL IOs –HD BANK45 ....................................................................................................................58
2.11.1.3 PL IOs –HD BANK46 ....................................................................................................................60
2.11.2 Power....................................................................................................................................................65
2.12 Board to Board Connector3 .......................................................................................................................66
2.12.1 PL Interfaces..........................................................................................................................................68
2.12.1.1 PL IOs –HD BANK43 ....................................................................................................................68
2.12.1.2 PL IOs –HD BANK44 ....................................................................................................................73
2.12.2 Power....................................................................................................................................................77
2.13 Zynq Ultrascale+ MPSoC PS Pin Multiplexing on Board to Board Connectors..............................................78
3. TECHNICAL SPECIFICATION...............................................................................................................................80
3.1 Power Input Requirement..........................................................................................................................80
3.2 Power Output Specification .......................................................................................................................81
3.2.1 Power Consumption ..............................................................................................................................81
3.3 Environmental Characteristics ...................................................................................................................82
3.3.1 Temperature Specification.....................................................................................................................82
3.3.2 RoHS2 Compliance.................................................................................................................................82
3.3.3 Electrostatic Discharge...........................................................................................................................82
3.3.4 Heat Sink ...............................................................................................................................................82
3.4 MechanicalCharacteristics .........................................................................................................................83
3.4.1 Zynq Ultrascale+ MPSoC SBC Mechanical Dimensions............................................................................83
4. ORDERING INFORMATION................................................................................................................................85
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List of Figures
Figure 1: Zynq Ultrascale+ MPSoC SBC Block Diagram ...............................................................................................11
Figure 2: Zynq Ultrascale+ MPSoC CPU Simplified Block Diagram ..............................................................................16
Figure 3: Zynq Ultrascale+ MPSoC Devices Comparison.............................................................................................17
Figure 4: Error Status Indication LEDs........................................................................................................................20
Figure 5: Dual Gigabit Ethernet Port..........................................................................................................................24
Figure 6: WLAN & BT with Antenna Connector..........................................................................................................25
Figure 7: Debug UART Header...................................................................................................................................26
Figure 8: Display Port Connector...............................................................................................................................27
Figure 9: Dual Stack USB3.0 Type-A Jack....................................................................................................................28
Figure 10: M.2 Key B Connector ................................................................................................................................29
Figure 11: HDMI IN Connector ..................................................................................................................................33
Figure 12: HDMI Out Connector ................................................................................................................................34
Figure 13: SFP+ Connector ........................................................................................................................................35
Figure 14: JTAG Header.............................................................................................................................................39
Figure 15: Fan Header...............................................................................................................................................40
Figure 16: RTC Header...............................................................................................................................................41
Figure 17: Power ON/OFF Switch ..............................................................................................................................42
Figure 18: Reset Switch.............................................................................................................................................42
Figure 19: Board to Board Connector1 ......................................................................................................................43
Figure 20: Board to Board Connector2 ......................................................................................................................53
Figure 21: Board to Board Connector3 ......................................................................................................................66
Figure 22: Input Power Jack ......................................................................................................................................80
Figure 23: Mechanical dimension of Zynq Ultrascale+ MPSoC SBC - Top View ...........................................................83
Figure 24: Mechanical dimension of Zynq Ultrascale+ MPSoC SBC - Bottom View .....................................................83
Figure 25: Mechanical dimension of Zynq Ultrascale+ MPSoC SBC - Side View...........................................................84
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List of Tables
Table 1: Acronyms & Abbreviations.............................................................................................................................8
Table 2: Terminology ................................................................................................................................................10
Table 3: Zynq Ultrascale+ MPSoC SBC Reference Clock..............................................................................................19
Table 4: Debug UART Header Pin Assignment ...........................................................................................................26
Table 5: M.2 Connector Pin Assignment....................................................................................................................30
Table 6: SFP+ Connector Pin Assignment...................................................................................................................36
Table 7: Clock Synthesier Output Clocks....................................................................................................................38
Table 8: JTAG Header Pinout.....................................................................................................................................39
Table 9: Fan Header Pinout .......................................................................................................................................40
Table 10: RTC Header Pinout.....................................................................................................................................41
Table 11: Board to Board Connector1 Pinout ............................................................................................................44
Table 12: Board to Board Connector2 Pinout ............................................................................................................54
Table 13: Board to Board Connector3 Pinout ............................................................................................................67
Table 14: PS IOMUX on Zynq Ultrascale+ MPSoC SBC................................................................................................78
Table 15: Power Input Requirement..........................................................................................................................80
Table 16: Power Output Specification .......................................................................................................................81
Table 17: Power Consumption¹ .................................................................................................................................81
Table 18: Temperature Specification.........................................................................................................................82
Table 19: Orderable Product Part Numbers...............................................................................................................85
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1. INTRODUCTION
1.1 Purpose
This document is the Hardware User Guide for the Zynq Ultrascale+ MPSoC Single Board Computer based on the Xilinx
Zynq Ultrascale+ MPSoC . This board is fully supported by iWave Systems Technologies Pvt. Ltd. This Guide provides
detailed information on the overall design and usage of the Zynq Ultrascale+ MPSoC SBC from a Hardware Systems
perspective.
1.2 SBC Overview
The Zynq Ultrascale+ MPSoC SBC is an extension of Zynq Ultrascale+ MPSoC. Zynq Ultrascale+ MPSoC SBC has a form
factor of 72mm x 100mm and provides the functional requirements for an embedded application. Three high speed
ruggedized terminal strip connectors provide the interface to carry all the I/O signals from Zynq Ultrascale+ MPSoC.
1.3 List of Acronyms
The following acronyms will be used throughout this document.
Table 1: Acronyms & Abbreviations
Acronyms
Abbreviations
ADC
Analog to Digital Converter
ARM
Advanced RISC Machine
BSP
Board Support Package
CAN
Controller Area Network
CPU
Central Processing Unit
DDR4 SDRAM
Double Data Rate fourth-generation Synchronous Dynamic Random Access Memory
FPGA
Field Programmable Gate Array
eMMC
Embedded Multimedia Card
GB
Giga Byte
Gbps
Gigabits per sec
GEM
Gigabit Ethernet Controller
GHz
Giga Hertz
GPIO
General Purpose Input Output
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
JTAG
Joint Test Action Group
Kbps
Kilobits per second
LVDS
Low Voltage Differential Signalling
MAC
Media Access Controller
MB
Mega Byte
Mbps
Megabits per sec
MHz
Mega Hertz
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Acronyms
Abbreviations
NPTH
Non Plated Through hole
PCB
Printed Circuit Board
PMIC
Power Management Integrated IC
PTH
Plated Through hole
PL
Programmable Logic
PS
Processing System
RGMII
Reduced Gigabit Media Independent Interface
RTC
Real Time Clock
SBC
Single Board Computer
SD
Secure Digital
SDIO
Secure Digital Input Output
SoC
System On Chip
SPI
Serial Peripheral Interface
UART
Universal Asynchronous Receiver/Transmitter
ULPI
UTMI+ Low Pin Interface
USB
Universal Serial Bus
USB OTG
USB On The Go
UTMI
USB2.0 Transceiver Macrocell Interface
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1.4 Terminlogy Description
In this document, wherever Signal Type is mentioned, below terminology is used.
Table 2: Terminology
Terminology
Description
I
Input Signal
O
Output Signal
IO
Bidirectional Input/output Signal
CMOS
Complementary Metal Oxide Semiconductor Signal
LVDS
Low Voltage Differential Signal
GBE
Gigabit Ethernet Media Dependent Interface differential pair signals
USB
Universal Serial Bus differential pair signals
OD
Open Drain Signal
OC
Open Collector Signal
Power
Power Pin
PU
Pull Up
PD
Pull Down
NA
Not Applicable
NC
Not Connected
Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes
the pull-ups or pull-downs implemented On-SBC.
1.5 References
•Zynq Ultrascale+ MPSoC Technical Reference Manual
•Zynq Ultrascale+ MPSoC Device Overview
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2. ARCHITECTURE AND DESIGN
This section provides detailed information about the Zynq Ultrascale+ MPSoC SBC features and Hardware architecture
with high level block diagram. Also, this section provides detailed information about Board to Board connectors pin
assignment and usage.
2.1 Zynq Ultrascale+ MPSoC SBC Block Diagram
EEPROM
(For MAC ADDR)
WLAN+BT
DDR4 –2GB
(Upgradable)
USB2.0
PHY
4 Port
USB Hub
iW-RainboW-G36S-Zynq Ultrascale+ MPSoC SBC SOM Block Diagram
1. DP Dual line supports upto 4K resolution.
2 CG devices supports Dual ARM Cortex-A53 & Dual ARM Cortex-R5. EG devices supports Quad ARM Cortex-A53, Dual ARM Cortex-R5 & Mali-400MP2 GPU. EV devices supports Quad ARM
Cortex-A53, Dual ARM Cortex-R5 , Mali-400MP2 GPU & H.264/H.265 VCU.
³ SYSMONE4 supports 10bit 200KSPS ADC and supports upto 17 Analog Inputs (One dedicated Analog input and 16 auxiliary analog input from any PL BANK)
4 GTH Transceiver block is supported in ZU4 & ZU5 MPSoC with data rates up to 12.5Gb/s. GTH transceiver block is not supported in ZU2 & ZU3 MPSoC.
“ “ This symbol indicates Hardware assembly options available in the board and by default which option is support ed. Contact iWave to support other assembly option.
Micro SD
(Optional)
DP
Connector ¹
GEM0
ULPI
DDR
Memory
Controller
SD0
DDR4 (64bit)
DDR4 (ECC)
(Optional)
eMMC –8GB
(Upgradable)
DDR4 ECC (8bit)
eMMC (8bit)
USB0
SD1
UART x 1 UART1 Ethernet
PHY1
Gigabit Ethernet1
RGMII
GEM3 Ethernet
PHY2
Gigabit Ethernet2
RGMII
CAN x 2 CAN0, CAN1
Lane2
PS GTR Transceiver
Lane3
Lane0 M.2 Key B
Connector
Lane1
DP (2nd Lane) x 1
SATA/PCIe x 1
USB 3.0/2.0 x 2
DP (1st Lane) x 1
Dual RJ45
Magjack
Processing System(PS)
Quad/Dual ARM Cortex-A53,
Dual Cortex-R5,Mali-400MP2,VCU
Programmable Logic (PL)
I2C0
USB3.0/2.0 x 1
Zynq Ultrascale+ (SFVC784)
ZU4/ZU5 - CG/EG/EV²
ZU2/ZU3 - CG/EG ²
Debug UART
Header
Debug UART UART0
JTAG Header JTAG PS JTAG
SPI0,I2C1
SPI x 1, I2C x 1
HD Bank
43,44
FPGA (13LVDS/26SE)
USB3.0 x 1
Dual Stack
USB 3.0 TypeA
Nano SIM
Connector
SIM
HP
Bank 64
FPGA IOs
Antenna
Connectors
RF (WLAN, BT )
SD (4bit) x 1
Bank 224
CH3
GTH Transceiver 4
High Speed Transceiver x 1 4
SDI Video Out
BNC Jack
(Optional)
SDI Video In
BNC Jack
(Optional)
SFP+ Conn
12V Power
Connector Power
Regulators Power to
Peripherals
12V
RTC Coin cell
Header PMIC
HP Bank
65,66
DDR4 –1GB
(Upgradable)
DDR4 (32bit)
HD Bank
46
B2B
Connector 3
B2B
Connector 1
FPGA (12LVDS/24SE) ³
B2B
Connector 2
FPGA (23LVDS/46SE)
HD Bank
45
FPGA (4LVDS/8SE)
HDMI Output
Connector
HDMI Input
Connector
Bank 224
CH[2:0]
High Speed Transceiver x 3
FPGA (7LVDS/14SE)
SYSMONE4
From B2B Connecor2
I2C x 1
FPGA (2LVDS/4SE)
From 45 HD Bank
Clock
Generator
To Transceiver
Bank
Figure 1: Zynq Ultrascale+ MPSoC SBC Block Diagram
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2.1.1 Zynq Ultrascale+ MPSoC SBC Features
The Zynq Ultrascale+ MPSoC SBC supports the following features.
SoC
•Xilinx Zynq Ultrascale+ MPSoC
➢Compatible Zynq Ultrascale+ MPSoC Family (SFVC784) –ZU4EV, ZU5EV
Programming Logic with up to 256K Logic cells and Processing System with integrated Quad-core
ARM Cortex-A53 MPCore Application processor (up to 1.5GHz), Dual-core ARM Cortex-R5 MPCore
Real Time Processor (up to 600MHz) and Mali™-400 MP2 Graphics Processor and H.264/H.265
Video Codec.
➢Compatible Zynq Ultrascale+ MPSoC Family (SFVC784) –ZU2EG, ZU3EG, ZU4EG, ZU5EG
Programming Logic with up to 256K Logic cells and Processing System with integrated Quad-core
ARM Cortex-A53 MPCore Application processor (up to 1.5GHz), Dual-core ARM Cortex-R5 MPCore
Real Time Processor (up to 600MHz) and Mali™-400 MP2 Graphics Processor.
➢Compatible Zynq Ultrascale+ MPSoC Family (SFVC784) –ZU2CG, ZU3CG, ZU4CG, ZU5CG
Programming Logic with up to 256K Logic cells and Processing System with integrated Dual-core
ARM Cortex-A53 MPCore Application processor (up to 1.3GHz), Dual-core ARM Cortex-R5 MPCore
Real Time Processor (up to 533MHz).
PMIC
•Dialog’s DA9063 PMIC with RTC
Memory
•2GB DDR4 SDRAM (64bit) for PS (Expandable)
•1GB DDR4 SDRAM (32bit) for PL (Expandable)
•8GB eMMC Flash (Expandable)
•EEPROM For MAC Address
•Micro SD Connector (Optional) 1
Features from PS Block
•Dual 10/100/1000Mbps Ethernet through RJ45 Magjack
•WLAN & BT Module with Antenna connector 1,2
•Debug UART Header
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Features from PS-GTR Transceiver
•Display Port Connector (Dual Lane upto 4K@30)
•Dual USB3.0 Type A Jack
•M.2 Key B Connector with SATA, PCIex1 and USB3.0
Features from PL-GTH Transceiver 3
•HDMI Input Connector (Upto 4K@60)
•HDMI Output Connector (Upto 4K@60)
•10G SFP+ Connector 4
•3G/12G SDI Input through HD BNC Jack (Optional) 4
•3G/12G SDI Output through HD BNC Jack (Optional) 4
Additional Features
•Clock Synthesizer/Generator
•JTAG Header
•FAN Header
•RTC Coin Cell Header
•Power On/OFF & Reset Switch
Board to Board Connector1 Interfaces (60pin)
From PS Block
•DATA UART1 x 1 Port 2
•SPI x 1 Port
•I2C1 x 1 Port
•CAN x 2 Ports
From PL Block
•PL IOs - HP Bank64
➢Upto 13 LVDS IOs/26 Single ended (SE) IOs
oUpto 3 GC Global Clock Input pins (LVDS/SE)
oUpto 8 ADC Input pins (Differential/Single Ended)
oVariable IO voltage support from 1.2V to 1.8V
•PL IOs - HD Bank45 ⁵
➢Upto 4 Single ended (SE) IOs
oVariable IO voltage support from 1.2V to 3.3V
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Board to Board Connector2 Interfaces (60pin)
From PL Block
•PL IOs - HP Bank64
➢Upto 7 LVDS IOs/14 Single ended (SE) IOs
oUpto 1 GC Global Clock Input pins (LVDS/SE)
oUpto 5 ADC Input pins (Differential/Single Ended)
oVariable IO voltage support from 1.2V to 1.8V
•PL IOs - HD Bank45 ⁵
➢Upto 4 LVDS IOs/8 Single ended (SE) IOs
oUpto 4 ADC Input pins (Differential/Single Ended)
oVariable IO voltage support from 1.2V to 3.3V
•PL IOs - HD Bank46 ⁵
➢Upto 12 LVDS IOs/24 Single ended (SE) IOs
oUpto 4 GC Global Clock Input pins (LVDS/SE)
oUpto 12 ADC Input pins (Differential/Single Ended)
oVariable IO voltage support from 1.2V to 3.3V
•One dedicated ADC Input (Differential) from SYSMONE4
Board to Board Connector3 Interfaces (60pin)
From PL Block
•PL IOs - HD Bank43 ⁵
➢Upto 11LVDS IOs/22 Single ended (SE) IOs
oUpto 3 GC Global Clock Input pins (LVDS/SE)
oUpto 11 ADC Input pins (Differential/Single Ended)
oVariable IO voltage support from 1.2V to 3.3V
•PL IOs - HD Bank44 ⁵
➢Upto 12 LVDS IOs/24 Single ended (SE) IOs
oUpto 4 GC Global Clock Input pins (LVDS/SE)
oUpto 8 ADC Input pins (Differential/Single Ended)
oVariable IO voltage support from 1.2V to 3.3V
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General Specification
•Power Supply : 12V, 5A Power Input Jack
•Form Factor : 72mm x 100mm
1In Zynq Ultrascale+ MPSoC SBC, SD1 signals from MPSoC is shared with WLAN module and MicroSD connector. So
either WLAN or Micro SD connector can be supported. By default WLAN module is supported in SBC. Contact iWave to
support Micro SD connector.
2 In Zynq Ultrascale+ MPSoC SBC, UART1 signals from MPSoC is shared with Bluetooth and Board to Board connector1
So either Bluetooth or Board to Board connector1 UART can be supported. By default UART1 is supported in Bluetooth
in SBC. Contact iWave to support UART1 on Board to Board Connector1.
³ Important Note: Since PL-GTH Transceivers are not supported in ZU3 & ZU2 Zynq Ultrascale+MPSoC, these features
from PL-GTH are not supported in ZU3 & ZU2 Zynq Ultrascale+MPSoC based SBC.
4 In Zynq Ultrascale+ MPSoC SBC, GTH Transceiver Channel3 is shared with SFP+ and SDI In & Out. So either SFP+ or SDI
IN & Out only can be supported. By default SFP+ is supported in SBC. Contact iWave to support SDI IN & Out.
⁵In ZCU2 & ZCU3 MPSoC devices, the PL Bank 43, 44, 45 & 46 is called as 44, 24, 25 & 26 respectively. Only the Bank
Numbering is different and all other functionalities remain same.
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2.2 Zynq Ultrascale+ MPSoC
Xilinx’s SoC portfolio integrates the software programmability of a processor with the hardware programmability of
an FPGA, providing unrivalled levels of system performance, flexibility, and scalability. Unlike traditional SoC
processing solutions, the flexible programmable logic provides optimization and differentiation, allowing to add the
peripherals and accelerators for a broad base of applications.
The Zynq Ultrascale+ MPSoC SBC is based on Xilinx Zynq Ultrascale+ MPSoC with SFVC784 package. Zynq Ultrascale+
MPSoC family integrates Processing system (PS) and Xilinx programmable logic (PL) in a single device. MPSoC’s
Processing system includes feature-rich Quad-core ARM Cortex-A53 MPCore up to 1.5 GHz of Application processor,
Dual-core ARM Cortex-R5 MPCore up to 600MHz, Mali™-400 MP2 of Graphics Processor and H.264/H.265 Video
Codec. The Block Diagram of Zynq Ultrascale+ MPSoC from Xilinx website is shown below for reference.
Figure 2: Zynq Ultrascale+ MPSoC CPU Simplified Block Diagram
Note: Please refer the latest Zynq Ultrascale+ MPSoC Datasheet & Technical Reference Manual for more details which
may be revised from time to time.
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The Zynq Ultrascale+ MPSoC SBC is compatible to ZU2CG, ZU3CG, ZU4CG, ZU5CG, ZU2EG, ZU3EG, ZU4EG, ZU5EG,
ZU4EV and ZU5EV MPSoC devices and feature comparison between these devices are shown below.
Figure 3: Zynq Ultrascale+ MPSoC Devices Comparison
The Zynq Ultrascale+ MPSoC’s PS has 78 dedicated I/O pins referred as MIO (Multiplexed I/O) for the PS peripheral
interfaces. These 78 MIO pins are divided into three banks (PS BANK500, 501 & 502) and each bank includes 26 device
pins. Since 78 MIO pins are not enough to support simultaneous use of all the peripherals supported by PS, there is
option in MPSoC to route most of the IO peripheral interfaces to PL Bank I/O pins referred as EMIO (Extended MIO).
Zynq Ultrascale+ MPSoC’s PS Peripheral Pin mapping options between MIO & EMIO is shown below.
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Peripheral
Interface
MIO
EMIO
Quad-SPI
NAND
Yes
No
USB2.0: 0,1
Yes: External PHY
No
SDIO 0,1
Yes
Yes
SPI: 0,1
I2C: 0,1
CAN: 0,1
GPIO
Yes
CAN: External PHY
GPIO: Up to 78 bits
Yes
CAN: External PHY
GPIO: Up to 96 bits
GigE: 0,1,2,3
RGMII v2.0:
External PHY
Supports GMII, RGMII v2.0 (HSTL), RGMII v1.3, MII, SGMII, and
1000BASE-X in Programmable Logic
UART: 0,1
Simple UART:
Only two pins (TX and RX)
Full UART (TX, RX, DTR, DCD, DSR, RI, RTS, and CTS) requires either:
• Two Processing System (PS) pins (RX and TX) through MIO and six
additional Programmable Logic (PL) pins, or
• Eight Programmable Logic (PL) pins
Debug Trace
Ports
Yes: Up to 16 trace bits
Yes: Up to 32 trace bits
Processor JTAG
Yes
Yes
The Zynq Ultrascale+ MPSoC’s PL Banks are classified as high-performance (HP) banks or high-density (HD) banks. The
HP Bank I/Os are optimized for highest performance operation organized in banks of 52pins. The HD Bank I/Os are
reduced-feature I/Os organized in banks of 24pins.
In Zynq Ultrascale+ MPSoC PL, each bank supports four global clock (GC or HDGC) input pin pairs. GC pins have direct
access to the global clock buffers, MMCMs and PLLs of the same Bank. HDGC pins are from HD I/O banks and have
direct access only to the global clock buffers.
Also Zynq Ultrascale+ MPSoC supports one types of high speed transceivers namely GTH and PS-GTR. These
transceivers are arranged in groups of four known as a transceiver Quad. GTH transceivers are from PL and PS-GTR
transceivers are from PS.
2.2.1 MPSoC Power
The Zynq Ultrascale+ MPSoC SBC uses discrete power regulators along with DA9063 PMIC from Dialog Semiconductor
for MPSoC power management. In SBC, PS low-power domain, PS full-power domain & PL power domain supply
voltage (VCC_PSINTLP, VCC_PSINTFP, VCCINT) is fixed to 0.85V or 0.9V based on the speed grade of the MPSoC. Also
all PS Bank (VCCO_PSIO) I/O voltage is fixed to 1.8V.
The I/O voltage of PL HP Banks (PL Bank 64) and PL HD Banks (PL Bank 43, 44, 45 & 46) which are connected to Board
to Board Connectors are generated from PMIC LDO1 and LDO6, LDO3, LDO4, & LDO7 respectively. By default, HP Banks
and HD Banks voltages are set to 1.2V and configurable through software after bootup
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2.2.2 MPSoC Reset
The Zynq Ultrascale+ MPSoC SBC uses PMIC’s Reset output (nRESET) for PS Power On Reset and connected to
PS_POR_B pin of MPSoC. Also it supports warm reset input from Reset Switch (SW2) and connected to PS_SRST_B pin
of MPSoC.
2.2.3 MPSoC Reference Clock
The Zynq Ultrascale+ MPSoC SBC supports on board clock oscillators for reference clock to different blocks of Zynq
Ultrascale+ MPSoC. These reference clock details are mentioned in the below table.
Table 3: Zynq Ultrascale+ MPSoC SBC Reference Clock.
Sl.
No
On-SBC Oscillator
Frequency
SoC Ball Name/
Pin Number
Signal Type/
Termination
Description
1
33.33MHz
PS_REF_CLK /
R16
1.8V, LVCMOS
33.33Mhz single ended reference
clock for PS.
2
100MHz¹
IO_L5P_HDGC_AD7P_43 /
AE12
1.8V², LVCMOS
100Mhz single ended reference
clock for PL. This is connected to PL
Bank43 HDGC Global clock pin.
3
300MHz
IO_L13N_T2L_N1_GC_QBC_66 /
D6
IO_L13P_T2L_N0_GC_QBC_66 /
D7
1.8V, LVDS
LVDS reference clock for PL DDR4
SDRAM. This is connected to PL
Bank66 Global clock pins.
¹ Important Note: I/O voltage of PL Bank43 is software configurable. Since this oscillator supports 1.8V to 3.3V VCC
only, this reference clock can be used only if the I/O voltage of PL Bank43 is set between 1.8V to 3.3V.
²Mentioned voltage level is based on after uboot bootup I/O voltage set to PL Bank43.
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2.2.4 MPSoC Configuration & Status
The Zynq Ultrascale+ MPSoC uses multi-stage boot process that supports both a non-secure and a secure boot. The PS
is the master of the boot and configuration process. Upon reset, device executes code out of on-chip ROM and copies
the first stage boot loader (FSBL) from the boot device to the on-chip RAM. The FSBL initiates the boot of the PS and
can load and configure the PL or configuration of the PL can be deferred to a later stage.
The Zynq Ultrascale+ MPSoC SBC supports two LEDs for the MPSoC error status indication namely PS_ERROR_OUT and
PS_ERROR_STATUS. LED D1 is for PS_ERROR_OUT and it is asserted for accidental loss of power, a hardware error, or
an exception in the PMU. LED D7 is for PS_ERROR_STATUS and it indicates a secure lockdown state. Alternatively, it
can be used by the PMU firmware to indicate system status.
Figure 4: Error Status Indication LEDs
2.2.5 MPSoC Boot Mode
The Zynq Ultrascale+ MPSoC always boots from PS first and configures the PL through software. MPSoC can support
eMMC, SD1, USB0 & JTAG as boot device and configurable through mode pins. Upon device reset, MPSoC mode pins
are read to determine the primary boot device. By default, eMMC is supported as boot device in SBC.
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