iWave iW-RainboW-G47M Installation manual

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Kintex Ultrascale+ FPGA SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
iW-RainboW-G47M
Kintex Ultrascale+ FPGA SOM
Hardware User Guide

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Kintex Ultrascale+ FPGA SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Document Revision History
Document Number
iW-PRHBZ-UM-01-R1.0-REL0.1-KU19P-FPGA-SOM-HardwareUserGuide
Release
Date
Description
0.1
29th Aug 2022
Initial Draft Version
PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the intended recipient(s). Do not read this
document if you are not the intended recipient. Any review, use, distribution or disclosure by others is strictly prohibited. If you
are not the intended recipient (or authorized to receive for the recipient), you are hereby notified that any disclosure, copying
distribution or use of any of the information contained within this document is STRICTLY PROHIBITED. Thank you. “iWave Systems
Tech. Pvt. Ltd.”

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iWave Systems Technologies Pvt. Ltd.
Disclaimer
iWave Systems reserves the right to change details in this publication including but not limited to any Product specification without
notice.
No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted
by law no liability (including liability to any person by reason of negligence) will be accepted by iWave Systems, its subsidiaries or
employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document.
CPU and other major components used in this product may have several silicon errata associated with it. Under no circumstances,
iWave Systems shall be liable for the silicon errata and associated issues.
Trademarks
All registered trademarks, product names mentioned in this publication are the property of their respective owners and used for
identification purposes only.
Certification
iWave Systems Technologies Pvt. Ltd. is an ISO 9001:2015 Certified Company.
Warranty & RMA
Warranty support for Hardware: 1 Year from iWave or iWave's EMS partner.
For warranty terms, go through the below web link,
http://www.iwavesystems.com/support/warranty.html
For Return Merchandise Authorization (RMA), go through the below web link,
http://www.iwavesystems.com/support/rma.html
Technical Support
iWave Systems technical support team is committed to provide the best possible support for our customers so that our Hardware
and Software can be easily migrated and used.
For assistance, contact our Technical Support team at,
Email : [e-mail]
Website : www.iwavesystems.com
Address : iWave Systems Technologies Pvt. Ltd.
# 7/B, 29th Main, BTM Layout 2nd Stage,
Bangalore, Karnataka,
India –560076

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Table of Contents
1. INTRODUCTION.............................................................................................................................................8
1.1 Purpose .......................................................................................................................................................8
1.2 SOM Overview............................................................................................................................................8
1.3 List of Acronyms.........................................................................................................................................8
1.4 Terminology Description.............................................................................................................................9
1.5 References...................................................................................................................................................9
2. ARCHITECTURE AND DESIGN .................................................................................................................10
2.1 Kintex Ultrascale+ FPGA (KU19P) SOM Block Diagram..........................................................................10
2.2 Kintex Ultrascale+ FPGA SOM Features...................................................................................................11
2.3 Kintex Ultrascale+ FPGA..........................................................................................................................14
2.3.1 FPGA & Design Information .................................................................................................................14
2.3.1.1 FPGA Power..................................................................................................................................................... 15
2.3.1.2 FPGA Reset ...................................................................................................................................................... 15
2.3.1.3 FPGA Reference Clock ..................................................................................................................................... 16
2.3.1.4 FPGA Configuration & Status........................................................................................................................... 17
2.3.1.5 FPGA Mode Configuration ............................................................................................................................... 18
2.3.1.6 FPGA System Monitor/ADC.............................................................................................................................. 18
2.3.2 FPGA Memory......................................................................................................................................19
2.3.2.1 DDR4 SDRAM1 with ECC................................................................................................................................ 19
2.3.2.2 DDR4 SDRAM2 with ECC................................................................................................................................ 19
2.4 Layerscape Processor.................................................................................................................................20
2.4.1 Processor & Design Information............................................................................................................20
2.4.1.1 LS1021A Booting and Configuration................................................................................................................. 20
2.4.1.2 LS1021A PMIC................................................................................................................................................. 21
2.4.1.3 LS1021A Reference Clock................................................................................................................................. 21
2.4.2 Processor Memory.................................................................................................................................22
2.4.2.1 DDR4 SDRAM with ECC for LS1021A.............................................................................................................. 22
2.4.2.2 NOR Flash........................................................................................................................................................ 22
2.4.2.3 MRAM .............................................................................................................................................................. 22
2.4.2.4 SRAM................................................................................................................................................................ 22
2.5 FPGA to CPU Interfaces............................................................................................................................23
2.5.1 PCIex1 Gen2 .........................................................................................................................................23
2.5.2 RGMII...................................................................................................................................................23
2.5.3 UART....................................................................................................................................................25
2.5.4 Interrupt Request pins............................................................................................................................25
2.6 Other On SOM Features ............................................................................................................................25
2.6.1 TPM Module.........................................................................................................................................25
2.6.2 Temperature Sensor...............................................................................................................................26
2.7 Board to Board Connector1 .......................................................................................................................27
2.7.1 LS1021A Interfaces...............................................................................................................................31
2.7.1.1 USB3.0.............................................................................................................................................................. 31

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2.7.1.2 SerDes Interface................................................................................................................................................ 31
2.7.1.3 GPIOs From LS1021A...................................................................................................................................... 31
2.7.2 FPGA Interfaces ....................................................................................................................................32
2.7.2.1 GTY High Speed Transceivers........................................................................................................................... 32
2.7.2.2 FPGA IOs –HD BANK92................................................................................................................................. 35
2.7.2.3 FPGA IOs –HP BANK65 & 67......................................................................................................................... 38
2.7.3 Power Control Input...............................................................................................................................40
2.8 Board to Board Connector2 .......................................................................................................................41
2.8.1 LS1021A Interfaces...............................................................................................................................45
2.8.1.1 Gigabit Ethernet Interface................................................................................................................................. 45
2.8.1.2 USB2.0 Interface............................................................................................................................................... 46
2.8.1.3 Debug UART Interface...................................................................................................................................... 46
2.8.1.4 Data UART Interface ........................................................................................................................................ 47
2.8.1.5 I2C Interface..................................................................................................................................................... 47
2.8.1.6 JTAG Interface.................................................................................................................................................. 48
2.8.1.7 SerDes Interface................................................................................................................................................ 48
2.8.1.8 GPIOs From LS1021A...................................................................................................................................... 49
2.8.2 FPGA Interfaces ....................................................................................................................................50
2.8.2.1 FPGA IOs –HP BANK66,65............................................................................................................................. 50
2.8.2.2 FPGA IOs –HP BANK67................................................................................................................................... 55
2.8.3 Power & Reset Input..............................................................................................................................61
2.9 Board to Board Connector3 .......................................................................................................................62
2.9.1 FPGA Interfaces ....................................................................................................................................66
2.9.1.1 GTY High Speed Transceivers........................................................................................................................... 66
2.9.2 Power....................................................................................................................................................71
2.10 Board to Board Connector4 .......................................................................................................................73
2.10.1 FPGA Interfaces ....................................................................................................................................75
2.10.1.1 GTY High Speed Transceivers....................................................................................................................... 75
2.10.2 Power....................................................................................................................................................76
2.11 LS1021A Processor Pin Multiplexing on Board-to-Board Connectors........................................................77
3. TECHNICAL SPECIFICATION...................................................................................................................85
3.1 Electrical Characteristics............................................................................................................................85
3.1.1 Power Input Requirement.......................................................................................................................85
3.1.2 Power Input Sequencing ........................................................................................................................86
3.1.3 Power Consumption...............................................................................................................................87
3.2 Environmental Characteristics ...............................................................................................................88
3.2.1 Temperature Specification ..................................................................................................................88
3.2.2 RoHS2 Compliance..............................................................................................................................88
3.2.3 Electrostatic Discharge........................................................................................................................88
3.2.4 Heat Sink...............................................................................................................................................89
3.3 Mechanical Characteristics ........................................................................................................................90
3.3.1 Kintex Ultrascale+ FPGA SOM Mechanical Dimensions.......................................................................90
4. ORDERING INFORMATION.......................................................................................................................93

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5. APPENDIX......................................................................................................................................................94
5.1 Kintex Ultrascale+ FPGA SOM Development Platform........................................................................94

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List of Figures
Figure 1: Kintex Ultrascale+ FPGA SOM Block Diagram................................................................................................................. 10
Figure 2: Kintex Ultrascale+ FPGA Devices Comparison ................................................................................................................ 14
Figure 3: Indication LEDs.............................................................................................................................................................. 17
Figure 4: LS1021A Internal Block Diagram .................................................................................................................................... 20
Figure 5: Board to Board Connector1 ........................................................................................................................................... 27
Figure 6: Board to Board Connector2 ........................................................................................................................................... 41
Figure 7: Board to Board Connector3 ........................................................................................................................................... 62
Figure 8: Board to Board Connector4 ........................................................................................................................................... 73
Figure 9: Power Input Sequencing................................................................................................................................................ 86
Figure 10: Heat Sink ..................................................................................................................................................................... 89
Figure 11: Mechanical dimension of Kintex Ultrascale+ FPGA SOM - Top View............................................................................. 90
Figure 12: Mechanical dimension of Kintex Ultrascale+ FPGA SOM - Bottom View ....................................................................... 91
Figure 13: Mechanical dimension of Kintex Ultrascale+ FPGA SOM - Side View ............................................................................ 92
Figure 14 Kintex Ultrascale+ FPGA (KU19P) Development Platform.............................................................................................. 94
List of Tables
Table 1: Acronyms & Abbreviations................................................................................................................................................ 8
Table 2: Terminology ..................................................................................................................................................................... 9
Table 3: Board to Board Connector1 Pinout ................................................................................................................................. 28
Table 4: Board to Board Connector2 Pinout ................................................................................................................................. 42
Table 5: Board to Board Connector3 Pinout ................................................................................................................................. 63
Table 6: Board to Board Connector4 Pinout ................................................................................................................................. 74
Table 7: LS1021A IOMUX on Kintex Ultrascale+ FPGA SOM .......................................................................................................... 77
Table 8: Power Input Requirement............................................................................................................................................... 85
Table 9: Power Sequence Timing.................................................................................................................................................. 86
Table 10: Temperature Specification............................................................................................................................................ 88
Table 11: Orderable Product Part Numbers.................................................................................................................................. 93

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1. INTRODUCTION
1.1 Purpose
This document is the Hardware User Guide for the Kintex Ultrascale+ FPGA System on Module based on the Xilinx Kintex Ultrascale+
FPGA (KU19P). This board is fully supported by iWave Systems Technologies Pvt. Ltd. This Guide provides detailed information on
the overall design and usage of the Kintex Ultrascale+ FPGA System on Module from a Hardware Systems perspective.
1.2 SOM Overview
The Kintex Ultrascale+ FPGA (KU19P) SOM is integrated with Xilinx KU19P FPGA SoC and NXP’s LS1021A Layerscape Processor.
Kintex Ultrascale+ FPGA SOM has a form factor of 110mm x 75mm and provides the functional requirements for an embedded
application. Two high speed ruggedized terminal strip connectors and Two High-Speed High-Density connectors provide the carrier
board interface to carry all the I/O signals to and from the Kintex Ultrascale+ FPGA SOM.
1.3 List of Acronyms
The following acronyms will be used throughout this document.
Table 1: Acronyms & Abbreviations
Acronyms
Abbreviations
ADC
Analog to Digital Converter
ARM
Advanced RISC Machine
BSP
Board Support Package
RCW
Reset Configuration Word
CPU
Central Processing Unit
DDR4 SDRAM
Double Data Rate fourth-generation Synchronous Dynamic Random Access Memory
FPGA
Field Programmable Gate Array
PBL
Pre-boot Loader
GB
Giga Byte
Gbps
Gigabits per sec
IFC
Integrated Flash Controller
GHz
Giga Hertz
GPIO
General Purpose Input Output
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
JTAG
Joint Test Action Group
Kbps
Kilobits per second
LVDS
Low Voltage Differential Signalling
MAC
Media Access Controller
MB
Mega Byte
Mbps
Megabits per sec
MHz
Mega Hertz

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Acronyms
Abbreviations
MRAM
Magneto-resistive Random Access Memory
PCB
Printed Circuit Board
PMIC
Power Management Integrated Circuit
SRAM
Static Random Access Memory
PL
Programmable Logic
PS
Processing System
RGMII
Reduced Gigabit Media Independent Interface
RTC
Real Time Clock
TPM
Trusted Platform Module
1.4 Terminology Description
In this document, wherever Signal Type is mentioned, below terminology is used.
Table 2: Terminology
Terminology
Description
I
Input Signal
O
Output Signal
IO
Bidirectional Input/output Signal
CMOS
Complementary Metal Oxide Semiconductor Signal
LVDS
Low Voltage Differential Signal
GBE
Gigabit Ethernet Media Dependent Interface differential pair signals
USB
Universal Serial Bus differential pair signals
OD
Open Drain Signal
OC
Open Collector Signal
Power
Power Pin
PU
Pull Up
PD
Pull Down
NA
Not Applicable
NC
Not Connected
1.5 References
•Kintex Ultrascale+ FPGA Technical Reference Manual
•Kintex Ultrascale+ FPGA Device Overview
•Kintex Ultrascale+ FPGAs Data Sheet: DC and AC Switching Characteristics
•QorIQ LS1021A Reference Manual
•QorIQ LS1021A Data Sheet

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2. ARCHITECTURE AND DESIGN
This section provides detailed information about the Kintex Ultrascale+ FPGA (KU19P) SOM features and Hardware architecture
with high level block diagram. Also, this section provides detailed information about Board-to-Board connectors pin assignment
and usage.
2.1 Kintex Ultrascale+ FPGA (KU19P) SOM Block Diagram
Kintex Ultrascale+ KU19P FPGA (B2104) SOM Block Diagram
Board to Board
High Speed
Connector2
(240Pin)
Board to Board
High Speed
Connector1
(240Pin)
Kintex Ultrascale+
KU19P (B2104)
Dual Arm® Cortex®-A7CPU
PCIe 2.0 x1
GTY Transceiver
DDR4
Controller
Ethernet1 Ethernet
PHY
Gigabit Ethernet
RGMII
USB1
USB 2.0 x 1
I2C x 2
Board to Board
High Speed
Connector3
(240Pin)
Board to Board
High Speed
Connector4
(80Pin)
FPGA IOs
DDR4
(64bit, 8bit ECC)
Bank
69,70, 71 DDR4 –4GB
Bank
72,73,74 DDR4 –4GB
Bank
228[2:0]
229,
230,
231,
232
GTY
Transceiver
Bank
225,
226
Bank
227
Bank
65, 67, 92
Bank 66,67
FPGA IOs
High Speed Transceiver (8 Channels)
High Speed Transceiver (4 Channels)
High Speed Transceiver (19 Channels)
Power
Regulators
Power to
Peripherals
5V
FPGA IOs (16LVDS/36SE/11ADC)
FPGA IOs (46LVDS/106SE/32ADC)
Configuration
Interface
QSPI
QSPI Flash
(128MB)
Bank
228[3]
DDR4
(64bit, 8bit ECC)
UART UART x 3
I2C
JTAG
RP
EP
Compatible FPGAs:
VU9P, VU11P, VU13P
228[3]
DDR4
(32bit, 4bit ECC)
DDR4 –2GB
SPI
NOR Flash
(256MB)
MRAM
(4MB)
IFC
SPI
SRAM
(512KB)
TPM 2.0
Parallel 16bit
SERDES [0]
Temperature
Sensor
I2C2
Bank 65
Ethernet3,
UART
RGMII, UART
Resistors
228[3]
2:1
MUX/DEMUX
CPU_JTAG
JTAG CPU_JTAG
USB 3.0 X1
USB 3.0 x 1
SERDES x 2 (PCIe/SATA/SGMII)
SERDES
[3:1]
SERDES x 1
SERDES x 1 (With REFCLK)
Figure 1: Kintex Ultrascale+ FPGA SOM Block Diagram

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2.2 Kintex Ultrascale+ FPGA SOM Features
The Kintex Ultrascale+ FPGA (KU19P) SOM supports the following features.
FPGA
•Xilinx Kintex Ultrascale+ FPGA
➢Kintex Ultrascale+ FPGA (FBVB2104) Package
System Logic cells up to 1.843K Logic cells and up to 1.685K Configurable Logic Blocks.
➢UltraRAM for on-chip memory integration
➢Integrated 100G Ethernet MAC with KR4 RS-FEC, PCIe® Gen4, and 150G Interlaken cores
➢16G and 28G backplane-capable transceivers
PMIC
•Dialog’s DA9062 PMIC (RTC is optional)
Memory
•4GB DDR4 SDRAM1 (64bit) with 8-bit ECC (Expandable)
•4GB DDR4 SDRAM2 (64bit) with 8-bit ECC (Expandable)
•128MB QSPI Flash.
CPU
•QorIQ LS1021A Processor
➢Arm® Cortex®-A7 MPCore compliant with Armv7-A™ architecture. LS1021A contains a dual-core Cortex-A7 cores
running up to 1.2 GHz
➢32 KB instruction and data L1 cache with single bit error detection and correction, ECC protection on both
instruction and data caches
•Up to 512 KB coherent L2 cache with single bit error detection and correction, ECC protection
PMIC
•Dialog’s DA9062 PMIC (with RTC)
Memory
•2GB DDR4 SDRAM (32bit) with 4-bit ECC (Expandable)
•256MB NOR Flash (16bit)
•4MB MRAM (16bit)
•512KB SRAM

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FPGA to CPU Interfaces
•PCIex1 Gen2
•RGMII
•UART
•Slide IDs
•Interrupt Request Pins
Other On-SOM Features
•TPM 2.0 Module
•Temperature Sensor
•Gigabit Ethernet PHY Transceiver
•Clock Synthesizer for On-SOM Clocks
•Fan Header (Optional)
Board to Board Connector1 Interfaces (240pin)
From LS1021a
•USB 3.0 x 1
•1 SerDes lane for high-speed peripheral interface with reference clock
•6 GPIOs From LS1021A
From KU19P
•GTY High Speed Transceivers (up to 32.75Gbps) x 8
•FPGA IOs - HD Bank 92
➢Up to 11 LVDS IOs/22 Single ended (SE) IOs
oUp to 3 HDGC Global Clock Input pins (LVDS/SE)
oUp to 11 ADC Input pins (Differential/Single Ended)
•FPGA IOs - HP Bank 65,67
➢Up to 5 LVDS IOs/14 Single ended (SE) IOs
oUp to 4 HDGC Global Clock Input pins (LVDS/SE)
Board to Board Connector2 Interfaces (240pin)
From LS1021a
•Gigabit Ethernet x 1 Port (through On-SOM Gigabit Ethernet PHY)
•USB2.0 x 1 Port
•Debug UART x 1 Port

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•Data UART x 2 Port
•I2C x 2 Ports
•JTAG x1 Port
•Up to 2 SerDes lanes for high-speed peripheral interfaces (PCIe, SATA, SGMII)
•10 GPIOs From LS1021A
From KU19P
•FPGA IOs - HP Bank 65,66
➢Up to 24 LVDS IOs/52 Single ended (SE) IOs
oUp to 4 GC Global Clock Input pins (LVDS/SE)
oUp to 16 ADC Input pins (Differential/Single Ended)
•FPGA IOs - HP Bank 67
➢Up to 22 LVDS IOs/44 Single ended (SE) IOs
oUp to 4 GC Global Clock Input pins (LVDS/SE)
oUp to 15 ADC Input pins (Differential/Single Ended)
Board to Board Connector3 Interfaces (240pin)
From KU19P
•GTY High Speed Transceivers (up to 32.75Gbps) x 201
Board to Board Connector4 Interfaces (80pin)
From KU19P
•GTY High Speed Transceivers (up to 32.75Gbps) x 4
General Specification
•Power Supply : 5V (from Board-to-Board Connector2)
•Form Factor : 110mm x 75mm
1In Board-to-Board Connector3, by default one GTY transceiver link is connected with on-SOM PCIe transceiver.

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2.3 Kintex Ultrascale+ FPGA
2.3.1 FPGA & Design Information
The Kintex Ultrascale+ FPGA SoC provides best performance with up to 40% lower power than previous generation Kintex series
due to enhanced system logic cell packaging. This also includes the highest signal processing bandwidth in a mid-range device, next
generation transceivers. The family is ideal for DSP intensive processing required for next generation and packet processing in 100G
networking.
Note: Please refer the latest Kintex Ultrascale+ FPGA Datasheet & Technical Reference Manual for more details which may be revised
from time to time.
Figure 2: Kintex Ultrascale+ FPGA Devices Comparison
The Kintex Ultrascale+ FPGA’s IO Banks are classified as high-performance (HP) banks or high-density (HD) banks. The HP Bank
I/Os are optimized for highest performance operation organized in banks of 52pins. The HD Bank I/Os are reduced-feature I/Os
organized in banks of 24pins.
In Kintex Ultrascale+ FPGA, each IO bank supports four global clock (GC or HDGC) input pin pairs. GC pins have direct access to
the global clock buffers, PLLs of the same Bank. HDGC pins are from HD I/O banks and have direct access only to the global clock
buffers. Also, Kintex Ultrascale+ FPGA supports high speed GTY transceivers.

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2.3.1.1 FPGA Power
The Kintex Ultrascale+ FPGA SOM uses discrete power regulators along with DA9062 PMIC from Dialog Semiconductor for FPGA
power management. In SOM, FPGA power domain supply voltage (VCC_INT, VCCINT_IO, VCCBRAM) is fixed to 0.85V or 0.9V based
on the speed grade of the FPGA.
The Kintex Ultrascale+ FPGA SOM supports Dialog semiconductor DA9062 PMIC for other powers to FPGA. The I2C2 module of
LS1021A is used for FPGA PMIC interface with I2C address 0x48. The I/O voltage of HD Bank (PL Bank 92) and HP Banks (Bank 65,
66 & 67) which are connected to Board-to-Board Connectors are generated from PMIC LDO1, LDO2, LDO3 and LDO4 respectively.
PMIC’s LDO1 is connected to I/O voltage of HD Bank92 and by default set to 1.2V, LDO2 is connected to I/O voltage of HP Bank65
and by default set to 1.8V, LDO3 is connected to HP Bank66 and by default set to 1.0V, LDO4 is connected to I/O voltage of HP
Bank67 and by default set to 1.0V. IO voltage is configurable through software after LS1021A boot-up.
PMIC supports reset output and connected to Kintex Ultrascale+ FPGA AL28 pin (IO_L24N_T3U_N11_DOUT_CSO_B_65) for power
on reset. Also, PMIC supports IRQ output for events indication and connected to FPGA BC28 pin (IO_T1U_N12_SMBALERT_65).
Important Note: Every Power Off and On, The DA9062 PMIC work as initial OTP Setting
2.3.1.2 FPGA Reset
The Kintex Ultrascale+ FPGA SOM uses PMIC’s Reset output (nRESET) for FPGA Power On Reset and connected to AL28 pin
(IO_L24N_T3U_N11_DOUT_CSO_B_65) of FPGA.

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2.3.1.3 FPGA Reference Clock
The Kintex Ultrascale+ FPGA SOM supports on board clock synthesizer for reference clock to different blocks of Kintex Ultrascale+
FPGA and LS1021A processor. The reference clock from Clock Synthesizer to FPGA is mentioned in the below table.
Sl.
No
On-SOM
Clock
Synthesizer
Frequency
FPGA Pin Name
FP
GA
Ban
k
FPGA
Pin No
Signal Type/
Termination
Description
Stability
1
300MHz
IO_L13P_T2L_N0_G
C_QBC_68
68
G14
1.8V, LVDS
LVDS reference clock for FPGA
DDR4 SDRAM1. This is
connected to FPGA Bank68
Global clock pins.
NA
IO_L13N_T2L_N1_G
C_QBC_68
F14
2
300MHz
IO_L13P_T2L_N0_G
C_QBC_71
71
J26
1.8V, LVDS
LVDS reference clock for FPGA
DDR4 SDRAM2. This is
connected to FPGA Bank71
Global clock pins.
NA
IO_L13N_T2L_N1_G
C_QBC_71
H26
NA
3
125MHz
IO_L7P_HDGC_AD5
P_92
92
AN22
1.8V, LVDS
Reference clock for FPGA. This
is connected to FPGA Bank92
HDGC Global clock pin.
NA
IO_L7N_HDGC_AD5
N_92
AN21
NA
4
100MHz
MGTREFCLK0P_228
228
AH11
1.8V, LVDS
Bank228 PCIe Reference
Clock0.
NA
MGTREFCLK0N_228
AH10
NA
5
125MHz
IO_L24P_T3U_N10_
EMCCLK_65
65
AL27
1.8V, LVCMOS
External Master Clock
NA

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2.3.1.4 FPGA Configuration & Status
In Kintex Ultrascale+ SOM, by default QSPI Flash is set as configuration device through mode pins. Memory configuration files are
generated from the BIT file in Vivado is programmed to QSPI through JTAG.
Figure 3: Indication LEDs
The Kintex Ultrascale+ FPGA SOM supports two LEDs for the Program Done indication and Power LED indication. LED D2 is for
PROG_DONE and it is asserted for DONE indicates successful completion of configuration. LED D1 is for Power LED and it indicates
the power which is the final in the power sequence.
The Kintex Ultrascale+ FPGA SOM supports three dedicated input and output configuration pins. By default, Weak pre -
reconfiguration I/O pull-up resistors disabled for PUDC_B pin, Standard FPGA power-on delay time for POR_OVERRIDE pin is
connected to Ground through 4.7K.

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2.3.1.5 FPGA Mode Configuration
The Kintex Ultrascale+ SOM provides mode pins for selection of configuration device. The SOM supports 4-bit QSPI Flash and JTAG
for the configuration of FPGA. By default, mode bit is configured to “001” for QSPI Flash as configuration device.
Below table provides the Mode bit status for available configuration devices of SOM.
MODE2
MODE1
MODE0
CONFIGURATION
MODE
0
0
1
QSPI
1
0
0
JTAG
2.3.1.6 FPGA System Monitor/ADC
The Kintex Ultrascale+ FPGA contain one System Monitor block (SYSMONE4). It is used to enhance the overall safety, security and
reliability of the system by monitoring the physical environment via on-chip power supply and temperature sensors.
The SYSMON uses 10-bit 200kSPS ADC to digitize the sensor/ADC inputs. It monitors the die temperature of the FPGA and several
internal supply nodes. The SYSMON can also monitor up to 17 external analog channels which includes 16 auxiliary analog inputs
and one VP_VN dedicated input. The external auxiliary inputs can be routed through any IO Bank. The ADC voltage reference is
selectable between an internal reference and the external pins VREFP and VREFN. In Kintex Ultrascale+ FPGA SOM, 1.25V external
voltage reference is supported.

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2.3.2 FPGA Memory
2.3.2.1 DDR4 SDRAM1 with ECC
The Kintex Ultrascale+ FPGA SOM supports 64bit, 4GB DDR4 RAM memory for FPGA. Four 16 bit, 1GB DDR4 SDRAM ICs is used to
support RAM memory of 4GB. These DDR4 devices operates at 2666Mbps data rate. In Kintex Ultrascale+ FPGA SOM, Bank64, 65
& 66 is used for FPGA DDR4 SDRAM1 interface. The RAM size can be expandable up to maximum of 16GB based on the availability
of higher density 16bit DDR4 device.
The Kintex Ultrascale+ FPGA SOM supports 300MHz LVDS DDR4 reference clock from on board clock synthesizer and connected to
Bank64 AT21 & AT22 dedicated clock input pins through AC Coupling capacitors.
Note: Kintex Ultrascale+ FPGA SOM with -2 & -3 speed grade FPGA can support up to 2666Mbps data rate for FPGA DDR4.
2.3.2.2 DDR4 SDRAM2 with ECC
The Kintex Ultrascale+ FPGA SOM supports 64bit, 4GB DDR4 RAM memory for FPGA’s FPGA. Four 16 bit, 1GB DDR4 SDRAM ICs is
used to support RAM memory of 4GB. These DDR4 devices operates at 2666Mbps data rate. In Kintex Ultrascale+ FPGA SOM,
Bank69, 70 & 71 is used for FPGA SDRAM2 DDR4 interface. Also, Both SDRAM1 and SDRAM2 supports two 4bit ECC for RAM
memory. The RAM size can be expandable up to maximum of 16GB based on the availability of higher density 16bit DDR4 device.
The Kintex Ultrascale+ FPGA SOM supports 300MHz LVDS DDR4 reference clock from on board clock synthesizer and connected to
Bank71 J26 & H26 dedicated clock input pins through AC Coupling capacitors.
Note: Kintex Ultrascale+ FPGA SOM with -2 & -3 speed grade FPGA can support up to 2666Mbps data rate for FPGA DDR4.

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2.4 Layerscape Processor
2.4.1 Processor & Design Information
The Kintex Ultrascale+ FPGA (KU19P) SOM is based on Xilinx Kintex Ultrascale+ FPGA (KU19P) integrated with LS1021A
Layerscape Processor. Featuring a pair of extremely power-efficient 32-bit Arm Cortex-A7 cores with ECC protected L1 and L2
cache memories for high reliability, running up to 1.2 GHz, and providing pre-silicon CoreMark performance of over 5,000, the
LS102xA family delivers greater performance than any previous sub-4W communication processor. The Block Diagram of LS1021A
from NXP website is shown below for reference.
Figure 4: LS1021A Internal Block Diagram
2.4.1.1 LS1021A Booting and Configuration
The Kintex Ultrascale+ SOM integrates KU19P FPGA SoC with L1021A Layerscape processor. The RCW and U-boot is programmed
in to the NOR Flash. On POR, Pre-Boot Loader (PBL) will fetch RCW configuration and PBL commands from NOR flash (chosen by
rcw_src selection pins). Then executes u-boot from NOR flash.