Lattice Semiconductor MachXO3-940 User manual

MachXO3-9400 Development Board
Evaluation Board User Guide
FPGA-EB-02004 Version 1.0
May 2017

MachXO3-9400 Development Board
Evaluation Board User Guide
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02004-1.0
Contents
Acronyms in This Document .................................................................................................................................................5
Introduction ..................................................................................................................................................................6
1.1. MachXO3-9400 Development Board ..................................................................................................................6
1.2. Features...............................................................................................................................................................7
1.3. MachXO3LF Device..............................................................................................................................................8
1.4. L-ASC10 Device....................................................................................................................................................8
Applying Power to the Board........................................................................................................................................9
JTAG/I2C Programming ...............................................................................................................................................11
3.1. JTAG Download Interface..................................................................................................................................11
3.2. I2C Download Interface .....................................................................................................................................12
3.3. Alternate JTAG Download Interface..................................................................................................................12
3.4. JTAG to MSPI Pass-through Interface................................................................................................................12
3.5. Other JTAG Configuration Pins ..........................................................................................................................12
MachXO3 Clock Sources .............................................................................................................................................13
Headers and Test Connections ...................................................................................................................................14
5.1. Versa Headers ...................................................................................................................................................14
5.2. Arduino Board GPIO Headers ............................................................................................................................16
5.3. FX12 Headers (DNI) ...........................................................................................................................................18
5.4. Aardvark Header (DNI) ......................................................................................................................................20
5.5. Raspberry Pi Board GPIO Header ......................................................................................................................21
I2C and SPI Buses.........................................................................................................................................................23
6.1. I2C Topology ......................................................................................................................................................23
6.2. SPI Topology ......................................................................................................................................................25
6.2.1. SPI Configuration ..........................................................................................................................................25
6.2.2. SPI Flash Access.............................................................................................................................................25
LEDs and Switches ......................................................................................................................................................26
7.1. Four-Position DIP Switch ...................................................................................................................................26
7.2. General Purpose Push Buttons..........................................................................................................................27
7.3. General Purpose LEDs .......................................................................................................................................27
7.4. LVDS Outputs Pins .............................................................................................................................................28
7.5. General Purpose DDR Outputs..........................................................................................................................29
ASC Connections .........................................................................................................................................................30
8.1. ASC Interface .....................................................................................................................................................30
8.2. ASC Voltage Monitor .........................................................................................................................................30
8.3. ASC Current Monitor .........................................................................................................................................31
8.4. ASC Temperature Monitor ................................................................................................................................32
8.5. ASC LEDs ............................................................................................................................................................33
8.6. ASC HVOUT and Trim Pins .................................................................................................................................33
Software Requirements ..............................................................................................................................................34
Storage and Handling..............................................................................................................................................34
Ordering Information..............................................................................................................................................34
References ..........................................................................................................................................................................35
Lattice Semiconductor Documents.................................................................................................................................35
Technical Support Assistance...............................................................................................................................................36
Appendix A. MachXO3-9400 Development Board Schematics...........................................................................................37
Appendix B. MachXO3-9400 Development Board Bill of Materials ...................................................................................47
Appendix C. Predefined Preference File Listing ..................................................................................................................54
Appendix D. User Defined Preference File Listing ..............................................................................................................55
Revision History...................................................................................................................................................................60

MachXO3-9400 Development Board
Evaluation Board User Guide
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02004-1.0 3
Figures
Figure 1.1. Top View of MachXO3-9400 Development Board..............................................................................................6
Figure 1.2. Bottom View of MachXO3-9400 Development Board........................................................................................7
Figure 2.1. Board Power Supply............................................................................................................................................9
Figure 3.1. JTAG/I2C Programming Architecture ................................................................................................................11
Figure 3.2. PTM Programming Mode .................................................................................................................................11
Figure 4.1. Optional Clock Circuit Design............................................................................................................................13
Figure 5.1. Aardvark SS Pin Connections ............................................................................................................................20
Figure 6.1. I2C Topology ......................................................................................................................................................23
Figure 6.2. I2C MUX Circuits ................................................................................................................................................24
Figure 7.1. Four-Position DIP Switch Circuits......................................................................................................................26
Figure 7.2. Four-Position DIP Switch Photograph...............................................................................................................26
Figure 7.3. Push Button SW5 Circuit Design .......................................................................................................................27
Figure 7.4. Board LEDs ........................................................................................................................................................28
Figure 8.1. POT Circuit Design for VMON7 .........................................................................................................................31
Figure 8.2. POT Wiper Description .....................................................................................................................................31
Figure 8.3. VCC Core Current Monitoring Circuit................................................................................................................32
Figure 8.4. PNP Temperature Sensor Circuit ......................................................................................................................32
Figure 8.5. NPN Temperature Sensor Circuit......................................................................................................................32
Figure 8.6. ASC LEDs ...........................................................................................................................................................33
Figure A.1. Title Page ..........................................................................................................................................................37
Figure A.2. Block Diagram...................................................................................................................................................38
Figure A.3. USB to JTAG I/F.................................................................................................................................................39
Figure A.4. VERSA Headers (BANK0)...................................................................................................................................40
Figure A.5. Arduino Headers (BANK1) ................................................................................................................................41
Figure A.6. CrossLink Headers (BANK2) ..............................................................................................................................42
Figure A.7. Raspberry Pi Header and Others (BANK3, BANK4, BANK5)..............................................................................43
Figure A.8. Analog Sense and Control ................................................................................................................................44
Figure A.9. Power Decoupling and LEDs .............................................................................................................................45
Figure A.10. Power Regulators ...........................................................................................................................................46

MachXO3-9400 Development Board
Evaluation Board User Guide
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-EB-02004-1.0
Tables
Table 2.1. 5 V Sources and Connections ...............................................................................................................................9
Table 2.2. MachXO3 Power Rail Options ............................................................................................................................10
Table 2.3. ASC Power Connections .....................................................................................................................................10
Table 3.1. JTAG Connections...............................................................................................................................................12
Table 3.2. Other JTAG Signals .............................................................................................................................................12
Table 4.1. JTAG Connections...............................................................................................................................................13
Table 5.1. Versa X2 Header Pin Connections ......................................................................................................................14
Table 5.2. Versa X3 Header Pin Connections ......................................................................................................................15
Table 5.3. Arduino J2 Pin Connections................................................................................................................................16
Table 5.4. Arduino J3 Pin Connections................................................................................................................................17
Table 5.5. Arduino J4 Pin Connections................................................................................................................................17
Table 5.6. Arduino J5 Pin Connections................................................................................................................................17
Table 5.7. FX12 U4 Header Pin Connections.......................................................................................................................18
Table 5.8. FX12 U5 Header Pin Connections.......................................................................................................................19
Table 5.9. Aardvark JP2 Header Pin Connections ...............................................................................................................20
Table 5.10. Raspberry Pi JP3 Header Pin Connections........................................................................................................21
Table 6.1. I2C MUX Function ...............................................................................................................................................23
Table 6.2. I2C Global Bus Connections ................................................................................................................................24
Table 6.3. MachXO3 SPI Connections .................................................................................................................................25
Table 6.4. MachXO3 SPI Configuration Options .................................................................................................................25
Table 7.1. Four-Position DIP Switch Signals ........................................................................................................................26
Table 7.2. Push Button Switch Signals ................................................................................................................................27
Table 7.3. LED Signals .........................................................................................................................................................27
Table 7.4. LVDS Test Points.................................................................................................................................................28
Table 7.5. GDDR Test Points ...............................................................................................................................................29
Table 8.1. ASC to MachXO3 Connections ...........................................................................................................................30
Table 8.2. ASC VMON Connections.....................................................................................................................................30
Table 8.3. ASC IMON Connections......................................................................................................................................31
Table 8.4. ASC TMON Connections .....................................................................................................................................32
Table 8.5. GPIO LED Connections .......................................................................................................................................33
Table 8.6. ASC HVOUT and Trim Connections ....................................................................................................................33
Table 11.1 Ordering Information ........................................................................................................................................34

MachXO3-9400 Development Board
Evaluation Board User Guide
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02004-1.0 5
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
ASC
Analog Sense and Control
CMOS
Complementary Metal-Oxide Semiconductor
GDDR
Graphics Double Data Rate
FTDI
Future Technology Devices International
GPIO
General Purpose Input/Output
I2C
Inter-Integrated Circuit
LVDS
Low-Voltage Differential Signaling
SPI
Serial Peripheral Interface

MachXO3-9400 Development Board
Evaluation Board User Guide
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02004-1.0
Introduction
The Lattice Semiconductor MachXO3-9400™ Development Board allows designers to investigate and experiment with
the features of the MachXO3 complex programmable logic device (CPLD) and the L-ASC10 (L-Analog Sense and Control
10 rails) hardware management expander. The features of the MachXO3-9400 Development Board can assist engineers
with the rapid prototyping and testing of their specific designs.
The MachXO3-9400 Development Board is part of the MachXO3-9400 Development Kit, which includes the following:
MachXO3-9400 Development Board pre-loaded with the demo design
Mini USB cable
QuickStart Guide
This document is intended to be referenced in conjunction with demo user guides for MachXO3-9400. See the
References
The contents of this user guide include top-level functional descriptions of the various portions of the development
board, descriptions of the on-board headers, diodes and switches and a complete set of schematics.
1.1. MachXO3-9400 Development Board
Along with the MachXO3LF-9400 CPLD, the MachXO3-9400 Development Board also features an L-ASC10 device to
enable designers to easily evaluate hardware management design and expand the usability of the MachXO3LF-9400
with Arduino, Raspberry, FX12, Versa and Aardvark headers.
Figure 1.1 shows the top view of the MachXO3-9400 Development Board. Figure 1.2 shows the bottom view of the
board.
Figure 1.1. Top View of MachXO3-9400 Development Board

MachXO3-9400 Development Board
Evaluation Board User Guide
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02004-1.0 7
Figure 1.2. Bottom View of MachXO3-9400 Development Board
1.2. Features
LCMXO3LF-9400C CPLD demonstration with L-ASC10 for simple hardware management including voltage, current
and temperature monitoring
General Purpose Input/Output (GPIO) interface with Arduino and Raspberry Pi boards
USB-B connection for device programming and Inter-Integrated Circuit (I2C) utility
On-board Boot Flash –16 Mbit Serial Peripheral Interface (SPI) Flash, with Quad read feature for user’s application
4-position DIP Switches, 4 push buttons and 16 LEDs for demo purposes
Diamond®programming support
Multiple reference clock sources
Two Hirose FX12-40 header positions (DNI)
Aardvark header (DNI)
Note:
DNI stands for “Do NOT Install” parts and DI stands for “Do Install” parts for assembly.
Caution:
The MachXO3-9400 Development Board contains ESD-sensitive components. ESD safe
practices should be followed while handling and using the development board.

MachXO3-9400 Development Board
Evaluation Board User Guide
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-EB-02004-1.0
1.3. MachXO3LF Device
The MachXO3-9400 Development Board features the MachXO3LF-9400 in 484-ball caBGA package. This MachXO3LF-
9400 device (also referred to as LCMXO3LF-9400C) features 9400 LUTs and 432 kbits of embedded block RAM. This
device offers a variety of features and programmability. For more information on the capabilities of MachXO3™, see
DS1047, MachXO3 Family Data Sheet.
1.4. L-ASC10 Device
The L-ASC10 (also referred to as ASC) is a Hardware Management (Power, Thermal, and Control Plane Management)
Expander designed to be used with Platform Manager 2 or MachXO2/MachXO3 FPGAs to implement the Hardware
Management Control function in a circuit board. The L-ASC10 enables seamless scaling of power supply voltage and
current monitoring, temperature monitoring, sequence and margin control channels. ASC includes dedicated interfaces
supporting the exchange of monitor signal status and output control signals with centralized hardware management
controllers. For more information on the capabilities of ASC device see DS1042, L-ASC10 Data Sheet.

MachXO3-9400 Development Board
Evaluation Board User Guide
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02004-1.0 9
Applying Power to the Board
The MachXO3-9400 Development Board is ready to power on with onboard Low Dropout (LDO) generators powered by
an external 5 V power, as shown in Figure 2.1. The 5 V power can come from a USB connection (J11) and routed to
multiple onboard headers listed Table 2.1. Note that the 5 V power path to headers should be manually connected
using a zero-ohm resistor or jumper before power is applied to the mated board as outlined in Table 2.1.
Table 2.1. 5 V Sources and Connections
Header (Reference)
5 V Power Pins
5 V Power Path (Assembly)
USB header (J11)
1
L3 (DI)
FX12 header 1 (U4)
23, 38
R153 (DNI)
FX12 header 2 (U5)
23, 38
R155 (DNI)
Aardvark header (JP2)
4, 6
R78(DNI), R79 (DNI)
Arduino header (J4)
5
JP6 (DNI)
Raspberry Pi header (JP3)
2, 4
JP7 (DNI)
Versa header (X2)
21
R30 (DNI)
Warning:
Avoid power conflict when the 5 V power path is enabled from the MachXO3-9400
Development Board to the mated board, Do Not apply 5V power from both boards
when the path is manually shorted.
Conversely, 5 V power can be supplied from onboard headers if J11 is not connected to a USB cable. The power from
the headers can be used to drive LDOs and other mated boards.
Aside from the 3.3 V LDO (U8) default power source for MachXO3 device (U3), the board provides additional LDO
footprint (U9) for lower power applications. For example, TLV1117LV12DCY can be used for 1.2 V VCCIOs. Other SOT-
223 footprint compatible LDOs from 1.2 V to 3.3 V can also be considered. VCCIO1 for Bank 1 and VCCIO3 for Bank 3
can likewise be supplied from mated boards. 3.3 V is used for better GPIO voltage alignment.
DNI
DI
USB
Header
(J11)Status LED:
D18
5V USB
R153
R155
R78
R79
JP6
JP7
R30
FX12 Header (U4)
FX12 Header (U5)
Aardvark
Header (JP2)
Arduino
Header (J4)
3.3 V Output
3.3 V LDO (U8)
Raspberry Pi
Header (JP3)
Versa
Header(X2)
3.3 V Output
+3.3 V ASC (U7)
VCC_CORE (U3)
VCCIO0 (U3)
VCCIO1 (U3)
VCCIO2 (U3)
VCCIO3 (U3)
VCCIO4 (U3)
VCCIO5 (U3)
JP1
R127
R124
R151
R126
R133
R139
Optional LDO (U9)
R128
R125
R129
R123
R130
R132
R137
R158
R138
R134
3.3 V
Figure 2.1. Board Power Supply

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10 FPGA-EB-02004-1.0
Table 2.2. MachXO3 Power Rail Options
MachXO3 Device Power (U3)
3.3 V Option (Assembly)
1.2V~3.3 V Option (Assembly)
Mated Board Option (Assembly)
VCC Core
R123 (DI)
R127 (DNI)*
NA
VCCIO0
R124 (DI)
R128 (DNI)
NA
VCCIO1
R125 (DI)
R129 (DNI)
R151 (DNI) for Arduino
VCCIO2
R126 (DI)
R130 (DNI)
NA
VCCIO3
R132 (DI)
R137 (DNI)
R158 (DNI) for Raspberry Pi
VCCIO4
R133 (DI)
R138 (DNI)
NA
VCCIO5
R134 (DI)
R139 (DNI)
NA
*Note: R127 is applicable only in 2.5 V~3.3 V (U9) range for LCMXO3LF-9400C device.
Warning:
Only one option should be enabled for each MachXO3 device power rail.
The ASC device (U7) acquires power from the 3.3 V LDO only. A jumper (JP1) needs to be installed to provide the power
and this can also be used as test point to measure current drawn by the ASC.
Table 2.3. ASC Power Connections
ASC Power
ASC Power Pins
ASC Power Isolation (Assembly)
3.3 V VCC
8, 33 of U7
JP1 (DI)

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© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02004-1.0 11
JTAG/I2C Programming
The JTAG/I2C programming architecture of the MachXO3-9400 Development Board is shown in Figure 3.1.
GND
rst#
Jumper
(JP9)
JTAG
Port 1
Port 0
FT2232H
(U1)
USB
Mini USB
(J11)
MachXO3
(U3)
I2C
ASC (U7)
SPI
SPI
Flash
(U6)
JTAG Header (J1) Raspberry Pi Header (JP3)
Figure 3.1. JTAG/I2C Programming Architecture
3.1. JTAG Download Interface
The MachXO3-9400 Development Board has a built-in download controller for programming the MachXO3 device. It
uses an FT2232H Future Technology Devices International (FTDI) part to convert USB to JTAG. To use the built-in
download cable, connect the USB cable from J11 to your PC (with Diamond programming software installed). A mini
USB to USB-A cable is included in the MarchXO3-9400 Development Kit. The USB hub on the PC detects the cable of the
USB function on Port 0, making the built-in cable available for use with the Diamond programming software. Use PTM
Programming for the Access mode as shown in Figure 3.2.
Figure 3.2. PTM Programming Mode

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-EB-02004-1.0
3.2. I2C Download Interface
The USB hub on the PC can also detect the addition of the USB function on Port 1. Select the port FTUSB-1 on the
programmer interface and enable the I2C MUX path from FTDI to the I2C bus. This is done by setting the J10 jumper
(D57 red LED is lighted). The I2C interface programming can be also used to configure the MachXO3 and ASC.
3.3. Alternate JTAG Download Interface
J1 is an 8-pin standalone JTAG header that is used with an external Lattice download cable (available separately) when
the FTDI part is disabled from the JTAG chain after setting JP9. A USB download cable can be attached to the board
using J1 to interface with the MachXO3. For details on the connection between the USB download cable and J1, refer
to UG48, Programming Cable User’s Guide.
J1 can also be used as test point when USB to JTAG is working. Additionally, you can enable the JTAG access path
through the Raspberry Pi header (JP3) for customer applications. This is done by connecting the JP3 header to the J1
header through some onboard resistors. The JTAG connections between J1 and JP3 are listed in Table 3.1.
Table 3.1. JTAG Connections
J1 Pin Number
JTAG Signal Name
MachXO3 Ball
Location for JTAG
JP3 Pin Number
J1 to JP3 Isolation
(Assembly)
Raspberry Pi GPIO
1
VCCIO0
—
—
—
—
2
TDO
E8
10
R90 (DNI)
IO15
3
TDI
E9
11
R93 (DNI)
IO17
4
—
—
—
—
—
5
—
—
—
—
—
6
TMS
C10
12
R91 (DNI)
IO18
7
GND
—
—
—
—
8
TCK
D10
8
R95 (DNI)
IO14
3.4. JTAG to MSPI Pass-through Interface
The download controller can also access the JTAG to MSPI pass-through circuit that allows the slave SPI Flash to be
erased, programmed, and read with Diamond Programmer.
3.5. Other JTAG Configuration Pins
The MachXO3-9400 Development Board provides test points for other JTAG configuration pins as shown in Table 3.2.
Table 3.2. Other JTAG Signals
Signal Name
MachXO3 Ball Location
Test Point
JTAGENB
E14
TP6
PROGRAMN
E15
Pin 1 of JP5
INITN
F16
TP7
DONE
E17
TP8
For more information on MachXO3 JTAG/ I2C programming, refer to TN1279, MachXO3 Programming and
Configuration Usage Guide.

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© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02004-1.0 13
MachXO3 Clock Sources
The MachXO3-9400 Development Board has four options for the MachXO3 clock sources:
12 MHz from U1
8 MHz from U7
User defined frequency by installing an oscillator in the Y2 (DNI) footprint
Off board clock source from J10 (DNI)
The 8 MHz clock from U7 is the default clock source when building a Platform Manager design. Note that JP1 should be
installed to power the ASC device.
The 12 MHz clock from the FT2232H FTDI device is another clock source. Its use requires JP11 to be installed to connect
the 12 MHz clock signal to the MachXO3 device I/O. JP9 should not be installed to enable U1.
Table 4.1. JTAG Connections
Clock
Frequency
Signal
Name
MachXO3
Ball
Location
Clock
Source
Comments
8 MHz
ASC_CLK
L1
U7
JP1 installed, test point TP14
12 MHz
12MHz
B10
U1
JP11 installed, JP9 removed
User defined
OSC_IN
D22
Y2 (DNI)
JP4 removed and OSC_EN signal (MachXO3 ball L20) Logic 1.
User defined
OSC_IN
D22
J10 (DNI)
Y2 not installed, or OSC_EN signal (MachXO3 ball L20) Logic 0, or JP4
installed.
Additional information on using optional clock sources:
The board provides for an optional clock input for the MachXO3 from either the Oscillator (Y2) or the SMA header
(J10) as shown in Figure 4.1. Neither of them are populated.
Y2 should be installed by the end user and it should be a 2.5 mm x 2.0 mm 4-SMD package. This is compatible with
the ASDMB serial of the Ultra Miniature Pure Silicon™ Clock Oscillator from Abracon LLC. JP4 can be used to
disable Y2 output by pulling down OSC_EN, which can also be controlled by the L20 pin of MachXO3.
J10 should be installed by the end user. A Complementary Metal-Oxide Semiconductor (CMOS) compatible clock
can then be connected with an SMA cable.
Figure 4.1. Optional Clock Circuit Design
C97
0.1uF
OSC_IN [4]
EXT_CLK
JP4
JUMPER
12
R144
0
1
2
VCCIO1
OSC_IN
Y2
ASDMB-XX.XXXMHz
DNI
VDD
43
OUT
2GND
1
Standby
R145 10K OSC_EN
J10
SMA DNI
1
5

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14 FPGA-EB-02004-1.0
Headers and Test Connections
This section describes the MachXO3-9400 Development Board headers and test connections.
5.1. Versa Headers
The board provides two headers –X2 and X3 for expansion purpose.
Table 5.1. Versa X2 Header Pin Connections
X2 Pin Number
Signal Name
MachXO3 Ball Location
1
GND
—
2
NC
—
3
EXPCON_2V5*
—
4
EXPCON_IO29
E12
5
EXPCON_IO30
D14
6
EXPCON_IO31
C15
7
EXPCON_IO32
C17
8
EXPCON_IO33
D15
9
EXPCON_IO34
C18
10
EXPCON_IO35
D16
11
EXPCON_IO36
C19
12
EXPCON_IO37
D17
13
EXPCON_IO38
D18
14
EXPCON_IO39
C20
15
EXPCON_IO40
E16
16
EXPCON_IO41
E13
17
EXPCON_IO42
F13
18
EXPCON_IO43
F15
19
EXPCON_IO44
G15
20
EXPCON_IO45
G12
21
5VIN*
—
22
GND
—
23
EXPCON_2V5*
—
24
GND
—
25
VCCIO0
—
26
GND
—
27
VCCIO0
—
28
GND
—
29
EXPCON_OSC*
—
30
GND
—
31
EXPCON_CLKIN
A10
32
GND
—
33
EXPCON_CLKOUT
A21
34
GND
—
35
EXPCON_3V3**
—

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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02004-1.0 15
Table 5.1. Versa X2 Header Pin Connections (continued)
X2 Pin Number
Signal Name
MachXO3 Ball Location
36
GND
—
37
EXPCON_3V3**
—
38
GND
—
39
EXPCON_3V3**
—
40
GND
—
Notes:
* Signal is optionally connected to power source through resistor; DNI.
** Signal is optionally connected to power source through resistor; DN.
Table 5.2. Versa X3 Header Pin Connections
X3 Pin Number
Signal Name
MachXO3 Ball Location
1
HPE_RESOUT#
G9
2
GND
—
3
EXPCON_IO0
F8
4
EXPCON_IO1
G8
5
EXPCON_IO2
F9
6
EXPCON_IO3
F7
7
EXPCON_IO4
E7
8
EXPCON_IO5
E6
9
EXPCON_IO6
D5
10
EXPCON_IO7
C3
11
EXPCON_IO8
D6
12
EXPCON_IO9
C4
13
EXPCON_IO10
F10
14
EXPCON_IO11
C5
15
EXPCON_IO12
C6
16
EXPCON_IO13
B12
17
EXPCON_IO14
D7
18
EXPCON_IO15
A12
19
GND
—
20
EXPCON_3V3**
—
21
EXPCON_IO16
D8
22
GND
—
23
EXPCON_IO17
C8
24
GND
—
25
EXPCON_IO18
D9
26
GND
—
27
EXPCON_IO19
E10
28
EXPCON_IO20
C9
29
EXPCON_IO21
G11
30
GND
—
31
EXPCON_IO22
E11

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16 FPGA-EB-02004-1.0
Table 5.2. Versa X3 Header Pin Connections (continued)
X3 Pin Number
Signal Name
MachXO3 Ball Location
32
EXPCON_IO23
D11
33
EXPCON_IO24
F11
34
GND
—
35
EXPCON_IO25
D12
36
EXPCON_IO26
F12
37
EXPCON_IO27
D13
38
CARDSEL#*
—
39
EXPCON_IO28
C14
40
GND
—
Notes:
* Signal is optionally connected to power source through resistor; DNI.
** Signal is optionally connected to power source through resistor; DN.
5.2. Arduino Board GPIO Headers
The board provides four headers –J2, J3, J4 and J5 for Arduino Zero board adaption.
Table 5.3. Arduino J2 Pin Connections
J2 Pin
Number
Signal Name
Arduino ZERO Board
Signal
MachXO3 Ball
Location
Comments
1
AR_IO8
~8
U21
—
2
AR_IO9
~9
U22
—
3
AR_SS_IO10
~10
W20
Optional connection to SS through R67 for SPI access,
DNI by default.
4
AR_MOSI_IO
11
~11
V18
Optional connection to SISPI through R82 for SPI
access, DNI by default.
5
AR_MISO_IO
12
~12
G16
Optional connection to SPISO through R77 for SPI
access, DNI by default.
6
AR_SCK_IO1
3
~13
F17
Optional connection to MCLK through R76 for SPI
access, DNI by default.
7
GND
GND
—
—
8
AR_AREF
AREF
U17
AR_AREF connection to AREF through R43, DNI by
default.
9
AR_SDA
SDA
U19
Optional connection to SDA0 through R44, DNI by
default.
10
AR_SCL
SCL
U18
Optional connection to SCL0 through R45, DNI by
default.

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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02004-1.0 17
Table 5.4. Arduino J3 Pin Connections
J3 Pin
Number
Signal Name
Arduino ZERO Board
Signal
MachXO3 Ball
Location
Comments
1
AR_IO0
RX <- 0
G19
—
2
AR_IO1
TX -> 1
G20
—
3
AR_IO2
2
G21
—
4
AR_IO3
~3
H20
—
5
AR_IO4
~4
G18
—
6
AR_IO5
~5
L21
—
7
AR_IO6
~6
W22
—
8
AR_IO7
7
V22
—
9
AR_SDA
SDA
U19
—
10
AR_SCL
SCL
U18
—
Table 5.5. Arduino J4 Pin Connections
J3 Pin
Number
Signal
Name
Arduino ZERO
Board Signal
MachXO3 Ball
Location
Comments
1
AR_IO
14
ATN
T17
—
2
NC
IOREF
—
—
3
AR_RE
SET
RESET
U20
Pin U20 should be set high by default. Avoid Arduino ZERO
board in Reset status when connected.
4
+3.3V_
AR
3.3 V
—
3.3 V power supply from Arduino ZERO board
5
AR_5V
5 V
—
Jump to 5 V main power through JP6
6
GND
GND
—
—
7
GND
GND
—
—
8
+12V
VIN
—
12 V power supply from Arduino ZERO board
Table 5.6. Arduino J5 Pin Connections
J3 Pin
Number
Signal Name
Arduino ZERO Board
Signal
MachXO3 Ball
Location
Comments
1
AR_AD0
A0
P19
Used as GPIO in digital mode
2
AR_AD1
A1
P18
Used as GPIO in digital mode
3
AR_AD2
A2
P17
Used as GPIO in digital mode
4
AR_AD3
A3
P16
Used as GPIO in digital mode
5
AR_AD4
A4
K22
Used as GPIO in digital mode
6
AR_AD5
A5
G17
Used as GPIO in digital mode
Note:
If JP6 is installed, 5 V power can be supplied from either the Arduino board or the
MachXO3-9400 Development Board. With JP6 removed, both boards need their own
5 V power.

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© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18 FPGA-EB-02004-1.0
5.3. FX12 Headers (DNI)
The board provides two headers –U4 and U5 to connect to FX12 compatible boards or cables. Each header has eight
pairs of Low-Voltage Differential Signaling (LVDS) signals for high speed data receiver.
Table 5.7. FX12 U4 Header Pin Connections
U4 Pin Number
Signal Name
MachXO3 Ball Location
1
CH0_DCK_P
AA10
2
CH0_DCK_N
AB10
3
GND
—
4
CH0_DATA0_P
AA4
5
CH0_DATA0_N
AB4
6
GND
—
7
CH0_DATA2_P
AA5
8
CH0_DATA2_N
AB5
9
GND
—
10
FX_SN*
—
11
FX_SCLK*
—
12
PWR_12V**
—
13
SDA2
AB13
14
SCL2
AA13
15
GND
—
16
CH2_DATA0_P
AA6
17
CH2_DATA0_N
AB6
18
GND
—
19
CH2_DCK_P
AA7
20
CH2_DCK_N
AB7
21
PWR_12V**
—
22
RESETN
AB3
23
PWR_5-0V*
—
24
CH0_DATA1_P
AA2
25
CH0_DATA1_N
AB2
26
PWR_3-3V*
—
27
CH0_DATA3_P
AA8
28
CH0_DATA3_N
AB8
29
PWR_1-8V*
—
30
FX_MOSI*
—
31
FX_MISO*
—
32
PWR_1-8V*
—
33
GND
—
34
GND
—
35
PWR_3-3V*
—
36
CH2_DATA1_P
AA9
37
CH2_DATA1_N
AB9

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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02004-1.0 19
Table 5.7. FX12 U4 Header Pin Connections (continued)
U4 Pin Number
Signal Name
MachXO3 Ball Location
38
PWR_5-0V*
-
39
SDA1
AA11
40
SCL1
AB11
Notes:
* Signal is optionally connected to power source through resistor; DNI.
** 12 V power needs external supply from pin 8 of J4.
Table 5.8. FX12 U5 Header Pin Connections
U5 Pin Number
Signal Name
MachXO3 Ball Location
1
CH1_DCK_P
AB12
2
CH1_DCK_N
AA12
3
GND
—
4
CH1_DATA0_P
AB16
5
CH1_DATA0_N
AA16
6
GND
-
7
CH1_DATA2_P
AB17
8
CH1_DATA2_N
AA17
9
GND
—
10
FX_SN*
—
11
FX_SCLK*
—
12
PWR_12V**
—
13
SDA2
AB13
14
SCL2
AA13
15
GND
—-
16
CH3_DATA0_P
AB18
17
CH3_DATA0_N
AA18
18
GND
—-
19
CH3_DCK_P
AB19
20
CH3_DCK_N
AA19
21
PWR_12V**
—-
22
RESETN
AB3
23
PWR_5-0V*
—-
24
CH1_DATA1_P
AB14
25
CH1_DATA1_N
AA14
26
PWR_3-3V*
—-
27
CH1_DATA3_P
AB15
28
CH1_DATA3_N
AA15
29
PWR_1-8V
—
30
FX_MOSI*
—
31
FX_MISO*
—
32
PWR_1-8V*
—
33
GND
—

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© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20 FPGA-EB-02004-1.0
Table 5.8. FX12 U5 Header Pin Connections (continued)
U5 Pin Number
Signal Name
MachXO3 Ball Location
34
GND
- —
35
PWR_3-3V*
—-
36
CH3_DATA1_P
AB20
37
CH3_DATA1_N
AA20
38
PWR_5-0V*
—-
39
SDA1
AA11
40
SCL1
AB11
Notes:
* Signal is optionally connected to power source through resistor; DNI.
** 12 V power needs external supply from pin 8 of J4.
5.4. Aardvark Header (DNI)
The Aardvark I2C /SPI Host Adapter is a fast and powerful I2C bus and SPI bus host adapter through USB. It allows a
developer to interface a Windows, Linux, or Mac OS X PC through USB to a downstream embedded system
environment and transfer serial messages using the I2C and SPI protocols.
The MachXO3-9400 Development Board provides an Aardvark compatible header for customer applications. The I2C
bus is capable of connecting to a global I2C bus on the board if JP10 is NOT set.
Table 5.9. Aardvark JP2 Header Pin Connections
JP2 Pin Number
Signal Name
MachXO3 Ball Location
1
JP2_SCL
To I2C analog switch U10
2
—
GND
3
JP2_SDA
To I2C analog switch U11
4
+5V_I2C
To VBUS_5V through R78, DNI
5
SPISO
To MachXO3 U9
6
+5V_SPI
To VBUS_5V through R79, DNI
7
MCLK
To MachXO3 T9
8
SISPI
To MachXO3 AA21
9
SS
Multiple options, as shown in Figure 5.1.
10
—
—
Caution:
VCCIO2 should be 3.3 V when connected to Aardvark I2C/SPI Host Adapter.
Pin 9 of the Aardvark header is an SS signal, which is optionally connected to multiple devices or connectors. By default,
it can access Slave SPI in the MachXO3 device as the Master SPI through R160. It can access FX12 header, Raspberry Pi
header and on-board SPI Flash by enabling R161. It can also access the Arduino header by enabling R67.
Figure 5.1. Aardvark SS Pin Connections