Lattice Semiconductor iCE40 UltraPlus User manual

iCE40 UltraPlus Mobile Development
Platform
Evaluation Board User Guide
FPGA-EB-02007 Version 1.1
April 2018

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02007-1.1
Contents
1. Introduction .................................................................................................................................................................4
2. Features .......................................................................................................................................................................5
3. Power and Battery .......................................................................................................................................................8
3.1. Power Source ......................................................................................................................................................8
3.2. Current Measurement Test Points ......................................................................................................................8
3.3. Battery Management and 4.2 V Regulator..........................................................................................................8
4. Clock Sources ...............................................................................................................................................................9
5. Software Requirements .............................................................................................................................................10
6. Demonstrations .........................................................................................................................................................11
6.1. Mobile Display Demonstration on U1 ...............................................................................................................11
6.2. Audio Microphone Demonstrations on U2 .......................................................................................................11
6.3. RGB LED Demonstration on U3 .........................................................................................................................11
6.4. Sensor Demonstrations on U3 ..........................................................................................................................12
6.5. Face Recognition Demonstration on U4 ...........................................................................................................12
7. Board Configuration and Programming.....................................................................................................................14
7.1. Jumpers and Switches .......................................................................................................................................14
7.2. Programming the iCE40 Devices Configuration Memory (CRAM) ....................................................................17
7.3. Programming Onboard SPI Flash.......................................................................................................................18
8. Communication Channels ..........................................................................................................................................20
8.1. USB ....................................................................................................................................................................20
8.2. Bluetooth...........................................................................................................................................................20
9. Ordering Information.................................................................................................................................................20
10. PCB Revision History ..................................................................................................................................................20
References ..........................................................................................................................................................................21
Standards Documents.....................................................................................................................................................21
Lattice Semiconductor Documents.................................................................................................................................21
Technical Support Assistance .............................................................................................................................................21
Appendix A. iCE40 UltraPlus Mobile Development Board Schematics...............................................................................22
Appendix B. iCE40 UltraPlus Mobile Development Board Bill of Materials........................................................................36
Accessories .....................................................................................................................................................................42
Revision History...................................................................................................................................................................43

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02007-1.1 3
Figures
Figure 2.1. iCE40 UltraPlus Mobile Development Platform Board (Top Side) ......................................................................6
Figure 2.2. iCE40 UltraPlus Mobile Development Platform Board (Bottom Side) ................................................................7
Figure 3.1. Power Block Diagram..........................................................................................................................................8
Figure 4.1. Clock Sources for the iCE40 UltraPlus MDP Board .............................................................................................9
Figure 6.1. Rework Resistor Positions Described in Parallel Video Bus Configuration .......................................................13
Figure 7.1. Board Configuration for Programming iCE40 UltraPlus Device “UI” ................................................................15
Figure 7.2. Programming iCE40 Devices on Board..............................................................................................................17
Figure 7.3. Programming SPI Flash on Board......................................................................................................................18
Figure A.1. Block Diagram...................................................................................................................................................22
Figure A.2. iCE40UP5K FPGA A - Display.............................................................................................................................23
Figure A.3. iCE40UP5K FPGA B - Audio ...............................................................................................................................24
Figure A.4. iCE40UP5K FPGA C - Sensor..............................................................................................................................25
Figure A.5. iCE40UP5K FPGA D - Camera............................................................................................................................26
Figure A.6. Common Components- SPI...............................................................................................................................27
Figure A.7. Display Circuitry................................................................................................................................................28
Figure A.8. Audio Circuitry..................................................................................................................................................29
Figure A.9. Sensor & RGB Circuitry .....................................................................................................................................30
Figure A.10. Camera Circuitry .............................................................................................................................................31
Figure A.11. USB Programming ..........................................................................................................................................32
Figure A.12. Power Supplies ...............................................................................................................................................33
Figure A.13. Common Components....................................................................................................................................34
Figure A.14. Battery Connector & Charger .........................................................................................................................35
Tables
Table 7.1. iCE40 UltraPlus Device Selection .......................................................................................................................14
Table 7.2. iCE40 UltraPlus Device Selection Summary .......................................................................................................16

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-EB-02007-1.1
1. Introduction
Thank you for choosing the Lattice iCE40 UltraPlus™Mobile Development Platform (MDP) Board.
This MDP board is an easy-to-use platform for demonstrating various features of the iCE40 UltraPlus for mobile
applications. The MDP form-factor is similar to a mobile device (cell phone), with various sensors, display, Bluetooth
communication, and others. The board contains four individual iCE40 UltraPlus devices, each configured with a unique
set of interfaces to support multiple demonstrations.
Features that can be demonstrated using this board include:
Mobile Display (Onboard 1.54 inch 240 x 240 RGB wearable type display with MIPI DSI interface)
Camera (Onboard VGA 640 x 480 sensor with CSI and parallel video interface option)
Image and facial recognition
Microphones (Onboard Dual I2S and Dual PDM microphones with audio amp, 3.5 mm and expansion connectors)
Voice recognition
Audio beam forming capabilities
Sensors (Various Mobile Type Sensors with expansion connector)
RGB LED
Pressure Sensor
Compass Sensor
Gyroscope Sensor
Accelerometer Sensor
This guide describes how to begin using the MDP. The contents of this user guide include top-level functional
descriptions of the various portions of the evaluation board, a summary of demonstrations, descriptions of the
onboard connectors, switches, jumpers, configuration options, along with a complete set of schematics and the bill of
materials.
Note:
Static electricity can severely shorten the lifespan of electronic components. Be careful
to follow proper ESD prevention handling standards when handling and using the
iCE40 UltraPlus Mobile Development Platform Board.

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02007-1.1 5
2. Features
The iCE40 UltraPlus Mobile Development Platform development kit includes the items below.
iCE40 UltraPlus Mobile Development Platform–PCB, case, and integrated Li-ion battery featuring:
Four iCE40 UltraPlus devices (U1-U4 iCE5UP5K-WLCSP30) in 30-Ball WLCSP packages
Large capacity of onboard SPI Flash memory (U37 Micron M25P80 8Mb) to store the FPGA demo bitstream for
all four iCE40 UltraPlus devices
Example of a PCB design using 0.40 mm Ball Pitch package
Control switches to select which of the four devices is active (only one device is active at a time)
Standard USB cable for device programming (Lattice part number HW-USBN-2A, HW-USBN-2B or equivalent)
RoHS-compliant packaging and process
Key Components
iCE40UP5K-30WLCSP (4 pieces)
Power Regulation
Bluetooth module
MIPI LCD Mobile Display (1.54 inch 240 x 240 RGB LH154Q01)
Camera image sensor OVM7692 VGA 640 x 480 (CSI and parallel video interface option)
Microphones (Dual I2S and Dual PDM microphones with audio amp, connectors for 3.5 mm and expansion)
RGB LED
Sensors that include:
–Barometric pressure sensor
–Compass sensor
–3D accelerometer and 3D gyroscope sensor
–Three-axis linear accelerometer sensor
Pre-loaded Demo –The kit includes a pre-loaded MIPI LCD Mobile Display demo.
USB Connector Cable –A mini-B USB port provides power, a programming interface and communication channel
for a PC to communicate directly to iCE40 devices.

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02007-1.1
Figure 2.1 shows the top side while Figure 2.2 on the next page shows the bottom side of the iCE40 UltraPlus Mobile
Development Platform Board indicating the specific features that are designed on the board.
J2 - MIPI LCD
Display Connector
U1 - iCE40UP5K
(Display Demo)
J19 –Program
iCE40 or Flash
D13 - RGB LED
SW2 - Power SW
J5 - Power Supply
and Programming
J34 –Analog
Audio HP Out
U30 - BLE Module
SW5 –SPI
Bus Switch
U4 - iCE40UP5K
(Camera Demo)
U39 –Image
Sensor
U16 –Camera
Expansion
Connector
Figure 2.1. iCE40 UltraPlus Mobile Development Platform Board (Top Side)

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02007-1.1 7
Battery
U94/19 –I2S
Microphones
U9 –FTDI
(USB to SPI)
U37 –SPI
Flash
U43 –Audio DAC
(I2S to Analog)
U2 –iCE40UP5K
(Audio Demo)
U95/12 –I2S
Microphones
U3 –iCE40UP5K
(Sensor Demo)
U35/22/36/38 –
Various Sensors
in Sensor Demo
Figure 2.2. iCE40 UltraPlus Mobile Development Platform Board (Bottom Side)

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-EB-02007-1.1
3. Power and Battery
3.1. Power Source
The MDP board can be powered by three sources:
External USB Connector J5 (5 V). Green LED D8 and Yellow LED D5 lights up when power is supplied.
External AP Header Connector J16-8 (5 V) and J16-9 (GND). Yellow LED D5 lights up when power is supplied.
Internal 250 mAH Li-ion battery contained internal to the MDP case.
External power from USB connector J5 and AP header connector J16 are 'Diode-ORd'. If power is supplied to both
connectors, the higher voltage powers the board. When external power is not supplied, the internal Li-ion battery
contained in the case powers the board.
Power switch SW2 turns the board ON and OFF by enabling/disabling the main voltage regulator outputs of 3.3 V, 2.5 V, and
1.2 V. Green LED D9 lights up when the 3.3 V rail is active and indicates that the board is powered ON.
USB
J16
CONN
Li-ion
BATT
BQ24232 VSUPPLY 4.2 V
POWER
SWITCH
VREG 3.3 V
VREG 2.5 V
VREG
1.2 V & 1.8 V
VREG
1.5 V & 2.8 V
VREG
1.8 V & 3.0 V
FLASH, BLE,
GYRO, FGDI
VREG LED
BACKLIGHT
FPGAs VPP2V5
FPGAs VCC
FPGAs VCCIO
CAMERA SENSOR
OVM7692
DISPLAY
DIODES 3.3 V
2.5 V
1.2 V
1.8 V
1.5 V
2.8 V
1.8 V
3.0 V
Figure 3.1. Power Block Diagram
3.2. Current Measurement Test Points
Each of the four FPGAs have six 1 Ωresistors in series with their power inputs to allow easy current measurements
using a voltmeter and to ease reworking VCCIO voltage rails. See Appendix A. iCE40 UltraPlus Mobile Development
Board Schematics for details.
3.3. Battery Management and 4.2 V Regulator
Chip BQ24232 U15 provides automatic battery management and the board's 4.2 V regulated voltage rail. The 4.2 V
rail (VSUPPLY) is used to generate all of the board's other voltages. The management chip is always ON (not
controlled by power switch SW2).
When external power is not available, the management chip uses the 250 mAH Li-ion battery internal to MDP case to
generate the 4.2 V rail.
When external 5 V is supplied (4.6 V to 6.0 V), the battery is automatically charged as required. The Green LED D6
lights during charging and turns OFF when charging is complete. Additionally, external power is used to generate the
4.2 V rail. The BQ24232 battery charging is configured with external resistors.
Default resistor configuration:
500 mA input current limit
200 mA charging current
25 mA end of charging termination current threshold
5-hour fast charge time and 30-minute pre-charge

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02007-1.1 9
4. Clock Sources
A 27 MHz oscillator is built on the Mobile Development Platform board. External clock input can also be provided to
this board depending on the J23 settings.
There are six devices sharing the same clock source that are available at the same time. These include four
iCE40UP5K(U1~U4) devices that are responsible for various demos, U43 which is a stereo audio DAC with direct drive
headphone amplifier, and U39 which is an ultra-compact size 640 x 480 image sensor.
Short Pins 2-3 leads the onboard 27 MHz clock to these devices and provides external clock source through Pin 2 and
Pin 3 (GND).
U14
On Board
27 MHz
External
Clock
Source
U1 ICE40UP5K –A
(Display Demo)
U2 ICE40UP5K –B
(Audio Demo)
U3 ICE40UP5K –C
(Sensor Demo)
U4 ICE40UP5K –D
(Camera Demo)
U43 Max9850
(Audio DAC&Amplifier, Audio Demo)
U39 OVM7692
(Image Sensor, Camera Demo)
Figure 4.1. Clock Sources for the iCE40 UltraPlus MDP Board

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-EB-02007-1.1
5. Software Requirements
Install the following software before you begin developing designs for the board:
Lattice iCEcube2 2017.01 (or higher)
Used for developing your own custom designs for the iCE40 UltraPlus FPGA.
Diamond Programmer®3. 8 (or higher)
Used to program the iCE40 UltraPlus FPGA.
These software programs are available at the www.latticesemi.com/software. Make sure you log in to
www.latticesemi.com, otherwise these software downloads will not be visible.

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02007-1.1 11
6. Demonstrations
Four iCE40UP5K-30WLCSP (U1-U4) devices are used on the Mobile Development Platform board. The devices are
responsible for specific demonstrations. Lattice provides separate user guides that describe each demo in detail. The
documents cover board configuration and step-by-step instructions. Please refer to the relevant documents for more
details.
The following sections describe the Mobile Development Platform board demos.
6.1. Mobile Display Demonstration on U1
This demo showcases the ability of iCE40 UltraPlus to drive a small wearable display and buffer one full image frame.
Key components for this demo include:
U1 iCE40UP5K-30WLCSP
J2 Display connector for MIPI LCD display (MIPI LCD Display, 1.4” LH154Q01 is included in the kit.)
U11 Display backlight driver
U13 1.8 V and 3.0 V voltage regulator
Note:
Be careful with the LCD display ribbon, it is fragile and can be damaged!
6.2. Audio Microphone Demonstrations on U2
FPGA U2 is optimized for microphone related demonstrations, such as audio beam. The board contains two I2S
microphones, two PDM microphones, a 3.5 mm audio jack driven by a MAX9850 headphone audio amplifier, and an
expansion connector allowing up to seven microphones used in an array. This demo shows the capability of picking up
human voice and driving the output on the speaker with the same quality, irrespective of where the voice is originating
from within a room.
Key components for this demo include:
U2 iCE40UP5K-30WLCSP
U12/U19 I2S omnidirectional microphone with Bottom Port and Analog Output
U94/U95 PDM omnidirectional microphone with Bottom Port and Analog Output
U43 Audio DAC with headphone amplifier.
J34 3.5 mm audio jack for analog output
J15 Expansion connector supporting up to seven microphones.
J25 Header used to configure FPGA to microphone connections
6.3. RGB LED Demonstration on U3
This demo showcases the capability of ICE40-UltraPlus to control and drive an RGB LED. A mobile app software GUI tool
is provided to allow a user to remotely control the LED via a phone or tablet over Bluetooth. The features of the demo
include:
Ability to control the color of the LED from a color palette.
Ability to control the brightness of the LED.
Ability to control the ON/OFF time of the LED –thereby creating a pulsating breathing effect.
Key components for this demo include:
U3 iCE40UP5K-30WLCSP
D13 RGB LED
U30 Bluetooth Module used for remote control

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-EB-02007-1.1
It is recommended to download the RGB LED software GUI which interfaces with the MDP. This GUI allows you to
control the RGB LED for color, brightness, blinking and ‘breathing’. Download the PC or MAC version of the GUI at
www.latticesemi.com/ice40ultraplusmdp.
6.4. Sensor Demonstrations on U3
This demo showcases the capability of iCE40 UltraPlus to act as a sensor hub.
Key components for this demo include:
U3 iCE40UP5K-30WLCSP.
U22 Digital barometric pressure sensor
U35 High performance e-compass 3D accelerometer and 3D magnetometer
U36 3D accelerometer and 3D gyroscope
U38 3-axis "pico" accelerometer
6.5. Face Recognition Demonstration on U4
This demo showcases the capability of ICE40-UltraPlus to detect and react to a general human face.
Key components for this demo include:
U4 iCE40UP5K-30WLCSP.
U39 Image Sensor OVM7692.
U16 Camera Expansion Connector.
U44 1.5 V and 2.8 V voltage regulator.
This demo uses the VGA (640 x 480) sensor OVM7692 U39 or the camera expansion connector U16. The default
interface uses CSI2, however, the interface can be configured for 3.3 V parallel video interface to support the facial
recognition demo with the following rework:
1. Remove resistors: R15, R29, R30, R47, R73, R90, R91, R100, R125, R126, R127, R142, R143, R149, R150, R154,
R155.
2. Install 0 Ω resistors (or short with solder blob): R31, R32, R43, R52, R53, R54, R55, R56.
3. Verify resistors installed: R22, R159, R160.
4. If using Xtal U14 as clock source Jumper J23-2 and 3 else J23-2 should be open.

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02007-1.1 13
Figure 6.1 shows the resistors of the rework. Resistors highlighted in red rectangle need to be removed; resistors
highlighted in green rectangle need to install 0 Ωresistors; blue highlights show the resistors needing installation
verification.
J23
U14 Xtal
U4 iCE40
U39 OVM7692
U16
Camera
Connector
J33
R142
U37
Flash
Figure 6.1. Rework Resistor Positions Described in Parallel Video Bus Configuration

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14 FPGA-EB-02007-1.1
7. Board Configuration and Programming
The iCE40 UltraPlus Mobile Development Board has four iCE40 devices. Each device serves specific demo purposes. As there
is only one USB to SPI bridge chip used onboard, programming different iCE40 devices can be completed using combinations
of jumper and switch settings. The installed jumpers used on the MDP board have a 2 mm pin-pitch, not the standard 100-mil
style.
7.1. Jumpers and Switches
The iCE40 UltraPlus Mobile Development Board has the following jumpers:
J19
Set these for either SPI Flash programing (both vertical) or SRAM (iCE40) programming (both horizontal), per the
silkscreen markings on the board.
J17
To program the iCE40 UltraPlus device U1, short pins 1-2. To program any other device on the board, short pins 9-10.
Note: Follow the silkscreen markings on the board, pins 1-2 are at the top of this header bank.
J25
To program the iCE40 UltraPlus device U2, short pins 1-2. To program any other device on the board, short pins 11-12.
Note: Follow the silkscreen markings on the board, pins 1-2 are at the bottom of this header bank.
J26
To program the iCE40 UltraPlus device U3, short pins 1-2. To program any other device on the board, short pins 9-10.
Note: Follow the silkscreen markings on the board, pins 1-2 are at the bottom of this header bank.
J27
To program the iCE40 UltraPlus device U4, short pins 1-2. To program any other device on the board, short pins 9-10.
Note: Follow the silkscreen markings on the board, pins 1-2 are at the top of this header bank.
J28
If you are doing SPI Flash programming, short pins 1-2. Otherwise, leave all pins open.
The iCE40 UltraPlus Mobile Development Board has the following switches:
SW5
This selects the target iCE40 UltraPlus device. Refer to Table 7.1 to select the correct device.
Table 7.1. iCE40 UltraPlus Device Selection
iCE40 UltraPlus
FPGA
Key Supported Features
SW5 (2,1)
Reference Image
U1
Display frame buffer: 240x240 display 18-bit color (R6,G6,B6),
MIPI DSI interface
OFF, OFF
U2
On-board stereo microphones (I2S and PDM): 7-microphone
expansion connector, headphone amp, audio output jack
OFF, ON
U3
Sensors: RGB LED, Pressure Sensor, Gyroscope,
Accelerometer, Compass
ON, OFF
U4
640x480 VGA Camera, MIPI CSI interface, expansion connector
utilizing single MIPI data lane
ON, ON
Use the marking on switch to determine SW5-1 and SW5-2 orientations, including the ‘ON’ direction.

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02007-1.1 15
SW9
This switch is used to add/remove the BLE module from the SPI bus. It is recommended that the BLE module be
removed from the SPI bus when the module is not in demo use.
Figure 7.1 shows the setting of jumpers and switches while trying to program iCE40 device “U1”directly.
J17 –Short pins 1-2
programming iCE40
device UI
SW2 –Slide on to
power on board
J5 –Power Supply
and Programming
J25 –Short pins 11-12
J17 –Short pins 1-2
programming iCE40
device UI
J19 –Put jumpers
horizontal to directly
program iCE40 device
J26 –Short pins 9-10
J27 –Short pins 9-10
J28 –Short pins 1-2
to program SPI Flash
SW9 –Set all pins in
SW9 to OFF to remove
BLE from SPI Bus
SW5 –Set 2 pins both
to OFF to select iCE40
device “UI”
Figure 7.1. Board Configuration for Programming iCE40 UltraPlus Device “UI”

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16 FPGA-EB-02007-1.1
Table 7.2. iCE40 UltraPlus Device Selection Summary
SPI Flash
Demux
CRESET Boot Control Jumper Placement
Section
iCE40 UltraPlus
RefDes
SW5 (2,1)
J17
J25
J26
J27
Camera
U1
OFF,OFF
1-2
11-12
9-10
9-10
Audio
U2
OFF, ON
9-10
1-2
9-10
9-10
Sensor/RGB
U3
ON, OFF
9-10
11-12
1-2
9-10
Display
U4
ON, ON
9-10
11-12
9-10
1-2

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02007-1.1 17
7.2. Programming the iCE40 Devices Configuration Memory (CRAM)
To program iCE40 UltraPlus devices’ CRAM in Diamond Programmer:
1. Set board jumpers on J19 horizontally for CRAM programming.
2. Remove board jumper J28: 1-2 for CRAM programming.
3. Use Diamond Programmer 3.8 or later.
4. Connect the iCE40 UltraPlus Mobile Development Platform board via the USB cable to a PC or MAC.
5. Start Diamond Programmer.
6. Set Device Family to iCE40 UltraPlus” and Device to “iCE40UP5K”. Refer Figure 7.2 below.
7. Be sure to perform the “Program, Verify” operation. If you select only the “Program” operation, you may get a false
positive that the device has programmed.
8. Field Programming Speed Settings should be set to “Use customer Clock Divider” and appropriate value “5” should
be set in the text box below.
9. Open the Device Properties dialog. Apply the settings highlighted.
10. Access mode: set to “CRAM programming” to allow directly programming iCE40 devices.
11. Operation: set to “Fast Program” mode.
12. Programming File: load bit stream file for demo.
13. Click OK to exit Device Properties dialog.
14. Click the Program button in Diamond Programmer to download the bit stream file.
Figure 7.2. Programming iCE40 Devices on Board

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18 FPGA-EB-02007-1.1
7.3. Programming Onboard SPI Flash
To program SPI flash in Diamond Programmer:
1. Set board jumpers on J19 vertically for SPI Flash programming.
2. Install board jumper J28: 1-2 for SPI Flash programming.
3. Start Diamond Programmer.
4. Set Device Family to iCE40 UltraPlus” and Device to “iCE40UP5K”.
5. Be sure to do the “Program, Verify” operation. If you select only the “Program” operation, you may get a false
positive that the device has programmed.
6. Field Programming Speed Settings should be set to “Use customer Clock Divider” and appropriate value “5” should
be set in the text box below.
7. Open the Device Properties dialog. Apply the settings highlighted.
Access mode: set to “SPI Flash Programming”.
Operation: set to “SPI Flash Erase, Program, Verify” mode.
Programming File: load bit stream file for demo.
SPI Flash Options: select correct Flash chip as shown in Figure 7.3 blow.
Load from File button should be used to refresh fields such as “Data file size”and “End address(Hex)”.
8. Click OK to exit Device Properties dialog.
9. Click the Program button in Diamond Programmer to download the bit stream file.
Figure 7.3. Programming SPI Flash on Board

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02007-1.1 19
The main differences between programming ICE40 UltraPlus devices and programming SPI Flash are:
1. Board jumpers on J19: Vertical for CRAM programming and horizontal for SPI Flash programming.
2. Board jumpers J28: 1-2: Remove for CRAM programming and install for SPI Flash programming.
3. The settings in the Device Properties dialog box in Diamond Programmer.
For more information on Diamond Programmer, please refer to its user guide.

iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20 FPGA-EB-02007-1.1
8. Communication Channels
To enable communication with external tools, devices or Apps on Smart phone, this board features a number of
communication channels.
8.1. USB
A USB cable from PC needs to be connected to J5 on board. This communication channel through U9 (FT2232H) is
mainly used for programing the SPI flash on board, or program the ICE devices directly depends on settings on jumper
J19.
8.2. Bluetooth
This board features a Bluetooth module U30 to enable wireless communication with external devices like smart
phones, which is very useful while need to run some APPs on smart phone in demos. This Bluetooth provide UART
channel to communicate with ICE40 devices on board.
The operating range of the BLE module is up to 100 meters.
9. Ordering Information
Description
Ordering Part Number
China RoHS Environment- Friendly Use Period (EFUP)
iCE40 UltraPlus Mobile Development Platform
iCE40UP5K-MDP-EVN
10. PCB Revision History
PCB Revision
Notes
Rev A, Rev B
Prototype revisions, unreleased
Rev C
Production revision
Includes two wires added during assembly to connect the UART of the FT2232HL to test
points. Specifically, these are U9-38 to J33-1 and U9-39 to J33-3.
Rev D
Production revision
Implements the wires from Rev C as PCB traces.
Rev C and Rev D schematics are identical.