Lattice Semiconductor ECP5-5G User manual

ECP5-5G™ Versa Development Board User Guide
EB103 Version 1.2, January 2016

2
ECP5-5G Versa Development Board
Introduction
The ECP5-5G™ Versa Development Board allows designers to investigate and experiment with the features of the
ECP5-5G Field-Programmable Gate Array. The features of the ECP5-5G Versa Development Board can assist
engineers with rapid prototyping and testing of their specific designs. The ECP5-5G Versa Development Board is
part of the ECP5-5G Versa Development Kit. The guide is intended to be referenced in conjunction with demo user
guides to demonstrate the ECP5-5G FPGA.
Figure 1. ECP5-5G Versa Development Board, Top Side
USB Programming
JTAG
Interface
PCI Express x1
On-Board
Clock
Management
12 V DC
Power Input
Expansion Connectors
DDR3
Memory
SERDES Test
SMA Connectors
LED
Display
Push-buttons
User
Switches
Status LEDs
SPI Flash
Configuration
Memory
Configuration
Mode Switches
ECP5-5G
Device
JTAG Chain
Selector
Dual RJ45
Ethernet Ports
Dual RJ45
Ethernet Ports
Features
• Half-length PCI Express form-factor
— Allows demonstration of PCI Express x1 interconnection
• Electrical testing of one full-duplex SERDES channel via SMA connections
• USB-B connection for UART and device programming
• Two RJ45 interfaces to 10/100/1000 Ethernet to RGMII
• On-board Boot Flash
— 128M Serial SPI Flash
• DDR3-1866 memory components (64Mb/x16)
• Expansion mezzanine interconnection for prototyping
• 14-segment alpha-numeric display
• Switches, LEDs and displays for demo purposes
•Diamond
®programming support
• On-board reference clock sources

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ECP5-5G Versa Development Board
The contents of this user guide include top-level functional descriptions of the various portions of the evaluation
board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics.
Caution: The ECP5-5G Versa Development Board contains ESD-sensitive components. ESD safe practices
should be followed while handling and using the evaluation board.
ECP5-5G Device
This board features an ECP5-5G FPGA with a 1.2 V core supply. It can accommodate all pin-compatible ECP5-5G
devices in the 381 ball caBGA package. A complete description of this device can be found in DS1057, ECP5-5G
Family Data Sheet.
Note: The connections referenced in this document refer to the LFE5UM5G-45F-8BG381C device.
Applying Power to the Board
The ECP5-5G Versa Development Board is ready to power on. The board can be supplied with power from a PCI
Express host system or standalone with an external wall power module.
The 12 V DC input power source is fused with a surface mounted fuse, as noted in Ta bl e 1.
Table 1. Board Power Supply Fuses (See Appendix A, Sheet 2, Figure 14- Voltage Regulators)
Fuse Designator Description
F1 12 V Input Supply Fuse
The board may be plugged into a host PC. Only plug the board into a PCI Express slot when the system is powered
off. Once inserted, the PC can be safely powered on.
Using the evaluation board outside of a PC chassis supply requires the factory-supplied wall supply module. Use of
other supplies is not suggested.
Figure 2. Power Distribution Scheme (See Appendix A, Sheet 2, Figure 14- Voltage Regulators)
12 V, 5 A fused
Status LED: D13
VCC Core: 1.2 V, 1.35 A
Status LED: D10
1.5 V, 1.1 A
Status LED: D11
3.3 V, 1.35 A
Status LED: D9
2.5 V, 1.1 A
Status LED: D31
SERDES VCCHTX0: 1.2 V, 0.5 A
SERDES VCCA0: 1.1 V, 0.5 A
Status LED: D12
SW
EN
SW
EN
LDO
SW
EN
SW
EN
LDO

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ECP5-5G Versa Development Board
Programming/FPGA Configuration
The ECP5-5G Versa Development Board has a built-in download controller for programming the ECP5-5G FPGA.
The built-in module consists of a USB Type-B connector and a USB UART device. To use the built-in download
cable, simply connect a standard USB cable (a USB-B to USB-A cable is included with the ECP5-5G Versa Devel-
opment Kit) from J2 to your PC (with Diamond programming software installed). The USB hub on the PC will detect
the addition of the USB function, making the built-in cable available for use with the Diamond programming soft-
ware. The USB cable is connected in parallel to J3.
Alternate Programmer Download Interface
J3 is a 10 pin JTAG connector that is provided for use with an external Lattice download cable (available sepa-
rately). A USB download cable can be attached to the board using J3 to interface with the FPGA (U1).
Note: Resistors R38, R33, R32 and R36 need to be removed for programming with J3.
The same interface can be used to access the ispClock 5406D clock device (U13) by reconfiguring the jumpers on
J50 (See Appendix A, Sheet 3, Figure 15 - Programming). U13 is factory-programmed for use with the reference
designs and should only be altered for customized designs.
Table 2. JTAG Connector Pinout (J3) (See Appendix A, Sheet 3, Figure 15 - Programming)
Pin Function
1PWR
2TDO
3TDI
4PROGRAMn
5 N/C
6TMS
7GND
8TCK
9DONE
10 INITn
Diamond Programmer Requirements
Note: This board includes the built-in download module and only requires the USB cable included with the board.
After initial board setup, use the following procedure to program the board. Instructions assume that Diamond Pro-
grammer software has been installed on a local PC.
Requirements:
• PC with Diamond Programmer 3.5.1 (or later) programming software, installed with appropriate drivers (USB
driver for USB cable).
Note: An option to install these drivers is included as part of the Diamond Programmer setup.

5
ECP5-5G Versa Development Board
Setting the Configuration Mode
The ECP5-5G device on the ECP5-5G Versa Development Board supports a variety of configuration modes,
including 1149.1 JTAG and Master SPI. Refer to TN1260, ECP5 and ECP5-5G sysCONFIG Usage Guide. On the
PCB, use the CFG Setting Dip Switch SW4 described in Ta b l e 3.
Note: SW4.4 is unused.
Figure 3. SW4
Table 3.
Configuration Mode CFG[2:0] SW4.3 SW4.2 SW4.1
1149.1 JTAG only 000 Down Down Down
Slave SPI 001 Down Down Up
Master SPI 010 Down Up Down
SCM (Slave_Serial) 101 Up Down Up
SCM (Slave_Parallel) 111 Up Up Up
CFG[2:0] Selection
Board Programming
The ECP5-5G programmable devices can be programmed using a computer running Lattice Diamond or Lattice
Diamond Programmer software connected to the Development board via a standard mini-USB cable. Refer to the
ECP5-5G Versa Development Kit Quick Start Guide (QS039) for more details. Once the programming software is
installed and the USB cable is connected to the board, the programmable devices can be programmed.
Figure 4. J50
The ECP5-5G FPGA (U1) and the ispClock5406D (U13) device can be programmed individually or together. JTAG
Chain Selector Header J50 is used to select which device(s) will be connected to the JTAG programming bus. The
ECP5-5G FPGA SRAM can be programmed directly, or the subtended configuration serial SPI flash (U52) pro-
grammed, via the same J50 setting. See Tabl e 4 and the diagrams below.

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ECP5-5G Versa Development Board
Table 4. JTAG Chain Selector
J50 Shunts JTAG Chain
1-2, 3-4, 5-6 ECP5-5G + ispClock
1-2, 3-5 ECP5-5G only
2-4, 5-6 ispClock only
Figure 5. J50 Settings
ECP5-5G +
ispCLOCK
ECP5-5G
only
ispCLOCK
only
Figure 6. ECP5-5G Status LEDs and Push-button Controls
The LEDs indicate the configuration status of the ECP5-5G FPGA.
•D17 (red) illuminated indicates that programming was aborted or reinitialized, driving the INITN output low.
•D20 (green) illuminated indicates the successful completion of configuration by releasing the open collector
DONE output pin.
•D19 (red) illuminated indicates that PROGRAMN is low.
•D18 (red) illuminated indicates that GSRN is low.

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ECP5-5G Versa Development Board
PROGRAMN and GSRN
These push-button switches assert/de-assert the logic levels on PROGRAMN (SW2) and GSRN (SW1). Depress-
ing the button drives a logic level “0” to the device.
Programming Serial SPI Flash Memory
A serial SPI (16-pin TSSOP, 128M) Flash memory device (U52) is on-board for non-volatile configuration memory
storage. A Micron N25Q128A device is populated on-board.
The Serial SPI Flash memory device can be configured easily via the ECP5-5G JTAG port. This mode enables the
FPGA to be programmed at power-up or assertion of PROGRAMN with a bitstream stored in the memory device.
1. Connect the ECP5-5G Versa Development Board.
2. Set J50 jumper to ECP5-5G only programming (See the Board Programming section.)
3. Scan the board or select the LFE5UM5G-45F device in the ECP5UM5G device family.
4. From the Edit pull down menu select Device Properties. Set the Access mode to SPI Flash Background Pro-
gramming and Operation to SPI Flash Erase, Program, Verify.
Figure 7. Diamond Programmer Main Screen
5. Under the SPI Flash Options, select Family to SPI Serial Flash, Vendor to Micron, Device to SPI-N25Q128A,
Package to 16-pin SO16.

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ECP5-5G Versa Development Board
Figure 8. Device Properties Dialog Box
6. Click OK in the Device Properties dialog box. You will return to the main configuration screen.
7. From the main programming window, select Program from the top toolbar. This begins the SPI Serial Flash
programming. Note that the SPI Flash Background Programming operation is only possible when the ECP5-5G
device is either erased or the active design has the MASTER_SPI_PORT mode enabled. For more details see
TN1260, ECP5 and ECP5-5G sysCONFIG Usage Guide.

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ECP5-5G Versa Development Board
On-Board Clock Capabilities
(See Appendix A, Sheet 9, Figure 21 - Reference Clock Generator)
The ECP5-5G Versa Development Board allows for several clock source options. Some of these options are con-
trolled via the ispClock5406D programmable clock manager device. The ispClock5406D enables the reference
clock from the PCI Express interface to provide a reference clock to the SERDES. This is true only when the board
is in a PCI Express host socket. When the board is not in a PCI Express host socket, the clock will be supplied by a
156.25 MHz clock on-board oscillator. Both clock inputs can be fanned out to the dedicated SERDES reference
inputs, FPGA inputs, and to the expansion connectors. The factory default programming provides a variety of
clocks to the SERDES and FPGA inputs to support Factory defined 5G applications. The ispClock chip may be pro-
grammed with user defined configurations to support a wide range of user applications.
Figure 9. Clock Controller Scheme
PLL
ispClock5406D (U13)
156.25MHz OSC
(X2)
100MHz PCIe CLK
(CN1)
PCIe PRSNT#
(J4)
BANK3
BANK2
BANK1
19/18
16/15
45
BANK0
48
LOCK#
MULTx2
MULTx1
REFCLK_D0
(U1:Y11/Y12)
35/34
PCLK0
(U1:A4/A5)
31/30
EXPCON_OSC
(X3:29)
27/26
REFCLK_D1
(U1:Y19/W20)
10/11
+
REFB
REFA
USER3
USER0
D30
0
1

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ECP5-5G Versa Development Board
General Purpose Clock Source
An on-board 100 MHz LVDS oscillator is provided for general purpose use. This clock source is connected to differ-
ential inputs P3 and P4 and must be used as LVDS inputs to the FPGA. This pin pair also provides optimal inter-
face to the FPGA PLL for customized use.
The PCI Express add-in card specification requires add-in boards to include capabilities to tell the host of its pres-
ence. The ECP5-5G Versa Development Board allows this optional connection via a board jumper. Using the board
with a PCI Express host requires the setting shown in Figure 10 below.
Figure 10. PCI Express PRSNT Control Connection
J4
1 2
3 4
5 6
PCI Express PRSNT
Jumper Selector
SERDES
The ECP5-5G Dual Channel Unit (DCU) SERDES FPGA is utilized on the board for several purposes. DCU0,
Channel 0 is provisioned to provide a single, full-duplex PCI Express channel. The high-speed signals are con-
nected to the PCI Express edge connection. DCU0, Channel 1 is connected to the SMA connectors for external
electrical demonstrations.
Table 5. PCI Express Channel Interconnections
Signal Name SERDES Port FPGA Ball Number
PETp0 HDRXP0_D0CH0 Y5
PETn0 HDRXN0_D0CH0 Y6
PERp0 HDTXP0_D0CH0 W4
PERn0 HDTXN0_D0CH0 W5
Table 6. SMA Test Interconnections
Connector SERDES Port FPGA Ball Number
J5 HDRXP0_D0CH1 Y7
J6 HDRXN0_D0CH1 Y8
J7 HDTXP0_D0CH1 W8
J8 HDTXN0_D0CH1 W9